TWI826107B - Pixel circuit and driving method thereof - Google Patents
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/06—Adjustment of display parameters
- G09G2320/0626—Adjustment of display parameters for control of overall brightness
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
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Abstract
Description
本發明是有關於一種顯示裝置,且特別是有關於一種畫素電路及其驅動方法。 The present invention relates to a display device, and in particular, to a pixel circuit and a driving method thereof.
在習知的顯示技術中,顯示面板容易受到畫素電路中的電晶體的臨界電壓(Threshold Voltage)變異影響,進而降低了顯示畫面的顯示品質。 In the conventional display technology, the display panel is easily affected by variations in the threshold voltage (Threshold Voltage) of the transistors in the pixel circuit, thereby reducing the display quality of the display image.
另外,在畫素電路操作於不同灰階程度的顯示畫面(例如,低灰階狀態或高灰階狀態)下,當驅動電晶體的導通電流皆處於大電流狀態,且發光元件長時間的被點亮時,將會使得畫素電路整體的功率消耗過高。此外,畫素電路中的系統低電壓也容易受到傳遞路徑的線阻影響,導致每一畫素的端點電壓不同,進而使得每一畫素中流經發光元件的導通電流會發生誤差。 In addition, when the pixel circuit operates in a display screen with different grayscale levels (for example, a low grayscale state or a high grayscale state), when the on-current of the driving transistor is in a large current state, and the light-emitting element is used for a long time. When lit, the overall power consumption of the pixel circuit will be too high. In addition, the system low voltage in the pixel circuit is also easily affected by the line resistance of the transmission path, resulting in a different terminal voltage of each pixel, which in turn causes an error in the conduction current flowing through the light-emitting element in each pixel.
有鑑於此,如何改善電晶體的臨界電壓變異影響,並且在畫素電路操作於不同灰階程度的顯示畫面下,有效地降低畫素電路的功率消耗,以提升顯示畫面的顯示品質,將是本領域相關 技術人員重要的課題。 In view of this, how to improve the influence of the variation of the critical voltage of the transistor and effectively reduce the power consumption of the pixel circuit when the pixel circuit operates in a display screen with different grayscale levels, so as to improve the display quality of the display screen, will be Relevant to this field Important topics for technicians.
本發明提供一種畫素電路及其驅動方法,其能夠在不同的操作模式下,有效地降低整體的功率消耗,並改善電晶體的臨界電壓變異問題,以提升顯示畫面的顯示品質。 The present invention provides a pixel circuit and a driving method thereof, which can effectively reduce the overall power consumption in different operating modes and improve the critical voltage variation problem of transistors to improve the display quality of the display screen.
本發明的畫素電路包括驅動電路、第一電壓調整器以及第二電壓調整器。驅動電路依據發光控制信號以產生導通電流。第一電壓調整器具有第一控制端,第一電壓調整器耦接至驅動電路,依據發光控制信號、第三源極驅動信號、第一資料電壓以及參考電壓以調整第一控制端的電壓準位,並依據第一控制端的電壓準位以產生第一驅動電流。第二電壓調整器具有第二控制端,第二電壓調整器耦接至驅動電路,依據第一源極驅動信號、第二源極驅動信號、第四源極驅動信號、第二資料電壓以及參考電壓以調整第二控制端的電壓準位,並依據第二控制端的電壓準位以產生第二驅動電流。其中,於第一操作模式下,導通電流的大小為第一驅動電流的電流值,於第二操作模式下,導通電流的大小為第一驅動電流以及第二驅動電流的總和的電流值。 The pixel circuit of the present invention includes a driving circuit, a first voltage regulator and a second voltage regulator. The driving circuit generates conduction current according to the lighting control signal. The first voltage regulator has a first control terminal. The first voltage regulator is coupled to the driving circuit and adjusts the voltage level of the first control terminal according to the lighting control signal, the third source driving signal, the first data voltage and the reference voltage. , and generate the first driving current according to the voltage level of the first control terminal. The second voltage regulator has a second control terminal. The second voltage regulator is coupled to the driving circuit. According to the first source driving signal, the second source driving signal, the fourth source driving signal, the second data voltage and the reference The voltage is used to adjust the voltage level of the second control terminal and generate the second driving current according to the voltage level of the second control terminal. Wherein, in the first operating mode, the magnitude of the on-current is the current value of the first driving current, and in the second operating mode, the magnitude of the on-current is the current value of the sum of the first driving current and the second driving current.
本發明的畫素電路的驅動方法,包括:使驅動電路依據發光控制信號以產生導通電流;使第一電壓調整器依據發光控制信號、第三源極驅動信號、第一資料電壓以及參考電壓以調整第一電壓調整器的第一控制端的電壓準位,並依據第一控制端的電 壓準位以產生第一驅動電流;使第二電壓調整器依據第一源極驅動信號、第二源極驅動信號、第四源極驅動信號、第二資料電壓以及參考電壓以調整第二電壓調整器的第二控制端的電壓準位,並依據第二控制端的電壓準位以產生第二驅動電流;以及於第一操作模式下,使導通電流的大小為第一驅動電流的電流值,於第二操作模式下,使導通電流的大小為第一驅動電流以及第二驅動電流的總和的電流值。 The driving method of the pixel circuit of the present invention includes: causing the driving circuit to generate an on-current according to the lighting control signal; causing the first voltage regulator to generate a conductive current according to the lighting control signal, the third source driving signal, the first data voltage and the reference voltage. Adjust the voltage level of the first control terminal of the first voltage regulator, and adjust the voltage level of the first control terminal according to the voltage level of the first control terminal. voltage level to generate a first driving current; causing the second voltage regulator to adjust the second voltage according to the first source driving signal, the second source driving signal, the fourth source driving signal, the second data voltage and the reference voltage. The voltage level of the second control terminal of the regulator is used to generate the second driving current according to the voltage level of the second control terminal; and in the first operating mode, the magnitude of the conduction current is the current value of the first driving current, and In the second operation mode, the magnitude of the conduction current is the current value of the sum of the first driving current and the second driving current.
基於上述,本發明諸實施例所述畫素電路可以於低灰階顯示狀態時,僅透過主要的電壓調整器來決定發光元件的發光亮度,而於高灰階顯示狀態時,透過額外的電壓調整器與主要的電壓調整器共同決定發光元件的發光亮度。如此一來,畫素電路可以透過兩條電流路徑來控制顯示畫面的灰階狀態,以降低系統高電壓以及系統低電壓之間的跨壓,並達到改善功率消耗的效果。 Based on the above, the pixel circuits described in the embodiments of the present invention can only use the main voltage regulator to determine the luminous brightness of the light-emitting element in the low-grayscale display state, and use an additional voltage in the high-grayscale display state. The regulator and the main voltage regulator jointly determine the brightness of the light-emitting element. In this way, the pixel circuit can control the grayscale state of the display screen through two current paths to reduce the cross-voltage between the system high voltage and the system low voltage, and achieve the effect of improving power consumption.
100:畫素電路 100: Pixel circuit
110:驅動電路 110: Drive circuit
120、130:電壓調整器 120, 130: Voltage regulator
C1~C3:電容器 C1~C3: capacitor
CT1、CT2:控制端 CT1, CT2: control terminal
CP:補償階段 CP: Compensation stage
EM:發光控制信號 EM: Luminous control signal
EP:發光階段 EP: Glowing Stage
EP1、EP2:子階段 EP1, EP2: sub-stage
ID:導通電流 ID: conduction current
I1、I2:驅動電流 I1, I2: drive current
LED:發光元件 LED: light emitting element
P1、P2:節點 P1, P2: nodes
RP:重置階段 RP: reset phase
S1~S4:源極驅動信號 S1~S4: source drive signal
S510~S540:步驟 S510~S540: steps
T1~T9:電晶體 T1~T9: Transistor
TD:驅動電晶體 TD: drive transistor
TFR:畫素期間 TFR: pixel period
TP:截止階段 TP: deadline stage
VREF:參考電壓 VREF: reference voltage
VL:低電壓 VL: low voltage
VSS:系統低電壓 VSS: system low voltage
VDD:系統高電壓 VDD: system high voltage
VDATA1、VDATA2:資料電壓 VDATA1, VDATA2: data voltage
VGH:閘極高電壓 VGH: gate high voltage
VGL:閘極低電壓 VGL: gate low voltage
圖1是依照本發明一實施例的畫素電路的示意圖。 FIG. 1 is a schematic diagram of a pixel circuit according to an embodiment of the present invention.
圖2是依照本發明圖1實施例的畫素電路操作於第一以及第二操作模式時的時序圖。 FIG. 2 is a timing diagram of the pixel circuit operating in the first and second operating modes according to the embodiment of FIG. 1 of the present invention.
圖3A至圖3D是依照本發明圖1實施例的畫素電路操作於第一操作模式時的等效電路圖。 3A to 3D are equivalent circuit diagrams of the pixel circuit according to the embodiment of FIG. 1 operating in the first operating mode.
圖4A至圖4D是依照本發明圖1實施例的畫素電路操作於第 二操作模式時的等效電路圖。 4A to 4D illustrate the pixel circuit operating in the third embodiment according to the embodiment of FIG. 1 of the present invention. Equivalent circuit diagram in two operating modes.
圖5是依照本發明一實施例的畫素電路的驅動方法的流程圖。 FIG. 5 is a flow chart of a driving method of a pixel circuit according to an embodiment of the present invention.
在本案說明書全文(包括申請專利範圍)中所使用的「耦接(或連接)」一詞可指任何直接或間接的連接手段。舉例而言,若文中描述第一裝置耦接(或連接)於第二裝置,則應該被解釋成該第一裝置可以直接連接於該第二裝置,或者該第一裝置可以透過其他裝置或某種連接手段而間接地連接至該第二裝置。另外,凡可能之處,在圖式及實施方式中使用相同標號的元件/構件/步驟代表相同或類似部分。不同實施例中使用相同標號或使用相同用語的元件/構件/步驟可以相互參照相關說明。 The term "coupling (or connection)" used throughout the specification of this case (including the scope of the patent application) can refer to any direct or indirect connection means. For example, if a first device is coupled (or connected) to a second device, it should be understood that the first device can be directly connected to the second device, or the first device can be connected through other devices or other devices. A connection means is indirectly connected to the second device. In addition, wherever possible, elements/components/steps with the same reference numbers are used in the drawings and embodiments to represent the same or similar parts. Elements/components/steps using the same numbers or using the same terms in different embodiments can refer to the relevant descriptions of each other.
圖1是依照本發明一實施例的畫素電路的示意圖。請參照圖1,在本實施例中,畫素電路100包括驅動電路110、電壓調整器120以及電壓調整器130。其中,驅動電路110包括驅動電晶體TD以及發光元件LED。驅動電晶體TD的第一端耦接至電壓調整器120以及電壓調整器130,驅動電晶體TD的控制端接收發光控制信號EM。發光元件LED的陽極端耦接至驅動電晶體TD的第二端,發光元件LED的陰極端耦接至系統低電壓VSS。
FIG. 1 is a schematic diagram of a pixel circuit according to an embodiment of the present invention. Please refer to FIG. 1 . In this embodiment, the
具體而言,本實施例的驅動電路110可以依據發光控制信號EM的狀態來產生導通電流ID,並且驅動電路110可以依據
導通電流ID來對應地點亮發光元件LED。其中,本實施例的發光元件LED可以例如是有機發光二極體(Organic Light Emitting Diode,OLED)、次毫米發光二極體(mini LED)或其他微型發光元件,本發明並未特別限制。
Specifically, the driving
電壓調整器120耦接至驅動電路110。電壓調整器120包括電晶體T1~T5以及電容器C1。電晶體T1的第一端耦接至系統高電壓VDD,電晶體T1的第二端耦接至節點P1,電晶體T1的控制端接收發光控制信號EM。電晶體T2(亦即,開關電晶體)的第一端耦接至系統高電壓VDD,電晶體T2的第二端耦接至驅動電路110,電晶體T2的控制端耦接至控制端CT1。電晶體T3的第一端耦接至參考電壓VREF,電晶體T3的第二端耦接至控制端CT1,電晶體T3的控制端接收源極驅動信號S3。電晶體T4的第一端耦接至節點P1,電晶體T4的控制端接收源極驅動信號S3。電晶體T5的第一端接收源極驅動信號S2,電晶體T5的第二端耦接至電晶體T4的第二端,電晶體T5的控制端耦接至資料電壓VDATA1。電容器C1耦接於控制端CT1以及節點P1之間。
The
具體而言,本實施例的電壓調整器120可依據發光控制信號EM、源極驅動信號S3、資料電壓VDATA1以及參考電壓VREF以調整電晶體T2的控制端(亦即,控制端CT1)的電壓準位。並且,電壓調整器120可在畫素電路100操作於第一操作模式以及第二操作模式的發光階段時,依據控制端CT1的電壓準位以產生驅動電流I1至驅動電路110。
Specifically, the
在另一方面,電壓調整器130包括電晶體T6~T9以及電容器C2~C3。電晶體T6的第一端耦接至資料電壓VDATA2,電晶體T6的第二端耦接至節點P2,電晶體T6的控制端接收源極驅動信號S4。電晶體T7的第一端耦接至低電壓VL,電晶體T7的第二端耦接至控制端CT2,電晶體T7的控制端接收源極驅動信號S1。電晶體T8的第一端耦接至驅動電路110,電晶體T8的第二端耦接至控制端CT2,電晶體T8的控制端接收源極驅動信號S2。電晶體T9的第一端耦接至參考電壓VREF,電晶體T9的第二端耦接至驅動電路110,電晶體T9的控制端耦接至控制端CT2。電容器C2耦接於控制端CT2以及節點P2之間。電容器C3耦接於節點P2以及參考電壓VREF之間。
On the other hand, the
具體而言,本實施例的電壓調整器130可依據源極驅動信號S1、源極驅動信號S2、源極驅動信號S4、資料電壓VDATA2以及參考電壓VREF以調整電晶體T9的控制端(亦即,控制端CT2)的電壓準位。並且,電壓調整器130可在畫素電路100操作於第二操作模式的發光階段時,依據控制端CT2的電壓準位以產生驅動電流I2至驅動電路110。
Specifically, the
值得一提的是,在本實施例中,畫素電路100可以從源極驅動器(或資料驅動器)(未繪示)接收資料電壓VDATA1以及資料電壓VDATA2。其中,所述源極驅動器(或資料驅動器)可根據顯示需求而產生資料電壓VDATA1以及資料電壓VDATA2至畫素電路100。舉例來說,資料電壓VDATA1可以是電壓範圍介
於第二電壓值(例如,0伏特(V))至第一電壓值(例如,6V)的方波信號,而資料電壓VDATA2可根據顯示需求而被設定為第二電壓值(例如,0V)或第一電壓值(例如,6V)。
It is worth mentioning that in this embodiment, the
進一步來說,當畫素電路100根據顯示需求而操作於第一操作模式時,電壓調整器130可於第一操作模式的發光階段中接收到具有第一電壓值(亦即,6V)的資料電壓VDATA2。而當畫素電路100根據顯示需求而操作於第二操作模式時,電壓調整器130可於第二操作模式的發光階段中接收到具有第二電壓值(亦即,0V)的資料電壓VDATA2。
Furthermore, when the
其中,上述的第一操作模式可意旨畫素電路100操作於低灰階(Low gray level)顯示狀態,而第二操作模式可意旨畫素電路100操作於高灰階(High gray level)顯示狀態。換言之,本實施例可以透過切換資料電壓VDATA2的電壓狀態來改變畫素電路100的操作模式或顯示狀態。
The above-mentioned first operation mode may mean that the
順帶一提的是,在本實施例中,電晶體T2以及電晶體T5彼此相互匹配。其中,上述的相互匹配可意旨電晶體的尺寸相同以及/或電晶體的臨界電壓(Threshold Voltage)相同。另外,在驅動電晶體TD以及電晶體T1~T9的設計上,驅動電晶體TD以及電晶體T1~T9可以是以P型電晶體為例,但本發明實施例不以此為限。 Incidentally, in this embodiment, the transistor T2 and the transistor T5 are matched with each other. The above-mentioned mutual matching may mean that the dimensions of the transistors are the same and/or the threshold voltages of the transistors are the same. In addition, in the design of the driving transistor TD and the transistors T1 to T9, the driving transistor TD and the transistors T1 to T9 can be P-type transistors as an example, but the embodiment of the present invention is not limited to this.
圖2是依照本發明圖1實施例的畫素電路操作於第一以及第二操作模式時的時序圖。請參照圖2,在本實施例中,畫素電
路100的一個畫素期間TFR可以區分為重置階段RP、補償階段CP、發光階段EP以及截止階段TP。畫素電路100可以依序操作於重置階段RP、補償階段CP、發光階段EP以及截止階段TP。重置階段RP、補償階段CP、發光階段EP以及截止階段TP彼此不相互重疊。其中,發光階段EP可以包括子階段EP1以及子階段EP2。
FIG. 2 is a timing diagram of the pixel circuit operating in the first and second operating modes according to the embodiment of FIG. 1 of the present invention. Please refer to Figure 2. In this embodiment, the pixel circuit
A pixel period TFR of the
關於畫素電路100操作於第一操作模式(亦即,低灰階顯示狀態)時的實施細節,請同時參照圖2以及圖3A至圖3D,圖3A至圖3D是依照本發明圖1實施例的畫素電路操作於第一操作模式時的等效電路圖。需注意到的是,為了方便示意,在圖3A至圖3D斷開的電晶體以打叉示意,而導通的電晶體以未打叉來示意。
Regarding the implementation details when the
請同時照圖2以及圖3A,在本實施例中,圖3A為畫素電路100操作在第一操作模式的重置階段RP時的等效電路圖。具體而言,在重置階段RP中,源極驅動信號S1、源極驅動信號S3以及源極驅動信號S4可以被設定為低電壓準位(例如,閘極低電壓VGL),而源極驅動信號S2以及發光控制信號EM可以被設定為高電壓準位(例如,閘極高電壓VGH)。
Please refer to FIG. 2 and FIG. 3A at the same time. In this embodiment, FIG. 3A is an equivalent circuit diagram when the
詳細來說,在重置階段RP中,電壓調整器120可依據被拉低的源極驅動信號S3而透過電晶體T3的導通路徑來提供參考電壓VREF至控制端CT1,藉以使控制端CT1的電壓準位對應地被拉高至等於參考電壓VREF的電壓值。並且,電壓調整器120
可基於被拉高的源極驅動信號S2,並依據被拉低的源極驅動信號S3以及資料電壓VDATA1而透過電晶體T4以及T5的導通路徑來提供閘極高電壓VGH至節點P1,藉以使節點P1的電壓準位對應地被拉高至等於閘極高電壓VGH的電壓值。
Specifically, during the reset phase RP, the
接著,電壓調整器130可依據被拉低的源極驅動信號S1而透過電晶體T7的導通路徑來提供低電壓VL至控制端CT2,藉以使控制端CT2的電壓準位對應地被拉低至等於低電壓VL的電壓值。
Then, the
在另一方面,在第一操作模式的重置階段RP中,本實施例的資料電壓VDATA2可以被設定為第二電壓值VDATA2_L(亦即,0V)。在此情況下,電壓調整器130可依據被拉低的源極驅動信號S4而提供資料電壓VDATA2至節點P2,藉以使節點P2的電壓準位對應地被拉低至等於資料電壓VDATA2的第二電壓值VDATA2_L。在此同時,驅動電路110可依據被拉高的發光控制信號EM而被斷開。
On the other hand, in the reset phase RP of the first operation mode, the data voltage VDATA2 of this embodiment may be set to the second voltage value VDATA2_L (ie, 0V). In this case, the
在完成各節點的重置動作之後,接著請同時參照圖2以及圖3B,在本實施例中,圖3B為畫素電路100操作在第一操作模式的補償階段CP時的等效電路圖。具體而言,在補償階段CP中,源極驅動信號S1以及發光控制信號EM可以被設定為高電壓準位(例如,閘極高電壓VGH),而源極驅動信號S2、源極驅動信號S3以及源極驅動信號S4可以被設定為低電壓準位(例如,閘極低電壓VGL)。
After completing the resetting operation of each node, please refer to FIG. 2 and FIG. 3B simultaneously. In this embodiment, FIG. 3B is an equivalent circuit diagram when the
詳細來說,在補償階段CP中,電壓調整器120可依據被拉低的源極驅動信號S3而透過電晶體T3的導通路徑來提供參考電壓VREF至控制端CT1,藉以使控制端CT1的電壓準位維持於參考電壓VREF的電壓值。並且,電壓調整器120可基於被拉低的源極驅動信號S2,並依據被拉低的源極驅動信號S3以及資料電壓VDATA1而透過電晶體T4以及T5的導通路徑來對節點P1進行放電,使得節點P1的電壓準位被調整為資料電壓VDATA1的電壓值以及電晶體T5的臨界電壓VTH5的電壓值的總和(亦即,VDATA1+|VTH5|)。
Specifically, in the compensation phase CP, the
接著,電壓調整器130可依據被拉低的源極驅動信號S2而透過電晶體T8以及T9的導通路徑來對控制端CT2進行充電,使得控制端CT2的電壓準位被調整為參考電壓VREF的電壓值以及電晶體T9的臨界電壓VTH9之間的電壓差值(亦即,VREF-|VTH9|)。
Then, the
其中,此時的電晶體T9可以透過電晶體T8的導通路徑而依據二極體組態(Diode Connection)的連接方式來形成一個二極體,以對臨界電壓VTH9進行補償,藉以提高補償精準度。 Among them, the transistor T9 at this time can form a diode according to the connection method of the diode configuration (Diode Connection) through the conduction path of the transistor T8 to compensate the critical voltage VTH9, thereby improving the compensation accuracy. .
此外,在第一操作模式的補償階段CP中,本實施例的資料電壓VDATA2可以被設定為第二電壓值VDATA2_L(亦即,0V)。在此情況下,電壓調整器130可依據被拉低的源極驅動信號S4而透過電晶體T6的導通路徑來提供資料電壓VDATA2至節點P2,藉以使節點P2的電壓準位維持於資料電壓VDATA2的第二電
壓值VDATA2_L。在此同時,驅動電路110可依據被拉高的發光控制信號EM而被斷開。
In addition, in the compensation phase CP of the first operation mode, the data voltage VDATA2 of this embodiment can be set to the second voltage value VDATA2_L (ie, 0V). In this case, the
接著請同時參照圖2以及圖3C,在本實施例中,圖3C為畫素電路100操作在第一操作模式的發光階段EP時的等效電路圖。具體而言,在發光階段EP中,源極驅動信號S1~S3可以被設定為高電壓準位(例如,閘極高電壓VGH),而發光控制信號EM可以被設定為低電壓準位(例如,閘極低電壓VGL)。並且,源極驅動信號S4在發光階段EP的子階段EP1中可被設定為低電壓準位(例如,閘極低電壓VGL),而在發光階段EP的子階段EP2中可被設定為高電壓準位(例如,閘極高電壓VGH)。
Next, please refer to FIG. 2 and FIG. 3C simultaneously. In this embodiment, FIG. 3C is an equivalent circuit diagram when the
詳細來說,在發光階段EP中,電壓調整器120可依據被拉低的發光控制信號EM而透過電晶體T1的導通路徑來提供系統高電壓VDD至節點P1,使得節點P1的電壓準位被調整為系統高電壓VDD的電壓值。
Specifically, in the light-emitting phase EP, the
接著,電壓調整器120可藉由電容器C1的耦合效應而使控制端CT1的電壓準位被調整為參考電壓VREF以及系統高電壓VDD、資料電壓VDATA1與電晶體T5的臨界電壓VTH5之間的電壓差值之總和。亦即,此時的控制端CT1的電壓準位為VREF+(VDD-VDATA1-|VTH5|)。
Then, the
在此情況下,電壓調整器120的電晶體T2可依據控制端CT1的電壓準位而產生驅動電流I1至驅動電路110。此時,流經發光元件LED的導通電流ID的大小即為驅動電流I1的電流值。
其中,導通電流ID以及驅動電流I1可以如下列式子(1)所示:ID=I1=K(VDD-(VREF-|VTH5|+VDD-VDATA1)-|VTH2|)^2=K(VDATA1-VREF)^2 式子(1)
In this case, the transistor T2 of the
依據上述的式子可以得知,當畫素電路100操作於發光階段EP時,由於電晶體T2與電晶體T5彼此相互匹配(亦即,臨界電壓VTH2相同於臨界電壓VTH5),因此,畫素電路100所產生的導通電流ID能夠與電晶體T2的臨界電壓VTH2以及系統高電壓VDD的電壓值無關。如此一來,畫素電路100可以改善電晶體T2(或開關電晶體)因製程上的差異或長時間操作所導致臨界電壓的偏移量的影響。並且,畫素電路100所產生的導通電流ID也較不容易受到系統高電壓VDD以及系統低電壓VSS的路徑中的線阻影響而發生誤差。
According to the above formula, it can be known that when the
在另一方面,在第一操作模式的發光階段EP中,本實施例的資料電壓VDATA2可以被設定為第一電壓值VDATA2_H(亦即,6V)。在此情況下,於第一操作模式的發光階段EP的子階段EP1中,電壓調整器130可依據被拉低的源極驅動信號S4而透過電晶體T6的導通路徑來提供資料電壓VDATA2至節點P2,藉以使節點P2的電壓準位被拉高至第一電壓值VDATA2_H。
On the other hand, in the light-emitting phase EP of the first operation mode, the data voltage VDATA2 of this embodiment can be set to the first voltage value VDATA2_H (ie, 6V). In this case, in the sub-phase EP1 of the light-emitting phase EP of the first operating mode, the
接著,電壓調整器130可藉由電容器C2的耦合效應而使控制端CT2的電壓準位被拉高至參考電壓VREF與電晶體T9的臨界電壓VTH9之間的電壓差值以及資料電壓VDATA2的電壓變化量△VDATA2的總和。亦即,此時的控制端CT2的電壓準位為
VREF-|VTH9|+△VDATA2。其中,上述的電壓變化量△VDATA2為第一電壓值VDATA2_H與第二電壓值VDATA2_L之間的電壓差值(亦即,VDATA2_H-VDATA2_L)。
Then, the
除此之外,於第一操作模式的發光階段EP的子階段EP2中,電壓調整器130可依據被拉高的源極驅動信號S4而斷開電晶體T6,並使節點P2的電壓準位維持於第一電壓值VDATA2_H。
In addition, in the sub-phase EP2 of the light-emitting phase EP of the first operating mode, the
也就是說,當畫素電路100操作於第一操作模式的發光階段EP時,畫素電路100可斷開電壓調整器130,並且依據控制端CT2的電壓準位而停止產生驅動電流I2至驅動電路110。
That is to say, when the
接著請同時參照圖2以及圖3D,在本實施例中,圖3D為畫素電路100操作在第一操作模式的截止階段TP時的等效電路圖。具體而言,在截止階段TP中,源極驅動信號S1~S4以及發光控制信號EM可以被設定為高電壓準位(例如,閘極高電壓VGH)。
Next, please refer to FIG. 2 and FIG. 3D simultaneously. In this embodiment, FIG. 3D is an equivalent circuit diagram when the
值得一提的是,由於圖3D所示的畫素電路100的控制端CT1、CT2以及節點P1、P2的電壓準位皆相同於圖3C所示的畫素電路100的控制端CT1、CT2以及節點P1、P2的電壓準位,因此,關於圖3D的畫素電路100中各個節點的電壓狀態可以參照圖3C所示的畫素電路100的相關說明來類推,故不再贅述。其中,在截止階段TP中,驅動電路110可依據被拉高的發光控制信號EM而停止點亮發光元件LED。
It is worth mentioning that since the voltage levels of the control terminals CT1 and CT2 and the nodes P1 and P2 of the
關於畫素電路100操作於第二操作模式(亦即,高灰階
顯示狀態)時的實施細節,請同時參照圖2以及圖4A至圖4D,圖4A至圖4D是依照本發明圖1實施例的畫素電路操作於第二操作模式時的等效電路圖。需注意到的是,為了方便示意,在圖4A至圖4D斷開的電晶體以打叉示意,而導通的電晶體以未打叉來示意。
Regarding the
請同時參照圖2以及圖4A,在本實施例中,圖4A為畫素電路100操作在第二操作模式的重置階段RP時的等效電路圖。其中,由於圖4A所示的畫素電路100的控制端CT1、CT2以及節點P1的電壓準位皆相同於圖3A所示的畫素電路100的控制端CT1、CT2以及節點P1的電壓準位,因此,關於圖4A的畫素電路100在重置階段RP中各個節點的電壓狀態可以參照圖3A所示的畫素電路100的相關說明來類推,故不再贅述。
Please refer to FIG. 2 and FIG. 4A at the same time. In this embodiment, FIG. 4A is an equivalent circuit diagram when the
不同於圖3A實施例的是,在圖4A的實施例中,資料電壓VDATA2可以被設定為第一電壓值VDATA2_H(亦即,6V)。在此情況下,電壓調整器130可依據被拉低的源極驅動信號S4而透過電晶體T6的導通路徑來提供資料電壓VDATA2至節點P2,藉以使節點P2的電壓準位對應地被拉高至等於資料電壓VDATA2的第一電壓值VDATA2_H。
Different from the embodiment of FIG. 3A , in the embodiment of FIG. 4A , the data voltage VDATA2 may be set to the first voltage value VDATA2_H (that is, 6V). In this case, the
接著請同時參照圖2以及圖4B,在本實施例中,圖4B為畫素電路100操作在第二操作模式的補償階段CP時的等效電路圖。其中,由於圖4B所示的畫素電路100的控制端CT1、CT2以及節點P1的電壓準位皆相同於圖3B所示的畫素電路100的控制
端CT1、CT2以及節點P1的電壓準位,因此,關於圖4B的畫素電路100在補償階段CP中各個節點的電壓狀態可以參照圖3B所示的畫素電路100的相關說明來類推,故不再贅述。
Next, please refer to FIG. 2 and FIG. 4B simultaneously. In this embodiment, FIG. 4B is an equivalent circuit diagram when the
不同於圖3B實施例的是,在圖4B的實施例中,資料電壓VDATA2可以被設定為第一電壓值VDATA2_H(亦即,6V)。在此情況下,電壓調整器130可依據被拉低的源極驅動信號S4而透過電晶體T6的導通路徑來提供資料電壓VDATA2至節點P2,藉以使節點P2的電壓準位維持於資料電壓VDATA2的第一電壓值VDATA2_H。
Different from the embodiment of FIG. 3B , in the embodiment of FIG. 4B , the data voltage VDATA2 may be set to the first voltage value VDATA2_H (that is, 6V). In this case, the
接著,請同時參照圖2以及圖4C,在本實施例中,圖4C為畫素電路100操作在第二操作模式的發光階段EP時的等效電路圖。
Next, please refer to FIG. 2 and FIG. 4C simultaneously. In this embodiment, FIG. 4C is an equivalent circuit diagram when the
詳細來說,在發光階段EP中,電壓調整器120可依據被拉低的發光控制信號EM而透過電晶體T1的導通路徑來提供系統高電壓VDD至節點P1,使得節點P1的電壓準位被調整為系統高電壓VDD的電壓值。
Specifically, in the light-emitting phase EP, the
接著,電壓調整器120可藉由電容器C1的耦合效應而使控制端CT1的電壓準位被調整為參考電壓VREF以及系統高電壓VDD、資料電壓VDATA1與電晶體T5的臨界電壓VTH5之間的電壓差值之總和。亦即,此時的控制端CT1的電壓準位為VREF+(VDD-VDATA1-|VTH5|)。
Then, the
在此情況下,電壓調整器120的電晶體T2可依據控制端
CT1的電壓準位而產生驅動電流I1至驅動電路110。其中,此時的驅動電流I1的電流大小可參照上述式子(1)所示。
In this case, the transistor T2 of the
在另一方面,在第二操作模式的發光階段EP中,本實施例的資料電壓VDATA2可以被設定為第二電壓值VDATA2_L(亦即,0V)。在此情況下,於第二操作模式的發光階段EP的子階段EP1中,電壓調整器130可依據被拉低的源極驅動信號S4而透過電晶體T6的導通路徑來提供資料電壓VDATA2至節點P2,藉以使節點P2的電壓準位被拉低至第二電壓值VDATA2_L。
On the other hand, in the light-emitting phase EP of the second operation mode, the data voltage VDATA2 of this embodiment can be set to the second voltage value VDATA2_L (ie, 0V). In this case, in the sub-phase EP1 of the light-emitting phase EP of the second operating mode, the
接著,電壓調整器130可藉由電容器C2的耦合效應而使控制端CT2的電壓準位被拉低至參考電壓VREF、電晶體T9的臨界電壓VTH9以及資料電壓VDATA2的電壓變化量△VDATA2之間的電壓差值。亦即,此時的控制端CT2的電壓準位為VREF-|VTH9|-△VDATA2。其中,上述的電壓變化量△VDATA2為第一電壓值VDATA2_H與第二電壓值VDATA2_L之間的電壓差值(亦即,VDATA2_H-VDATA2_L)。
Then, the
在此情況下,電壓調整器130的電晶體T9可依據控制端CT2的電壓準位而產生驅動電流I2至驅動電路110。其中,驅動電流I2可以如下列式子(2)所示:I2=K(VREF-(VREF-|VTH9|-△VDATA2)-|VTH9|)^2=K(△VDATA2)^2 式子(2)
In this case, the transistor T9 of the
也就是說,在第二操作模式下,驅動電路110所產生的導通電流ID的電流大小可為驅動電流I1以及驅動電流I2的總和
的電流值。其中,此時的導通電流ID可以如下列式子(3)所示:ID=I1+I2=K(VDATA1-VREF)^2+K(△VDATA2)^2 式子(3)
That is to say, in the second operating mode, the current magnitude of the on-current ID generated by the driving
其中,上述的ID為導通電流ID的電流值;K為驅動電晶體TD的製程參數;VDATA1為資料電壓VDATA1的電壓值;VREF為參考電壓VREF的電壓值;△VDATA2為資料電壓VDATA2的電壓變化量。 Among them, the above ID is the current value of the on-current ID; K is the process parameter of the driving transistor TD; VDATA1 is the voltage value of the data voltage VDATA1; VREF is the voltage value of the reference voltage VREF; △VDATA2 is the voltage change of the data voltage VDATA2 quantity.
接著請同時參照圖2以及圖4D,在本實施例中,圖4D為畫素電路100操作在第二操作模式的截止階段TP時的等效電路圖。其中,由於圖4D所示的畫素電路100的控制端CT1、CT2以及節點P1的電壓準位皆相同於圖3D所示的畫素電路100的控制端CT1、CT2以及節點P1的電壓準位,因此,關於圖4D的畫素電路100在截止階段TP中各個節點的電壓狀態可以參照圖3D所示的畫素電路100的相關說明來類推,故不再贅述。
Next, please refer to FIG. 2 and FIG. 4D simultaneously. In this embodiment, FIG. 4D is an equivalent circuit diagram when the
不同於圖3D實施例的是,在圖4D的實施例中,資料電壓VDATA2可以被設定為第二電壓值VDATA2_L(亦即,0V)。因此,電壓調整器130可依據被拉高的源極驅動信號S4而斷開電晶體T6,以使節點P2的電壓準位維持於資料電壓VDATA2的第二電壓值VDATA2_L。
Different from the embodiment of FIG. 3D , in the embodiment of FIG. 4D , the data voltage VDATA2 may be set to the second voltage value VDATA2_L (ie, 0V). Therefore, the
依據上述的說明內容可以得知,當畫素電路100操作於第一操作模式(亦即,低灰階顯示狀態)的發光階段時,可以僅透過電壓調整器120來決定發光元件LED的發光亮度,而當畫素電路100操作於第二操作模式(亦即,高灰階顯示狀態)的發光
階段時,可以透過額外的電壓調整器130與電壓調整器120共同決定發光元件LED的發光亮度。
According to the above description, it can be known that when the
如此一來,本實施例的畫素電路100可以透過兩條電流路徑來控制顯示畫面的灰階狀態,以降低系統高電壓VDD以及系統低電壓VSS之間的跨壓,並達到改善功率消耗的效果。
In this way, the
此外,本實施例的畫素電路100亦可對電晶體的臨界電壓變異進行補償,藉以提升導通電流ID的一致性,且改善顯示品質。
In addition, the
圖5是依照本發明一實施例的畫素電路的驅動方法的流程圖。請同時參照圖1以及圖5,在步驟S510中,畫素電路100使驅動電路110依據發光控制信號EM以產生導通電流ID。在步驟S520中,畫素電路100使電壓調整器120依據發光控制信號EM、源極驅動信號S3、資料電壓VDATA1以及參考電壓VREF以調整電壓調整器120的控制端CT1的電壓準位,並依據控制端CT1的電壓準位以產生驅動電流I1。在步驟S530中,畫素電路100使電壓調整器130依據源極驅動信號S1、源極驅動信號S2、源極驅動信號S4、資料電壓VDATA2以及參考電壓VREF以調整電壓調整器130的控制端CT2的電壓準位,並依據控制端CT2的電壓準位以產生驅動電流I2。在步驟S540中,於第一操作模式下,畫素電路100使導通電流ID的大小為驅動電流I1的電流值,於第二操作模式下,畫素電路100使導通電流ID的大小為驅動電流I1以及驅動電流I2的總和的電流值。
FIG. 5 is a flow chart of a driving method of a pixel circuit according to an embodiment of the present invention. Please refer to FIG. 1 and FIG. 5 simultaneously. In step S510, the
關於圖5各步驟的實施細節在前述的實施例及實施方式都有詳盡的說明,在此則不再贅述。 The implementation details of each step in Figure 5 have been described in detail in the foregoing embodiments and implementations, and will not be described again here.
綜上所述,本發明諸實施例所述畫素電路可以於低灰階顯示狀態時,僅透過主要的電壓調整器來決定發光元件的發光亮度,而於高灰階顯示狀態時,透過額外的電壓調整器與主要的電壓調整器共同決定發光元件的發光亮度。如此一來,畫素電路可以透過兩條電流路徑來控制顯示畫面的灰階狀態,以降低系統高電壓以及系統低電壓之間的跨壓,並達到改善功率消耗的效果。 To sum up, the pixel circuit according to the embodiments of the present invention can determine the luminous brightness of the light-emitting element only through the main voltage regulator in the low-grayscale display state, and through an additional voltage regulator in the high-grayscale display state. The voltage regulator and the main voltage regulator jointly determine the brightness of the light-emitting element. In this way, the pixel circuit can control the grayscale state of the display screen through two current paths to reduce the cross-voltage between the system high voltage and the system low voltage, and achieve the effect of improving power consumption.
100:畫素電路 100: Pixel circuit
110:驅動電路 110: Drive circuit
120、130:電壓調整器 120, 130: Voltage regulator
C1~C3:電容器 C1~C3: capacitor
CT1、CT2:控制端 CT1, CT2: control terminal
EM:發光控制信號 EM: Luminous control signal
ID:導通電流 ID: conduction current
I1、I2:驅動電流 I1, I2: drive current
LED:發光元件 LED: light emitting element
P1、P2:節點 P1, P2: nodes
S1~S4:源極驅動信號 S1~S4: source drive signal
T1~T9:電晶體 T1~T9: Transistor
TD:驅動電晶體 TD: drive transistor
VREF:參考電壓 VREF: reference voltage
VL:低電壓 VL: low voltage
VSS:系統低電壓 VSS: system low voltage
VDD:系統高電壓 VDD: system high voltage
VDATA1、VDATA2:資料電壓 VDATA1, VDATA2: data voltage
Claims (16)
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WO2011013409A1 (en) * | 2009-07-28 | 2011-02-03 | シャープ株式会社 | Active matrix substrate, display device, and organic el display device |
TW201239848A (en) * | 2011-03-17 | 2012-10-01 | Au Optronics Corp | Organic light emitting display having threshold voltage compensation mechanism and driving method thereof |
TW201413685A (en) * | 2012-09-17 | 2014-04-01 | Innocom Tech Shenzhen Co Ltd | Display device and light adjusting method thereof |
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TW201239848A (en) * | 2011-03-17 | 2012-10-01 | Au Optronics Corp | Organic light emitting display having threshold voltage compensation mechanism and driving method thereof |
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