TWI826107B - Pixel circuit and driving method thereof - Google Patents

Abstract

A pixel circuit and a driving method are provided. In the pixel circuit, a driving circuit generates an on-current according to a lighting control signal. A first voltage regulator adjusts a voltage level of a first control terminal according to the lighting control signal, a third source driving signal, a first data voltage and a reference voltage, and generates a first driving current according to the voltage level of the first control terminal. A second voltage regulator adjusts a voltage level of a second control terminal according to the first, second and fourth source driving signals, a second data voltage and the reference voltage, and generates a second driving current according to the voltage level of the second control terminal. In a first operation mode, the magnitude of the on-current is the current value of the first driving current. In a second operation mode, the magnitude of the on-current is the current value of the sum of the first driving current and the second driving current.

Description

Pixel circuit and driving method

The present invention relates to a display device, and in particular, to a pixel circuit and a driving method thereof.

In the conventional display technology, the display panel is easily affected by variations in the threshold voltage (Threshold Voltage) of the transistors in the pixel circuit, thereby reducing the display quality of the display image.

In addition, when the pixel circuit operates in a display screen with different grayscale levels (for example, a low grayscale state or a high grayscale state), when the on-current of the driving transistor is in a large current state, and the light-emitting element is used for a long time. When lit, the overall power consumption of the pixel circuit will be too high. In addition, the system low voltage in the pixel circuit is also easily affected by the line resistance of the transmission path, resulting in a different terminal voltage of each pixel, which in turn causes an error in the conduction current flowing through the light-emitting element in each pixel.

In view of this, how to improve the influence of the variation of the critical voltage of the transistor and effectively reduce the power consumption of the pixel circuit when the pixel circuit operates in a display screen with different grayscale levels, so as to improve the display quality of the display screen, will be Relevant to this field Important topics for technicians.

The present invention provides a pixel circuit and a driving method thereof, which can effectively reduce the overall power consumption in different operating modes and improve the critical voltage variation problem of transistors to improve the display quality of the display screen.

The pixel circuit of the present invention includes a driving circuit, a first voltage regulator and a second voltage regulator. The driving circuit generates conduction current according to the lighting control signal. The first voltage regulator has a first control terminal. The first voltage regulator is coupled to the driving circuit and adjusts the voltage level of the first control terminal according to the lighting control signal, the third source driving signal, the first data voltage and the reference voltage. , and generate the first driving current according to the voltage level of the first control terminal. The second voltage regulator has a second control terminal. The second voltage regulator is coupled to the driving circuit. According to the first source driving signal, the second source driving signal, the fourth source driving signal, the second data voltage and the reference The voltage is used to adjust the voltage level of the second control terminal and generate the second driving current according to the voltage level of the second control terminal. Wherein, in the first operating mode, the magnitude of the on-current is the current value of the first driving current, and in the second operating mode, the magnitude of the on-current is the current value of the sum of the first driving current and the second driving current.

The driving method of the pixel circuit of the present invention includes: causing the driving circuit to generate an on-current according to the lighting control signal; causing the first voltage regulator to generate a conductive current according to the lighting control signal, the third source driving signal, the first data voltage and the reference voltage. Adjust the voltage level of the first control terminal of the first voltage regulator, and adjust the voltage level of the first control terminal according to the voltage level of the first control terminal. voltage level to generate a first driving current; causing the second voltage regulator to adjust the second voltage according to the first source driving signal, the second source driving signal, the fourth source driving signal, the second data voltage and the reference voltage. The voltage level of the second control terminal of the regulator is used to generate the second driving current according to the voltage level of the second control terminal; and in the first operating mode, the magnitude of the conduction current is the current value of the first driving current, and In the second operation mode, the magnitude of the conduction current is the current value of the sum of the first driving current and the second driving current.

Based on the above, the pixel circuits described in the embodiments of the present invention can only use the main voltage regulator to determine the luminous brightness of the light-emitting element in the low-grayscale display state, and use an additional voltage in the high-grayscale display state. The regulator and the main voltage regulator jointly determine the brightness of the light-emitting element. In this way, the pixel circuit can control the grayscale state of the display screen through two current paths to reduce the cross-voltage between the system high voltage and the system low voltage, and achieve the effect of improving power consumption.

100: Pixel circuit

110: Drive circuit

120, 130: Voltage regulator

C1~C3: capacitor

CT1, CT2: control terminal

CP: Compensation stage

EM: Luminous control signal

EP: Glowing Stage

EP1, EP2: sub-stage

ID: conduction current

I1, I2: drive current

LED: light emitting element

P1, P2: nodes

RP: reset phase

S1~S4: source drive signal

S510~S540: steps

T1~T9: Transistor

TD: drive transistor

TFR: pixel period

TP: deadline stage

VREF: reference voltage

VL: low voltage

VSS: system low voltage

VDD: system high voltage

VDATA1, VDATA2: data voltage

VGH: gate high voltage

VGL: gate low voltage

FIG. 1 is a schematic diagram of a pixel circuit according to an embodiment of the present invention.

FIG. 2 is a timing diagram of the pixel circuit operating in the first and second operating modes according to the embodiment of FIG. 1 of the present invention.

3A to 3D are equivalent circuit diagrams of the pixel circuit according to the embodiment of FIG. 1 operating in the first operating mode.

4A to 4D illustrate the pixel circuit operating in the third embodiment according to the embodiment of FIG. 1 of the present invention. Equivalent circuit diagram in two operating modes.

FIG. 5 is a flow chart of a driving method of a pixel circuit according to an embodiment of the present invention.

The term "coupling (or connection)" used throughout the specification of this case (including the scope of the patent application) can refer to any direct or indirect connection means. For example, if a first device is coupled (or connected) to a second device, it should be understood that the first device can be directly connected to the second device, or the first device can be connected through other devices or other devices. A connection means is indirectly connected to the second device. In addition, wherever possible, elements/components/steps with the same reference numbers are used in the drawings and embodiments to represent the same or similar parts. Elements/components/steps using the same numbers or using the same terms in different embodiments can refer to the relevant descriptions of each other.

FIG. 1 is a schematic diagram of a pixel circuit according to an embodiment of the present invention. Please refer to FIG. 1 . In this embodiment, the pixel circuit 100 includes a driving circuit 110 , a voltage regulator 120 and a voltage regulator 130 . The driving circuit 110 includes a driving transistor TD and a light emitting element LED. The first terminal of the driving transistor TD is coupled to the voltage regulator 120 and the voltage regulator 130, and the control terminal of the driving transistor TD receives the lighting control signal EM. The anode terminal of the light-emitting element LED is coupled to the second terminal of the driving transistor TD, and the cathode terminal of the light-emitting element LED is coupled to the system low voltage VSS.

Specifically, the driving circuit 110 of this embodiment can generate the conduction current ID according to the state of the light emission control signal EM, and the driving circuit 110 can generate the conduction current ID according to the state of the light emission control signal EM. The current ID is conducted to correspondingly light up the light-emitting element LED. The light-emitting element LED in this embodiment may be, for example, an organic light-emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), or other micro-light-emitting elements, and the invention is not particularly limited.

The voltage regulator 120 is coupled to the driving circuit 110 . The voltage regulator 120 includes transistors T1 to T5 and a capacitor C1. The first terminal of the transistor T1 is coupled to the system high voltage VDD, the second terminal of the transistor T1 is coupled to the node P1, and the control terminal of the transistor T1 receives the lighting control signal EM. The first terminal of the transistor T2 (ie, the switching transistor) is coupled to the system high voltage VDD, the second terminal of the transistor T2 is coupled to the driving circuit 110, and the control terminal of the transistor T2 is coupled to the control terminal CT1. The first terminal of the transistor T3 is coupled to the reference voltage VREF, the second terminal of the transistor T3 is coupled to the control terminal CT1, and the control terminal of the transistor T3 receives the source driving signal S3. The first terminal of the transistor T4 is coupled to the node P1, and the control terminal of the transistor T4 receives the source driving signal S3. The first terminal of the transistor T5 receives the source driving signal S2, the second terminal of the transistor T5 is coupled to the second terminal of the transistor T4, and the control terminal of the transistor T5 is coupled to the data voltage VDATA1. Capacitor C1 is coupled between control terminal CT1 and node P1.

Specifically, the voltage regulator 120 of this embodiment can adjust the voltage of the control terminal of the transistor T2 (ie, the control terminal CT1) according to the light emission control signal EM, the source driving signal S3, the data voltage VDATA1 and the reference voltage VREF. accurate position. Furthermore, the voltage regulator 120 can generate the driving current I1 to the driving circuit 110 according to the voltage level of the control terminal CT1 when the pixel circuit 100 operates in the light-emitting phase of the first operation mode and the second operation mode.

On the other hand, the voltage regulator 130 includes transistors T6˜T9 and capacitors C2˜C3. The first terminal of the transistor T6 is coupled to the data voltage VDATA2, the second terminal of the transistor T6 is coupled to the node P2, and the control terminal of the transistor T6 receives the source driving signal S4. The first terminal of the transistor T7 is coupled to the low voltage VL, the second terminal of the transistor T7 is coupled to the control terminal CT2, and the control terminal of the transistor T7 receives the source driving signal S1. The first terminal of the transistor T8 is coupled to the driving circuit 110, the second terminal of the transistor T8 is coupled to the control terminal CT2, and the control terminal of the transistor T8 receives the source driving signal S2. The first terminal of the transistor T9 is coupled to the reference voltage VREF, the second terminal of the transistor T9 is coupled to the driving circuit 110, and the control terminal of the transistor T9 is coupled to the control terminal CT2. Capacitor C2 is coupled between control terminal CT2 and node P2. Capacitor C3 is coupled between node P2 and reference voltage VREF.

Specifically, the voltage regulator 130 of this embodiment can adjust the control terminal of the transistor T9 (i.e. , the voltage level of the control terminal CT2). Furthermore, the voltage regulator 130 can generate the driving current I2 to the driving circuit 110 according to the voltage level of the control terminal CT2 when the pixel circuit 100 operates in the light-emitting phase of the second operating mode.

It is worth mentioning that in this embodiment, the pixel circuit 100 can receive the data voltage VDATA1 and the data voltage VDATA2 from a source driver (or data driver) (not shown). The source driver (or data driver) can generate the data voltage VDATA1 and the data voltage VDATA2 to the pixel circuit 100 according to display requirements. For example, the data voltage VDATA1 can be in the voltage range A square wave signal between a second voltage value (for example, 0 volts (V)) and a first voltage value (for example, 6V), and the data voltage VDATA2 can be set to the second voltage value (for example, 0V) according to display requirements. or a first voltage value (for example, 6V).

Furthermore, when the pixel circuit 100 operates in the first operation mode according to the display requirement, the voltage regulator 130 can receive data with the first voltage value (ie, 6V) in the light-emitting phase of the first operation mode. Voltage VDATA2. When the pixel circuit 100 operates in the second operating mode according to display requirements, the voltage regulator 130 can receive the data voltage VDATA2 with the second voltage value (ie, 0V) during the light-emitting phase of the second operating mode.

The above-mentioned first operation mode may mean that the pixel circuit 100 operates in a low gray level display state, and the second operation mode may mean that the pixel circuit 100 operates in a high gray level display state. . In other words, this embodiment can change the operating mode or display state of the pixel circuit 100 by switching the voltage state of the data voltage VDATA2.

Incidentally, in this embodiment, the transistor T2 and the transistor T5 are matched with each other. The above-mentioned mutual matching may mean that the dimensions of the transistors are the same and/or the threshold voltages of the transistors are the same. In addition, in the design of the driving transistor TD and the transistors T1 to T9, the driving transistor TD and the transistors T1 to T9 can be P-type transistors as an example, but the embodiment of the present invention is not limited to this.

FIG. 2 is a timing diagram of the pixel circuit operating in the first and second operating modes according to the embodiment of FIG. 1 of the present invention. Please refer to Figure 2. In this embodiment, the pixel circuit A pixel period TFR of the path 100 can be divided into a reset phase RP, a compensation phase CP, a light emitting phase EP and a cutoff phase TP. The pixel circuit 100 may operate in the reset phase RP, the compensation phase CP, the light emission phase EP and the cut-off phase TP in sequence. The reset phase RP, the compensation phase CP, the lighting phase EP and the cut-off phase TP do not overlap with each other. The light-emitting phase EP may include sub-phase EP1 and sub-phase EP2.

Regarding the implementation details when the pixel circuit 100 operates in the first operating mode (that is, the low grayscale display state), please refer to FIG. 2 and FIG. 3A to FIG. 3D. FIG. 3A to FIG. 3D are implemented in accordance with FIG. 1 of the present invention. The equivalent circuit diagram of the example pixel circuit when operating in the first operating mode. It should be noted that, for convenience of illustration, disconnected transistors are indicated by a cross in FIGS. 3A to 3D , while conductive transistors are indicated by an uncrossed one.

Please refer to FIG. 2 and FIG. 3A at the same time. In this embodiment, FIG. 3A is an equivalent circuit diagram when the pixel circuit 100 operates in the reset phase RP of the first operation mode. Specifically, in the reset phase RP, the source driving signal S1 , the source driving signal S3 and the source driving signal S4 may be set to a low voltage level (for example, the gate low voltage VGL), and the source driving signal The signal S2 and the light emission control signal EM may be set to a high voltage level (eg, gate high voltage VGH).

Specifically, during the reset phase RP, the voltage regulator 120 can provide the reference voltage VREF to the control terminal CT1 through the conduction path of the transistor T3 according to the source driving signal S3 that is pulled down, so that the control terminal CT1 The voltage level is accordingly pulled up to a voltage value equal to the reference voltage VREF. And, voltage regulator 120 The gate high voltage VGH can be provided to the node P1 through the conduction paths of the transistors T4 and T5 based on the source drive signal S2 that is pulled high, and based on the source drive signal S3 that is pulled low and the data voltage VDATA1, so that the gate high voltage VGH can be provided to the node P1. The voltage level of node P1 is accordingly pulled up to a voltage value equal to the gate high voltage VGH.

Then, the voltage regulator 130 can provide the low voltage VL to the control terminal CT2 through the conduction path of the transistor T7 according to the pulled-down source driving signal S1, so that the voltage level of the control terminal CT2 is correspondingly pulled down to Is equal to the voltage value of low voltage VL.

On the other hand, in the reset phase RP of the first operation mode, the data voltage VDATA2 of this embodiment may be set to the second voltage value VDATA2_L (ie, 0V). In this case, the voltage regulator 130 can provide the data voltage VDATA2 to the node P2 according to the source driving signal S4 that is pulled down, so that the voltage level of the node P2 is correspondingly pulled down to a second level equal to the data voltage VDATA2. Voltage value VDATA2_L. At the same time, the driving circuit 110 can be turned off according to the high light emitting control signal EM.

After completing the resetting operation of each node, please refer to FIG. 2 and FIG. 3B simultaneously. In this embodiment, FIG. 3B is an equivalent circuit diagram when the pixel circuit 100 operates in the compensation phase CP of the first operation mode. Specifically, in the compensation phase CP, the source driving signal S1 and the emission control signal EM can be set to a high voltage level (for example, the gate high voltage VGH), while the source driving signal S2 and the source driving signal S3 And the source driving signal S4 can be set to a low voltage level (eg, gate low voltage VGL).

Specifically, in the compensation phase CP, the voltage regulator 120 can provide the reference voltage VREF to the control terminal CT1 through the conduction path of the transistor T3 according to the pulled-down source driving signal S3, so that the voltage of the control terminal CT1 The level is maintained at the voltage value of the reference voltage VREF. Furthermore, the voltage regulator 120 can discharge the node P1 through the conduction paths of the transistors T4 and T5 based on the pulled-down source driving signal S2 and based on the pulled-down source driving signal S3 and the data voltage VDATA1, The voltage level of the node P1 is adjusted to the sum of the voltage value of the data voltage VDATA1 and the voltage value of the threshold voltage VTH5 of the transistor T5 (ie, VDATA1+|VTH5|).

Then, the voltage regulator 130 can charge the control terminal CT2 through the conduction paths of the transistors T8 and T9 according to the pulled-down source driving signal S2, so that the voltage level of the control terminal CT2 is adjusted to the reference voltage VREF. The voltage difference between the voltage value and the threshold voltage VTH9 of the transistor T9 (that is, VREF-|VTH9|).

Among them, the transistor T9 at this time can form a diode according to the connection method of the diode configuration (Diode Connection) through the conduction path of the transistor T8 to compensate the critical voltage VTH9, thereby improving the compensation accuracy. .

In addition, in the compensation phase CP of the first operation mode, the data voltage VDATA2 of this embodiment can be set to the second voltage value VDATA2_L (ie, 0V). In this case, the voltage regulator 130 can provide the data voltage VDATA2 to the node P2 through the conduction path of the transistor T6 according to the source driving signal S4 that is pulled down, so that the voltage level of the node P2 is maintained at the data voltage VDATA2 the second electricity Voltage value VDATA2_L. At the same time, the driving circuit 110 can be turned off according to the high light emitting control signal EM.

Next, please refer to FIG. 2 and FIG. 3C simultaneously. In this embodiment, FIG. 3C is an equivalent circuit diagram when the pixel circuit 100 operates in the light-emitting phase EP of the first operation mode. Specifically, in the light-emitting phase EP, the source driving signals S1 ~ S3 can be set to a high voltage level (eg, gate high voltage VGH), and the light-emitting control signal EM can be set to a low voltage level (eg, gate high voltage VGH). , gate low voltage VGL). Furthermore, the source driving signal S4 may be set to a low voltage level (for example, the gate low voltage VGL) in the sub-stage EP1 of the light-emitting stage EP, and may be set to a high voltage in the sub-stage EP2 of the light-emitting stage EP. level (for example, gate high voltage VGH).

Specifically, in the light-emitting phase EP, the voltage regulator 120 can provide the system high voltage VDD to the node P1 through the conduction path of the transistor T1 according to the pulled-down light-emitting control signal EM, so that the voltage level of the node P1 is adjusted. Adjust to the voltage value of system high voltage VDD.

Then, the voltage regulator 120 can adjust the voltage level of the control terminal CT1 to a voltage between the reference voltage VREF, the system high voltage VDD, the data voltage VDATA1 and the critical voltage VTH5 of the transistor T5 through the coupling effect of the capacitor C1 The sum of the differences. That is, the voltage level of the control terminal CT1 at this time is VREF+(VDD-VDATA1-|VTH5|).

In this case, the transistor T2 of the voltage regulator 120 can generate the driving current I1 to the driving circuit 110 according to the voltage level of the control terminal CT1. At this time, the magnitude of the on-current ID flowing through the light-emitting element LED is the current value of the driving current I1. Among them, the on-current ID and the driving current I1 can be shown as the following formula (1): ID=I1=K(VDD-(VREF-|VTH5|+VDD-VDATA1)-|VTH2|)^2=K(VDATA1 -VREF)^2 Formula (1)

According to the above formula, it can be known that when the pixel circuit 100 operates in the light-emitting phase EP, since the transistor T2 and the transistor T5 match each other (that is, the critical voltage VTH2 is the same as the critical voltage VTH5), therefore, the pixel The conduction current ID generated by the circuit 100 can be independent of the threshold voltage VTH2 of the transistor T2 and the voltage value of the system high voltage VDD. In this way, the pixel circuit 100 can improve the influence of the offset of the threshold voltage of the transistor T2 (or the switching transistor) due to process differences or long-term operation. Furthermore, the on-current ID generated by the pixel circuit 100 is less susceptible to errors caused by line resistance in the path of the system high voltage VDD and the system low voltage VSS.

On the other hand, in the light-emitting phase EP of the first operation mode, the data voltage VDATA2 of this embodiment can be set to the first voltage value VDATA2_H (ie, 6V). In this case, in the sub-phase EP1 of the light-emitting phase EP of the first operating mode, the voltage regulator 130 can provide the data voltage VDATA2 to the node through the conduction path of the transistor T6 according to the source driving signal S4 that is pulled down. P2, so that the voltage level of node P2 is pulled up to the first voltage value VDATA2_H.

Then, the voltage regulator 130 can use the coupling effect of the capacitor C2 to raise the voltage level of the control terminal CT2 to the voltage difference between the reference voltage VREF and the threshold voltage VTH9 of the transistor T9 and the voltage of the data voltage VDATA2 The sum of the changes △VDATA2. That is, the voltage level of the control terminal CT2 at this time is VREF-|VTH9|+△VDATA2. The above-mentioned voltage change amount ΔVDATA2 is the voltage difference between the first voltage value VDATA2_H and the second voltage value VDATA2_L (that is, VDATA2_H-VDATA2_L).

In addition, in the sub-phase EP2 of the light-emitting phase EP of the first operating mode, the voltage regulator 130 can turn off the transistor T6 according to the pulled-up source driving signal S4 and adjust the voltage level of the node P2 Maintained at the first voltage value VDATA2_H.

That is to say, when the pixel circuit 100 operates in the light-emitting phase EP of the first operating mode, the pixel circuit 100 can turn off the voltage regulator 130 and stop generating the driving current I2 to the driver according to the voltage level of the control terminal CT2. Circuit 110.

Next, please refer to FIG. 2 and FIG. 3D simultaneously. In this embodiment, FIG. 3D is an equivalent circuit diagram when the pixel circuit 100 operates in the cut-off phase TP of the first operation mode. Specifically, in the cut-off phase TP, the source driving signals S1 to S4 and the light emission control signal EM may be set to a high voltage level (for example, the gate high voltage VGH).

It is worth mentioning that since the voltage levels of the control terminals CT1 and CT2 and the nodes P1 and P2 of the pixel circuit 100 shown in FIG. 3D are the same as those of the control terminals CT1 and CT2 of the pixel circuit 100 shown in FIG. 3C The voltage levels of nodes P1 and P2, therefore, the voltage status of each node in the pixel circuit 100 in FIG. 3D can be deduced by referring to the relevant description of the pixel circuit 100 shown in FIG. 3C, and will not be described again. Among them, in the cut-off phase TP, the driving circuit 110 can stop lighting the light-emitting element LED according to the high light-emitting control signal EM.

Regarding the pixel circuit 100 operating in the second operating mode (ie, high grayscale For implementation details of the display state), please refer to FIG. 2 and FIG. 4A to FIG. 4D. FIG. 4A to FIG. 4D are equivalent circuit diagrams when the pixel circuit according to the embodiment of FIG. 1 operates in the second operation mode of the present invention. It should be noted that, for convenience of illustration, disconnected transistors are indicated by a cross in FIGS. 4A to 4D , while conductive transistors are indicated by an uncrossed transistor.

Please refer to FIG. 2 and FIG. 4A at the same time. In this embodiment, FIG. 4A is an equivalent circuit diagram when the pixel circuit 100 operates in the reset phase RP of the second operation mode. Among them, since the voltage levels of the control terminals CT1, CT2 and node P1 of the pixel circuit 100 shown in FIG. 4A are the same as the voltage levels of the control terminals CT1, CT2 and node P1 of the pixel circuit 100 shown in FIG. 3A , therefore, the voltage state of each node in the reset phase RP of the pixel circuit 100 in FIG. 4A can be deduced by analogy with reference to the relevant description of the pixel circuit 100 shown in FIG. 3A , and will not be described again.

Different from the embodiment of FIG. 3A , in the embodiment of FIG. 4A , the data voltage VDATA2 may be set to the first voltage value VDATA2_H (that is, 6V). In this case, the voltage regulator 130 can provide the data voltage VDATA2 to the node P2 through the conduction path of the transistor T6 according to the source driving signal S4 that is pulled down, so that the voltage level of the node P2 is pulled up accordingly. to a first voltage value VDATA2_H equal to the data voltage VDATA2.

Next, please refer to FIG. 2 and FIG. 4B simultaneously. In this embodiment, FIG. 4B is an equivalent circuit diagram when the pixel circuit 100 operates in the compensation phase CP of the second operation mode. Among them, since the voltage levels of the control terminals CT1, CT2 and node P1 of the pixel circuit 100 shown in FIG. 4B are all the same as those of the pixel circuit 100 shown in FIG. 3B, The voltage levels of terminals CT1, CT2 and node P1. Therefore, the voltage status of each node in the compensation phase CP of the pixel circuit 100 of FIG. 4B can be deduced by referring to the relevant description of the pixel circuit 100 shown in FIG. 3B. Therefore, No more details.

Different from the embodiment of FIG. 3B , in the embodiment of FIG. 4B , the data voltage VDATA2 may be set to the first voltage value VDATA2_H (that is, 6V). In this case, the voltage regulator 130 can provide the data voltage VDATA2 to the node P2 through the conduction path of the transistor T6 according to the source driving signal S4 that is pulled down, so that the voltage level of the node P2 is maintained at the data voltage VDATA2 The first voltage value VDATA2_H.

Next, please refer to FIG. 2 and FIG. 4C simultaneously. In this embodiment, FIG. 4C is an equivalent circuit diagram when the pixel circuit 100 operates in the light-emitting phase EP of the second operation mode.

Specifically, in the light-emitting phase EP, the voltage regulator 120 can provide the system high voltage VDD to the node P1 through the conduction path of the transistor T1 according to the pulled-down light-emitting control signal EM, so that the voltage level of the node P1 is adjusted. Adjust to the voltage value of system high voltage VDD.

Then, the voltage regulator 120 can adjust the voltage level of the control terminal CT1 to a voltage between the reference voltage VREF, the system high voltage VDD, the data voltage VDATA1 and the critical voltage VTH5 of the transistor T5 through the coupling effect of the capacitor C1 The sum of the differences. That is, the voltage level of the control terminal CT1 at this time is VREF+(VDD-VDATA1-|VTH5|).

In this case, the transistor T2 of the voltage regulator 120 can The voltage level of CT1 generates a driving current I1 to the driving circuit 110 . The current magnitude of the driving current I1 at this time can be represented by the above formula (1).

On the other hand, in the light-emitting phase EP of the second operation mode, the data voltage VDATA2 of this embodiment can be set to the second voltage value VDATA2_L (ie, 0V). In this case, in the sub-phase EP1 of the light-emitting phase EP of the second operating mode, the voltage regulator 130 can provide the data voltage VDATA2 to the node through the conduction path of the transistor T6 according to the source driving signal S4 that is pulled down. P2, so that the voltage level of the node P2 is pulled down to the second voltage value VDATA2_L.

Then, the voltage regulator 130 can pull down the voltage level of the control terminal CT2 to between the reference voltage VREF, the threshold voltage VTH9 of the transistor T9 and the voltage variation ΔVDATA2 of the data voltage VDATA2 through the coupling effect of the capacitor C2 voltage difference. That is, the voltage level of the control terminal CT2 at this time is VREF-|VTH9|-ΔVDATA2. The above-mentioned voltage change amount ΔVDATA2 is the voltage difference between the first voltage value VDATA2_H and the second voltage value VDATA2_L (that is, VDATA2_H-VDATA2_L).

In this case, the transistor T9 of the voltage regulator 130 can generate the driving current I2 to the driving circuit 110 according to the voltage level of the control terminal CT2. Among them, the driving current I2 can be shown as the following formula (2): I2=K(VREF-(VREF-|VTH9|-△VDATA2)-|VTH9|)^2=K(△VDATA2)^2 Equation ( 2)

That is to say, in the second operating mode, the current magnitude of the on-current ID generated by the driving circuit 110 may be the sum of the driving current I1 and the driving current I2 current value. Among them, the on-current ID at this time can be shown as the following formula (3): ID=I1+I2=K(VDATA1-VREF)^2+K(△VDATA2)^2 Formula (3)

Among them, the above ID is the current value of the on-current ID; K is the process parameter of the driving transistor TD; VDATA1 is the voltage value of the data voltage VDATA1; VREF is the voltage value of the reference voltage VREF; △VDATA2 is the voltage change of the data voltage VDATA2 quantity.

Next, please refer to FIG. 2 and FIG. 4D simultaneously. In this embodiment, FIG. 4D is an equivalent circuit diagram when the pixel circuit 100 operates in the cut-off phase TP of the second operation mode. Among them, since the voltage levels of the control terminals CT1, CT2 and node P1 of the pixel circuit 100 shown in FIG. 4D are the same as the voltage levels of the control terminals CT1, CT2 and node P1 of the pixel circuit 100 shown in FIG. 3D , therefore, the voltage state of each node of the pixel circuit 100 in FIG. 4D during the cut-off phase TP can be deduced by analogy with reference to the relevant description of the pixel circuit 100 shown in FIG. 3D , and will not be described again.

Different from the embodiment of FIG. 3D , in the embodiment of FIG. 4D , the data voltage VDATA2 may be set to the second voltage value VDATA2_L (ie, 0V). Therefore, the voltage regulator 130 can turn off the transistor T6 according to the pulled-up source driving signal S4, so that the voltage level of the node P2 is maintained at the second voltage value VDATA2_L of the data voltage VDATA2.

According to the above description, it can be known that when the pixel circuit 100 operates in the light-emitting stage of the first operating mode (that is, the low grayscale display state), the luminous brightness of the light-emitting element LED can be determined only through the voltage regulator 120 , and when the pixel circuit 100 operates in the second operation mode (ie, high grayscale display state), the light emitting During this stage, the additional voltage regulator 130 and the voltage regulator 120 can be used to jointly determine the brightness of the light-emitting element LED.

In this way, the pixel circuit 100 of this embodiment can control the grayscale state of the display screen through two current paths to reduce the cross-voltage between the system high voltage VDD and the system low voltage VSS, and to improve power consumption. Effect.

In addition, the pixel circuit 100 of this embodiment can also compensate for the variation of the threshold voltage of the transistor, thereby improving the consistency of the on-current ID and improving the display quality.

FIG. 5 is a flow chart of a driving method of a pixel circuit according to an embodiment of the present invention. Please refer to FIG. 1 and FIG. 5 simultaneously. In step S510, the pixel circuit 100 causes the driving circuit 110 to generate the on-current ID according to the light emission control signal EM. In step S520, the pixel circuit 100 causes the voltage regulator 120 to adjust the voltage level of the control terminal CT1 of the voltage regulator 120 according to the light emission control signal EM, the source driving signal S3, the data voltage VDATA1 and the reference voltage VREF, and according to The voltage level of the terminal CT1 is controlled to generate the driving current I1. In step S530, the pixel circuit 100 causes the voltage regulator 130 to adjust the control terminal CT2 of the voltage regulator 130 according to the source drive signal S1, the source drive signal S2, the source drive signal S4, the data voltage VDATA2 and the reference voltage VREF. The voltage level of the control terminal CT2 is used to generate the driving current I2 according to the voltage level of the control terminal CT2. In step S540, in the first operation mode, the pixel circuit 100 makes the conduction current ID equal to the current value of the driving current I1. In the second operation mode, the pixel circuit 100 makes the conduction current ID equal to the driving current. The current value of the sum of I1 and drive current I2.

The implementation details of each step in Figure 5 have been described in detail in the foregoing embodiments and implementations, and will not be described again here.

To sum up, the pixel circuit according to the embodiments of the present invention can determine the luminous brightness of the light-emitting element only through the main voltage regulator in the low-grayscale display state, and through an additional voltage regulator in the high-grayscale display state. The voltage regulator and the main voltage regulator jointly determine the brightness of the light-emitting element. In this way, the pixel circuit can control the grayscale state of the display screen through two current paths to reduce the cross-voltage between the system high voltage and the system low voltage, and achieve the effect of improving power consumption.

100: Pixel circuit

110: Drive circuit

120, 130: Voltage regulator

C1~C3: capacitor

CT1, CT2: control terminal

EM: Luminous control signal

ID: conduction current

I1, I2: drive current

LED: light emitting element

P1, P2: nodes

S1~S4: source drive signal

T1~T9: Transistor

TD: drive transistor

VREF: reference voltage

VL: low voltage

VSS: system low voltage

VDD: system high voltage

VDATA1, VDATA2: data voltage

Claims (16)

A pixel circuit including: a driving circuit that generates a conduction current based on a lighting control signal; A first voltage regulator has a first control terminal. The first voltage regulator is coupled to the drive circuit. According to the light emission control signal, a third source drive signal, a first data voltage and a reference voltage To adjust the voltage level of the first control terminal and generate a first driving current according to the voltage level of the first control terminal; and A second voltage regulator has a second control terminal. The second voltage regulator is coupled to the drive circuit and operates based on a first source drive signal, a second source drive signal, and a fourth source drive signal. signal, a second data voltage and the reference voltage to adjust the voltage level of the second control terminal, and generate a second driving current according to the voltage level of the second control terminal, Wherein, in a first operating mode, the magnitude of the on-current is the current value of the first driving current, and in a second operating mode, the magnitude of the on-current is the first driving current and the second driving current. The sum of the current values. The pixel circuit of claim 1, wherein in a reset phase of the first operation mode or the second operation mode, the first voltage regulator provides The reference voltage is used to pull up the voltage level of the first control terminal, and the second voltage regulator provides a low voltage to pull down the voltage level of the second control terminal according to the first source driving signal being pulled down. . The pixel circuit of claim 1, wherein in a compensation phase of the first operation mode or the second operation mode, the second voltage regulator provides The reference voltage is used to charge the second control terminal. The pixel circuit of claim 1, wherein in a light-emitting phase of the first operation mode, the first voltage regulator pulls down the voltage level of the first control terminal according to the light-emitting control signal that is pulled down. , and generates the first driving current to the driving circuit, and the second voltage regulator increases the voltage level of the second control terminal according to the second data voltage and the fourth source driving signal that is pulled down, And stop generating the second driving current. The pixel circuit of claim 4, wherein in the light-emitting phase of the second operation mode, the first voltage regulator pulls down the voltage level of the first control terminal according to the light-emitting control signal that is pulled down. , and generates the first drive current to the drive circuit, and the second voltage regulator pulls down the voltage level of the second control terminal according to the second data voltage and the pulled-down fourth source drive signal, and generate the second driving current to the driving circuit. The pixel circuit of claim 5, wherein when the second data voltage is set to a first voltage value, the pixel circuit operates in the first operation mode, and when the second data voltage is set to When a second voltage value is reached, the pixel circuit operates in the second operation mode, wherein the first voltage value is greater than the second voltage value. The pixel circuit as claimed in claim 1, wherein the driving circuit includes: a driving transistor, a first terminal of which is coupled to the first voltage regulator and the second voltage regulator, and a control terminal of which receives the light-emitting control signal; and A light-emitting element has its anode terminal coupled to the second terminal of the driving transistor and its cathode terminal coupled to a system low voltage. The pixel circuit of claim 1, wherein the first voltage regulator includes: A first transistor, its first terminal is coupled to a system high voltage, its second terminal is coupled to a first node, and its control terminal receives the light-emitting control signal; a second transistor with a first terminal coupled to the system high voltage, a second terminal coupled to the drive circuit, and a control terminal coupled to the first control terminal; a third transistor with a first terminal coupled to the reference voltage, a second terminal coupled to the first control terminal, and a control terminal receiving the third source driving signal; a fourth transistor with a first terminal coupled to the first node and a control terminal receiving the third source driving signal; a fifth transistor, a first terminal of which receives the second source drive signal, a second terminal of which is coupled to the second terminal of the fourth transistor, and a control terminal of which is coupled to the first data voltage; and A capacitor is coupled between the first control terminal and the first node. The pixel circuit of claim 8, wherein the second transistor and the fifth transistor match each other. The pixel circuit of claim 1, wherein the second voltage regulator includes: a first transistor with a first terminal coupled to the second data voltage, a second terminal coupled to a first node, and a control terminal receiving the fourth source driving signal; a second transistor with a first terminal coupled to a low voltage, a second terminal coupled to the second control terminal, and a control terminal receiving the first source driving signal; a third transistor with a first end coupled to the drive circuit, a second end coupled to the second control end, and a control end receiving the second source drive signal; a fourth transistor with a first terminal coupled to the reference voltage, a second terminal coupled to the drive circuit, and a control terminal coupled to the second control terminal; a first capacitor coupled between the second control terminal and the first node; and A second capacitor is coupled between the first node and the reference voltage. A driving method for pixel circuits, including: causing a driving circuit to generate a conductive current according to a lighting control signal; A first voltage regulator is caused to adjust the voltage level of a first control terminal of the first voltage regulator according to the lighting control signal, a third source driving signal, a first data voltage and a reference voltage, and based on The voltage level of the first control terminal is used to generate a first driving current; causing a second voltage regulator to adjust the voltage of the second voltage regulator according to a first source drive signal, a second source drive signal, a fourth source drive signal, a second data voltage and the reference voltage. a voltage level of a second control terminal, and generate a second driving current according to the voltage level of the second control terminal; and In a first operation mode, the magnitude of the conduction current is the current value of the first driving current, and in a second operation mode, the magnitude of the conduction current is the first driving current and the second driving current. The sum of the current values. The driving method as described in claim 11, wherein the driving method further includes: In a reset phase of the first operation mode or the second operation mode, the first voltage regulator is caused to provide the reference voltage to pull up the first control terminal according to the third source driving signal being pulled down. voltage level, and causes the second voltage regulator to provide a low voltage according to the first source driving signal being pulled down to pull down the voltage level of the second control terminal. The driving method as described in claim 11, wherein the driving method further includes: In a compensation phase of the first operation mode or the second operation mode, the second voltage regulator is caused to provide the reference voltage according to the pulled-down second source driving signal to perform operation on the second control terminal. Charge. The driving method as described in claim 11, wherein the driving method further includes: In a lighting phase of the first operation mode, the first voltage regulator is caused to pull down the voltage level of the first control terminal according to the pulled down lighting control signal, thereby generating the first driving current to the driving circuit, and causes the second voltage regulator to raise the voltage level of the second control terminal according to the second data voltage and the pulled-down fourth source drive signal, and stop generating the second drive current. The driving method as described in claim 14, wherein the driving method further includes: In the light-emitting phase of the second operation mode, the first voltage regulator is caused to pull down the voltage level of the first control terminal according to the pulled-down light-emitting control signal to generate the first driving current to the driving circuit, and causes the second voltage regulator to pull down the voltage level of the second control terminal according to the second data voltage and the pulled-down fourth source drive signal to generate the second drive current to the drive circuit. The driving method of claim 15, wherein when the second data voltage is set to a first voltage value, the pixel circuit is operated in the first operation mode, and when the second data voltage is set to When a second voltage value is reached, the pixel circuit is operated in the second operation mode, wherein the first voltage value is greater than the second voltage value.

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