TWI749825B - Sweep generator circuit - Google Patents

Abstract

A sweep generator circuit including a driving stage and a buffer stage is provided. The driving stage receives a switch signal and a reset signal to provide a sweep reference voltage. The buffer stage receives the sweep reference voltage to provide a sweep signal in response to the sweep reference voltage. The sweep signal is dropped from a preset level to a stop level in response to a level switching of the reset signal.

Description

Ramp generation circuit

The present invention relates to a ramp wave generating circuit, and more particularly to a ramp wave generating circuit of a miniature light emitting diode display.

In recent years, self-luminous displays have risen. Among them, organic light-emitting diode displays (OLED) and quantum dot light-emitting diode displays (QLED) compete for the monopoly of liquid crystal displays (LCD) in display panels. -LED) display is expected to become the mainstream of next-generation display technology based on its many excellent component characteristics.

In a miniature light-emitting diode display, the pixel circuit can receive a ramp signal from an external digital-to-analog converter and use the ramp signal and written data to determine the current width of the diode. In addition, the digital-to-analog converter converts the digital control signal provided by the field programmable logic gate array (FPGA) into an analog signal to generate the required waveform. However, the above method has a more complicated drive structure and higher cost.

The present invention provides a ramp wave generating circuit, which has a relatively simple circuit structure, and therefore does not require a digital-to-analog converter with high cost and complicated control, so as to reduce the overall hardware cost and control complexity.

The ramp wave generating circuit of the present invention includes a driver stage and a buffer stage. The driver stage receives the switch signal and the reset signal to provide a ramp reference voltage. The buffer stage receives the ramp reference voltage and provides a ramp signal in response to the ramp reference voltage. The ramp signal reflects the level switch of the reset signal from the preset level to the stop level.

Based on the foregoing, in the ramp wave generating circuit of the embodiment of the present invention, the ramp wave generating circuit is composed of a driver stage and a buffer with a relatively simple circuit structure, thereby eliminating the need for high cost and complicated control of digital-to-analog converters, thereby reducing the overall The cost of hardware and the complexity of control.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meaning in the context of related technologies and the present invention, and will not be interpreted as idealized or excessive The formal meaning, unless explicitly defined as such in this article.

It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or parts, these elements, components, regions, and/or Or part should not be restricted by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, the “first element”, “component”, “region”, “layer” or “portion” discussed below may be referred to as a second element, component, region, layer or section without departing from the teachings herein.

The terminology used here is only for the purpose of describing specific embodiments and is not restrictive. As used herein, unless the content clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include the plural forms, including "at least one." "Or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the related listed items. It should also be understood that when used in this specification, the terms "including" and/or "including" designate the presence of the features, regions, wholes, steps, operations, elements, and/or components, but do not exclude one or more The existence or addition of other features, regions as a whole, steps, operations, elements, components, and/or combinations thereof.

FIG. 1 is a system schematic diagram of a ramp wave generating circuit according to an embodiment of the present invention. Referring to FIG. 1, in an embodiment of the present invention, the ramp wave generating circuit 100 can be applied to a display, especially an active micro light emitting diode display, and provides a ramp signal V _SWEEP to a display panel (not shown) Pixel PX, where the ramp wave generating circuit 100 can be configured in the drive circuit (not shown) of the display, for example, in the source driver (not shown) of the display, but the embodiment of the present invention is not limited to this .

In this embodiment, the ramp wave generating circuit 100 includes a driver stage 110 and a buffer stage 120. The driver stage 110 receives the switch signal SW and the reset signal RESET to provide a ramp reference voltage Vx, and the buffer stage 120 receives the ramp reference voltage Vx to provide a ramp signal V _SWEEP in response to the ramp reference voltage Vx. Among them, the ramp signal V _SWEEP reflects the level switch of the reset signal RESET from the preset level (VP2 shown in FIG. 2) to the stop level (VT2 shown in FIG. 2).

In this embodiment, the driver stage 110 is only composed of transistors and capacitors, and the buffer stage 120 is only composed of transistors. Therefore, the ramp wave generating circuit 100 has a simpler circuit structure, thereby eliminating the need for high cost and complicated control. Digital-to-analog converter to reduce overall hardware cost and control complexity.

In this embodiment, the driving stage 110 includes a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor C1, and a second capacitor C2. The first capacitor C1 has a first terminal and a second terminal coupled to the ramp reference voltage Vx. The first transistor T1 has a first terminal coupled to the second terminal of the first capacitor C1, a second terminal receiving the gate low voltage VGL, and a control terminal coupled to the first terminal of the first capacitor C1.

The second transistor T2 has a first terminal receiving the first voltage V1, a second terminal coupled to the second terminal of the first capacitor C1, and a control terminal receiving the reset signal RESET. The third transistor T3 has a first terminal receiving the first bias voltage VB1, a second terminal coupled to the first terminal of the first capacitor C1, and a control terminal receiving the switch signal SW. The second capacitor C2 is coupled between the ramp reference voltage Vx and the gate low voltage VGL.

The buffer stage 120 includes a fourth transistor T4 and a fifth transistor T5. The fourth transistor T4 has _{a first terminal for providing the ramp signal V SWEEP,} a second terminal for receiving the gate low voltage VGL, and a control terminal for receiving the ramp reference voltage Vx. The fifth transistor T5 has a first terminal receiving the gate voltage VGH, a second terminal coupled to the first terminal of the fourth transistor T4, and a control terminal receiving the second bias voltage VB2.

In the embodiment of the present invention, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are each a P-type transistor. In addition, the first transistor T1 can operate in the cut-off region as a low-current current source, and the fourth transistor T4 and the fifth transistor T5 can operate in the saturation region as an on switch.

In the embodiment of the present invention, the aspect ratio of the first transistor T1 may be the same as the aspect ratio of the third transistor T3, but smaller than the aspect ratio of the second transistor T2. The aspect ratio of the fourth transistor T4 and the fifth transistor T5 may be the same, and may be greater than the aspect ratio of the second transistor T2.

2 is a schematic diagram of driving waveforms of a ramp wave generating circuit according to an embodiment of the present invention. 1 and 2, when the reset signal RESET and the switch signal SW switch from the high voltage level VH to the low voltage level VL, the second transistor T2 and the third transistor T3 will be turned on, so the first bias The voltage VB1 is transmitted to the control terminal of the first transistor T1, and the first voltage V1 is transmitted to the second capacitor C2.

In order to make the first transistor T1 operate in the cut-off region (or called the subcritical region), the first bias voltage VB1 can be approximately the first voltage V1 minus the threshold voltage of the first transistor T1 (ie VB1≈V1-|V _TH1 |), at this time, the source-drain voltage V _{SG1 of the} first transistor T1 will be stored in the first capacitor C1. In addition, the ramp reference voltage Vx is charged through the first voltage V1 to rise to the first predetermined voltage VP1, wherein the first predetermined voltage VP1 is approximately equal to the first voltage V1.

Moreover, in order to make the fifth transistor T5 operate in the saturation region, the second bias voltage VB2 may be greater than or equal to the level of the ramp signal V _SWEEP minus the threshold voltage of the first transistor T5 (that is, VB2≧V _SWEEP -|V _TH5 |), and a fourth transistor T4 and the fifth transistor T5 operates in the saturation region, level of the ramp signal V ramp _SWEEP is equal to the reference power source voltage Vx add a fourth drain voltage V crystal of T4 _SG4 (that is, V _SWEEP =Vx+V _SG4 ).

Since the fourth transistor T4 and the fifth transistor T5 are on the same current path, the current I4 flowing through the fourth transistor T4 is equal to the current I5 of the fifth transistor T5. At this time, the current I4 flowing through the fourth transistor T4 is (1/2)u _p C _ox (W/L) ₄ (V _SWEEP -Vx-|V _TH4 |) ² and flows through the fifth transistor T5 The current I5 is (1/2)u _p C _ox (W/L) ₅ (VGH-VB2-|V _TH5 |) ² . The aspect ratio (W/L) _{4 of the} fourth transistor T4 is equal to the aspect ratio (W/L) _{5 of the fifth transistor T5 and the threshold voltage V TH4 of the} fourth transistor T4 is equal to that of the fifth transistor T5 When the threshold voltage V _{TH5 is} equal, the level of the ramp signal V _SWEEP is equal to the ramp reference voltage Vx plus the gate high voltage VGH and then minus the second bias voltage VB2 (that is, V _SWEEP =Vx+VGH−VB2). In other words, the second preset level VP2 is equal to the first preset voltage VP1 plus the gate high voltage VGH minus the second bias voltage VB2, that is, the preset level VP2 of the _{ramp signal V SWEEP is controlled by the first preset voltage VP1.} Two bias voltage VB2.

Before the reset signal RESET is switched to the high voltage level VH, due to the charging effect of the first voltage V1, the ramp reference voltage Vx maintains the first preset voltage VP1, and the level of the ramp signal V _SWEEP is maintained at the second preset level Level VP2. When the reset signal RESET switches from the low voltage level VL to the high voltage level VH, the ramp reference voltage Vx responds to the level switch of the reset signal RESET and drops from the first preset level VP1 to the first stop level VT1 , And the ramp signal V _SWEEP reflects the level switch of the reset signal RESET from the second preset level VP2 to the second stop level VT2.

In the embodiment of the present invention, the first stop level VT1 is approximately equal to the first voltage minus the current I1 flowing through the first transistor T1 divided by the capacitance value of the second capacitor C2 and multiplied by the fall time t _EM . (That is, VT1=V1-(I1/C2).t _EM ). In other words, _{the falling slope of the ramp signal V SWEEP} is controlled by the first voltage V1 and the first bias voltage VB1.

In this embodiment, the switch signal SW and the reset signal RESET are, for example, different signals, and the duration P2 during which the switch signal SW is at the low voltage level VL is less than the duration P1 during which the reset signal RESET is at the low voltage level VL. However, in other embodiments, the switch signal SW and the reset signal RESET may be the same signal (that is, the same signal), thereby reducing the number of wires in the circuit layout and reducing the complexity of the circuit layout.

In summary, in the ramp wave generating circuit of the embodiment of the present invention, the ramp wave generating circuit is composed of a driver stage and a buffer with a relatively simple circuit structure, thereby eliminating the need for high cost and complex control digital-to-analog converters. Reduce overall hardware cost and control complexity. Moreover, the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor may all be P-type transistors, thereby simplifying the complexity of the manufacturing process.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to those defined by the attached patent scope.

100: ramp wave generating circuit 110: driver stage 120: buffer stage C1: first capacitor C2: second capacitor I1, I4, I5: current P1, P2: duration PX: pixel RESET: reset signal SW: switch signal T1: first transistor T2: second transistor T3: third transistor T4: fourth transistor T5: fifth transistor t _EM : fall time V1: first voltage VB1: first bias voltage VB2: second Bias voltage VGH: gate high voltage VGL: gate low voltage VH: high voltage level VL: low voltage level VP1: first preset voltage VP2: second preset level V _SG4 : source-drain voltage V _SWEEP : Ramp signal VT1: first stop level VT2: second stop level Vx: ramp reference voltage

FIG. 1 is a system schematic diagram of a ramp wave generating circuit according to an embodiment of the present invention. 2 is a schematic diagram of driving waveforms of a ramp wave generating circuit according to an embodiment of the present invention.

100: ramp wave generating circuit

110: driver stage

120: Buffer level

C1: The first capacitor

C2: second capacitor

I1, I4, I5: current

PX: pixel

RESET: reset signal

SW: Switch signal

T1: The first transistor

T2: second transistor

T3: third transistor

T4: Fourth transistor

T5: fifth transistor

V1: first voltage

VB1: first bias

VB2: second bias voltage

VGH: Very high gate voltage

VGL: Low gate voltage

V _SG4 : source-drain voltage

V _SWEEP : ramp signal

Vx: ramp reference voltage

Claims (8)

A ramp wave generating circuit includes: a drive stage that receives a switch signal and a reset signal to provide a ramp wave reference voltage; and a buffer stage that receives the ramp wave reference voltage to reflect the ramp wave reference voltage supply A ramp signal, wherein the ramp signal responds to the level switch of the reset signal falling from a preset level to a stop level, wherein the driving stage includes: a first capacitor having a first terminal, And a second terminal coupled to the ramp reference voltage; a first transistor having a first terminal coupled to the second terminal of the first capacitor, a second terminal receiving a gate low voltage, And a control terminal coupled to the first terminal of the first capacitor; a second transistor having a first terminal receiving a first voltage, and a second terminal coupled to the second terminal of the first capacitor , And a control terminal receiving the reset signal; a third transistor having a first terminal receiving a first bias, a second terminal coupled to the first terminal of the first capacitor, and receiving A control terminal of the switch signal; and a second capacitor, coupled between the ramp reference voltage and the gate low voltage. The ramp wave generating circuit according to claim 1, wherein the first transistor is operated in the cut-off region. The ramp wave generating circuit according to claim 1, wherein the falling slope of the ramp signal is controlled by the first voltage and the first bias voltage. The ramp wave generating circuit according to claim 1, wherein the buffer stage includes: a fourth transistor having a first end for providing the ramp signal, a second end for receiving the gate low voltage, and receiving A control terminal of the ramp reference voltage; and a fifth transistor having a first terminal receiving an extremely high voltage, a second terminal coupled to the first terminal of the fourth transistor, and receiving A control terminal of a second bias. The ramp wave generating circuit according to claim 4, wherein the fourth transistor and the fifth transistor operate in a saturation region. The ramp wave generating circuit according to claim 4, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are each a P-type transistor. The ramp wave generating circuit according to claim 3, wherein the preset level of the ramp signal is controlled by the second bias voltage. The ramp wave generating circuit according to claim 1, wherein the switch signal and the reset signal are the same signal.

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