JP2014207569A - Ramp wave generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for suppressing a fluctuation in the amplitude of a ramp waveform of an output voltage VOUT due to variations in a capacitance C1 of a capacitor, a constant current Io and a ramp wave generation period T when a ramp wave generation circuit is implemented in an integrated circuit.SOLUTION: In an embodiment, the ramp wave generation circuit includes: an operational amplifier having a positive input terminal connected to a first reference voltage; the capacitor inserted between a negative input terminal and an output terminal of the operational amplifier; and a current source for injecting a constant current into the operational amplifier. The ramp wave generation circuit specifies a current value of the current source by a second reference voltage and a switched capacitor resistor manufactured in the same manufacturing process as the capacitor, and uses any of a single reference clock or a multiplied or divided output thereof as a clock for driving the switched capacitor resistor and a clock for a timer for deciding the ramp wave output period, and the like.

Description

The present invention relates to a ramp wave generation circuit using a charge / discharge operation of a capacitor.

A general configuration of the ramp wave generating circuit is shown in FIG.
In FIG. 1, E1 is the voltage value of the DC power supply 1, SW1 and SW2 are switch circuits, C1 is the capacitance of the capacitor 2, VOUT is the voltage value at the output voltage terminal 3, and Io is the current value of the constant current source 4.

FIG. 2 shows voltage waveforms representing the operation of the circuit of FIG.
In the circuit of FIG. 1, the output voltage VOUT is initially set to the voltage E1 with SW1 off and SW2 on.
When SW1 is turned on and SW2 is turned off, a charging (or discharging) current flows through the capacitor 2, and a ramp waveform voltage is generated at VOUT. Specifically, since the electric charge accumulated in the capacitor 2 is charged or discharged by a constant current source, the output voltage VOUT changes with a certain slope with respect to time.
Thereafter, the output voltage VOUT is initialized to the reference voltage E1 by switching SW1 off and SW2 on again. By repeating such an operation, the ramp waveform shown in FIG. 2 is generated.

In the above operation, when the time t when the SW1 is turned on and the SW2 is turned on to transition to the ramp wave generation period in which SW1 is turned on and SW2 is turned off is set to 0, the output voltage VOUT is expressed by the following equation. be able to.
VOUT = E1- (Io / C1) t (1)
Here, assuming that the ramp wave generation period is T, the amplitude of the ramp wave is (Io / C1) T.

However, in this conventional circuit, the time slope and amplitude of the ramp waveform vary due to variations in the capacitance C1 of the capacitor 2 and variations in the constant current Io.

Further, the ramp wave generation period T also varies with variations in the characteristics of the timer that determines the ramp wave generation period T, which can also be a variation factor of the ramp wave amplitude.

This state is indicated by a one-dot chain line in FIG.

For example, when the ramp wave generation circuit is applied to the generation of the reference voltage of the integral type A / D converter, the variation in the time slope and amplitude of the output ramp wave becomes the variation in the resolution of the A / D conversion and the measurable range. End up.

In order to suppress such variations in the ramp waveform, a trimming circuit and a correction circuit that finely adjust the integrated current Io are used. (For example, refer to Patent Document 1).

JP-A-6-326565

When the conventional circuit is mounted as an integrated circuit, the amplitude of the ramp waveform of the output voltage VOUT caused by the variation of the capacitance C1 of the capacitor 2, the current Io supplied from the constant current source 4 and the ramp wave generation period T is shown. A method for suppressing fluctuations is provided.

According to the ramp wave generation circuit of the embodiment, an operational amplifier whose positive input terminal is connected to the first reference voltage, a capacitor inserted between the negative input terminal and the output terminal, and a constant current are injected into the operational amplifier. And a current value of the second reference voltage and a switched capacitor resistor manufactured in the same manufacturing process as the capacitor. A driving clock of the switched capacitor resistor and a ramp wave output period It is characterized in that a single reference clock, or a multiplication or division output thereof is used as a clock for determining a timer.

As a specific example of the combination of the switched capacitor driving clock and the clock such as a timer, the switched capacitor resistor can be driven by the counter clock signal in the integrating A / D converter.

According to the ramp wave generation circuit of the present invention, the constant current Io increases / decreases in conjunction with the variation fluctuation amount of the capacitor capacitance C1, so that the fluctuation of the time ramp of the output ramp wave determined by the ratio of both is suppressed, It is possible to suppress fluctuations in the amplitude of the wave output.

Further, since the resistance value of the switched capacitor resistance is proportional to the drive frequency fclk given by the reference clock, it is possible to cancel the amplitude fluctuation accompanying the fluctuation of the ramp wave generation period T due to the variation of the timer.

For this reason, it is possible to reduce the correction circuit and the trimming circuit, or the scale, which are necessary for increasing the accuracy of the ramp wave generation circuit.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a circuit diagram showing an example of the configuration of the ramp wave generation circuit according to the embodiment of the present invention.

The ramp wave generation circuit of this embodiment includes an integration circuit 1 in which an integration capacitor 12 is connected between the input and output terminals of the operational amplifier OP1, and a current source unit 2 that outputs a charging current.

The current source unit 2 has a second reference voltage E2, a capacitor 22 formed by the same manufacturing process as the integrating capacitor 12, two switch circuits SW21 and SW22, and a frequency fclk for driving these switch circuits. It is generated by a switched capacitor resistor consisting of a clock circuit. At this time, the constant current output Io2 of the current source unit 2 is Io2 = E2 · C2 · fclk.

The clocks for driving the switch groups SW11 and SW22 for controlling the generation and initial value setting of the ramp wave in the integration circuit 1 and the switch groups SW21 and SW22 for controlling the switched capacitors in the current source unit 2 are a single reference clock. , Or its multiplication or division output.

Therefore, the ramp waveform output in this embodiment can be defined by the following equation from the above equation (1).
VOUT = E1- (C2 / C1) E2 / fclk.t (2)

Here, when the capacitors 12 and 22 are formed in the same manufacturing process, the deviation of the capacitance values C1 and C2 due to the manufacturing variation of both has the same tendency, and the fluctuation due to the manufacturing variation of the ramp time gradient is suppressed. The

Further, when the ramp wave generation period T is determined by N division of fclk, the amplitude A is A = (C2 / C1) E2 · N (3)
Therefore, according to the present invention, there is an effect of correcting the fluctuation of the ramp wave amplitude with respect to the fluctuation of the ramp wave generation period T accompanying the variation of the timer circuit.

As an application example of the ramp wave generation circuit to an electronic device, the configuration of an integrating A / D converter will be described with reference to FIG.

The integrating A / D converter includes a ramp wave generation circuit 1 described in the first embodiment, a comparator 4 that compares the ramp wave output VOUT with an input signal, a counter 5, and a frequency of a reference clock signal. And a device for frequency division or multiplication by a phase lock loop circuit or the like.

The counter 5 starts counting operation of the counting clock simultaneously with the start of the ramp wave generation period T of the ramp wave generating circuit 3, and stops the counting operation when the output of the comparator 4 is inverted as a trigger input. is there.

The time from the start of ramp wave generation to the output inversion of the comparator 4 is proportional to the magnitude of the input signal, and A / D conversion is performed by reading the count value of the counter 5 at the end of the counting operation.

Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the claims.

As described above, according to the present invention, variation in the amplitude of the output waveform by the ramp wave generation circuit is suppressed, so that the trimming circuit can be deleted or scaled down.

FIG. 1 is a configuration diagram of a ramp wave generation circuit. FIG. 2 is an explanatory diagram showing an output voltage waveform of the ramp wave generation circuit of FIG. FIG. 3 is an explanatory diagram showing the configuration of the first embodiment of the present invention. FIG. 4 is an explanatory diagram showing the configuration of the second embodiment of the present invention.

Claims (4)

An operational amplifier having a positive input terminal connected to the first reference voltage, a first capacitor inserted between the negative input terminal and the output terminal, and a current source that injects a constant current into the negative input terminal of the operational amplifier. The current value is composed of a second reference voltage and a switched capacitor resistor composed of a second capacitor manufactured in the same manufacturing process as the capacitor, and a driving clock of the switched capacitor resistor, A ramp wave generating circuit characterized in that a clock such as a timer for determining a ramp wave output period uses either a single reference clock or a multiplied or divided output thereof. A ramp wave generation circuit that obtains a first reference voltage and a second reference voltage from a single power source in the ramp wave generation circuit. A ramp wave output of the ramp wave generation circuit according to claim 1 or 2 as a reference voltage, a comparator for comparing with an input signal, a clock signal input, and a cycle of a ramp waveform of the ramp wave generation circuit An integration type A / D converter that takes out the count value of the counter and outputs a digital conversion output when the output of the comparator is inverted, in the ramp wave generation circuit. Applied to an integrated A / D converter characterized in that the switched capacitor drive clock that generates the reference current and the count clock of the counter use either a single reference clock, or its multiplied or divided output. Ramp wave generation circuit. An electronic device using the ramp wave generation circuit according to claim 1 or 2, wherein a clock generated by the electronic device itself is used as a reference clock of the ramp wave generation circuit. Applied ramp wave generation circuit.

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