CN112967672A - Ramp wave generating circuit - Google Patents

Ramp wave generating circuit Download PDF

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Publication number
CN112967672A
CN112967672A CN202110270595.2A CN202110270595A CN112967672A CN 112967672 A CN112967672 A CN 112967672A CN 202110270595 A CN202110270595 A CN 202110270595A CN 112967672 A CN112967672 A CN 112967672A
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China
Prior art keywords
ramp
transistor
terminal
voltage
signal
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CN202110270595.2A
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CN112967672B (en
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陈彦儒
洪嘉泽
刘恩池
庄锦棠
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AU Optronics Corp
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AU Optronics Corp
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Electronic Switches (AREA)

Abstract

A ramp generating circuit includes a driving stage and a buffer stage. The driving stage receives the switching signal and the reset signal to provide a ramp reference voltage. The buffer stage receives the ramp reference voltage to provide a ramp signal in response to the ramp reference voltage. The ramp signal falls from a preset level to a stop level in response to the level switching of the reset signal.

Description

Ramp wave generating circuit
Technical Field
The present invention relates to a ramp generating circuit, and more particularly to a ramp generating circuit for a micro light emitting diode display.
Background
In recent years, light emitting displays have grown, and among them, organic light emitting diode displays (OLEDs) and quantum dot light emitting diode displays (QLEDs) compete for the exclusive position of Liquid Crystal Displays (LCDs) on display panels, and Micro light emitting diode (Micro-LED) displays are expected to become the mainstream of next generation display technologies based on their many excellent element characteristics.
In a micro light emitting diode display, a pixel circuit may receive a ramp signal from an external digital-to-analog converter and determine a current width of a diode using the ramp signal and written data. The digital-to-analog converter converts a digital control signal provided by a Field Programmable Gate Array (FPGA) into an analog signal to generate a desired waveform. However, the above method has a more complicated driving structure and higher cost.
Disclosure of Invention
The invention provides a ramp wave generating circuit, which has a simpler circuit structure, so that a digital-to-analog converter with high cost and complex control is not needed, and the whole hardware cost and the control complexity are reduced.
The ramp wave generating circuit comprises a driving stage and a buffer stage. The driving stage receives the switching signal and the reset signal to provide a ramp reference voltage. The buffer stage receives the ramp reference voltage to provide a ramp signal in response to the ramp reference voltage. The ramp signal falls from a preset level to a stop level in response to the level switching of the reset signal.
In view of the above, the ramp generating circuit according to the embodiment of the invention is formed by the driving stage and the buffer having a relatively simple circuit structure, so that a digital-to-analog converter with high cost and complicated control is not required, thereby reducing the overall hardware cost and the control complexity.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a system diagram of a ramp generating circuit according to an embodiment of the invention.
Fig. 2 is a schematic diagram of driving waveforms of a ramp generating circuit according to an embodiment of the invention.
Description of reference numerals:
100: ramp wave generating circuit
110: drive stage
120: buffer stage
C1: first capacitor
C2: second capacitor
I1, I4, I5: electric current
P1, P2: duration of time
PX: pixel
RESET: reset signal
SW: switching signal
T1: a first transistor
T2: second transistor
T3: a third transistor
T4: a fourth transistor
T5: fifth transistor
tEM: time of fall
V1: first voltage
VB 1: first bias voltage
VB 2: second bias voltage
VGH gate high voltage
VGL: very low voltage of gate
VH: high voltage level
VL: low voltage level
VP 1: a first preset voltage
VP 2: second predetermined level
VSG4: source drain voltage
VSWEEP: ramp signal
VT 1: first stop level
VT 2: second stop level
Vx: ramp reference voltage
Detailed Description
Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element," "component," "region," "layer" or "portion" discussed below could be termed a second element, component, region, layer or portion without departing from the teachings herein.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms, including "at least one", unless the content clearly indicates otherwise. "or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions integers, steps, operations, elements, components, and/or groups thereof.
Fig. 1 is a system diagram of a ramp generating circuit according to an embodiment of the invention. Referring to fig. 1, in the embodiment of the invention, the ramp generating circuit 100 can be applied to a display, particularly an active micro led display, and provides a ramp signal VSWEEPTo a pixel PX in a display panel (not shown), the ramp generating circuit 100 may be disposed in a driving circuit (not shown) of the display, for example, a source driver (not shown) of the display, but the embodiment of the invention is not limited thereto.
In this embodiment, the ramp generating circuit 100 includes a driving stage 110 and a buffering stage 120. The driver stage 110 receives the switch signal SW and the RESET signal RESET to provide a ramp reference voltage Vx, and the buffer stage 120 receives the ramp reference voltage Vx to reflect the ramp reference voltage VxSupply ramp signal VSWEEP. Wherein, the ramp signal VSWEEPThe level switch in response to the RESET signal RESET falls from the preset level (VP 2 shown in fig. 2) to the stop level (VT 2 shown in fig. 2).
In the embodiment, the driving stage 110 is composed of only transistors and capacitors, and the buffering stage 120 is composed of only transistors, so that the ramp generating circuit 100 has a simpler circuit structure, thereby eliminating the need for a digital-to-analog converter with high cost and complicated control, and reducing the overall hardware cost and control complexity.
In the embodiment, the driving stage 110 includes a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor C1, and a second capacitor C2. The first capacitor C1 has a first terminal and a second terminal coupled to the ramp reference voltage Vx. The first transistor T1 has a first terminal coupled to the second terminal of the first capacitor C1, a second terminal receiving the gate low voltage VGL, and a control terminal coupled to the first terminal of the first capacitor C1.
The second transistor T2 has a first terminal receiving the first voltage V1, a second terminal coupled to the second terminal of the first capacitor C1, and a control terminal receiving a RESET signal RESET. The third transistor T3 has a first terminal receiving the first bias voltage VB1, a second terminal coupled to the first terminal of the first capacitor C1, and a control terminal receiving the switch signal SW. The second capacitor C2 is coupled between the ramp reference voltage Vx and the gate low voltage VGL.
The buffer stage 120 includes a fourth transistor T4 and a fifth transistor T5. The fourth transistor T4 has a gate terminal for providing a ramp signal VSWEEPA first terminal receiving the gate low voltage VGL, a second terminal receiving the ramp reference voltage Vx. The fifth transistor T5 has a first terminal receiving the gate high voltage VGH, a second terminal coupled to the first terminal of the fourth transistor T4, and a control terminal receiving the second bias voltage VB 2.
In the embodiment of the invention, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are each a P-type transistor. Also, the first transistor T1 may operate in the off region as a low current source, and the fourth transistor T4 and the fifth transistor T5 may operate in the saturation region as an on switch.
In the embodiment of the present invention, the aspect ratio of the first transistor T1 may be the same as that of the third transistor T3, but smaller than that of the second transistor T2. The aspect ratios of the fourth transistor T4 and the fifth transistor T5 may be the same, and may be greater than the aspect ratio of the second transistor T2.
Fig. 2 is a schematic diagram of driving waveforms of a ramp generating circuit according to an embodiment of the invention. Referring to fig. 1 and 2, when the RESET signal RESET and the switch signal SW are switched from the high voltage level VH to the low voltage level VL, the second transistor T2 and the third transistor T3 are turned on, so that the first bias voltage VB1 is transmitted to the control terminal of the first transistor T1, and the first voltage V1 is transmitted to the second capacitor C2.
In order to make the first transistor T1 operate in the cut-off region (or sub-threshold region), the first bias voltage VB1 may be about the first voltage V1 minus the threshold voltage of the first transistor T1 (i.e. VB1 ≈ V1 | V1 |)TH1| at this time, the source-drain voltage V of the first transistor T1SG1Is stored in the first capacitor C1. The ramp reference voltage Vx is charged by the first voltage V1 to rise to the first preset voltage VP1, wherein the first preset voltage VP1 is approximately equal to the first voltage V1.
Also, in order to operate the fifth transistor T5 in the saturation region, the second bias voltage VB2 may be equal to or greater than the ramp signal VSWEEPIs subtracted by the threshold voltage of the first transistor T5 (i.e., VB2 ≧ V)SWEEP-|VTH5|) and the ramp signal V is operated in the saturation region when the fourth and fifth transistors T4 and T5 are operated in the saturation regionSWEEPIs equal to the ramp reference voltage Vx plus the source-drain voltage V of the fourth transistor T4SG4(i.e., V)SWEEP＝Vx+VSG4)。
Since the fourth transistor T4 and the fifth transistor T5 are on the same current path, the current I4 flowing through the fourth transistor T4 is equal to the current I5 flowing through the fifth transistor T5. At this time, the current I4 flowing through the fourth transistor T4 is (1/2) upCox(W/L)4(VSWEEP-Vx-|VTH4|)2And flow ofThe current I5 through the fifth transistor T5 is (1/2) upCox(W/L)5(VGH-VB2-|VTH5|)2. In aspect ratio (W/L) of the fourth transistor T44Aspect ratio (W/L) to the fifth transistor T55Equal and the threshold voltage V of the fourth transistor T4TH4And the threshold voltage V of the fifth transistor T5TH5Equal, ramp signal VSWEEPIs equal to the ramp reference voltage Vx plus the gate high voltage VGH minus the second bias voltage VB2 (i.e., VSWEEPVx + VGH-VB 2). In other words, the second preset level VP2 is equal to the first preset voltage VP1 plus the gate high voltage VGH minus the second bias voltage VB2, i.e. the ramp signal VSWEEPIs controlled by the second bias voltage VB 2.
Before the RESET signal RESET is switched to the high voltage level VH, the ramp reference voltage Vx maintains the first preset voltage VP1 due to the charging effect of the first voltage V1, and the ramp signal V is switched to the high voltage level VHSWEEPIs maintained at the second preset level VP 2. When the RESET signal RESET is switched from the low voltage level VL to the high voltage level VH, the ramp reference voltage Vx drops from the first preset level VP1 to the first stop level VT1 in response to the level switch of the RESET signal RESET, and the ramp signal V1SWEEPThe level switch in response to the RESET signal RESET falls from the second preset level VP2 to the second stop level VT 2.
In the embodiment of the invention, the first stop level VT1 is approximately equal to the first voltage minus the falling time T multiplied by the value of the current I1 flowing through the first transistor T1 divided by the capacitance of the second capacitor C2EMThe resulting value (i.e., VT1 ═ V1- (I1/C2). tEM). In other words, the ramp signal VSWEEPIs controlled by the first voltage V1 and the first bias voltage VB 1.
In the present embodiment, the switch signal SW and the RESET signal RESET are different signals, for example, and the duration P2 of the switch signal SW at the low voltage level VL is less than the duration P1 of the RESET signal RESET at the low voltage level VL, but in other embodiments, the switch signal SW and the RESET signal RESET may be the same signal (i.e., the same signal), so that the number of traces in the circuit layout can be reduced, and the complexity of the circuit layout can be reduced.
In summary, in the ramp generating circuit of the embodiment of the invention, the ramp generating circuit is composed of the driving stage and the buffer with a simpler circuit structure, so that a digital-to-analog converter with high cost and complicated control is not required, and the overall hardware cost and the control complexity are reduced. In addition, the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor can all be P-type transistors, thereby simplifying the complexity of the process.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (9)

1. A ramp generating circuit comprising:
a driving stage for receiving a switching signal and a reset signal to provide a ramp reference voltage; and
a buffer stage for receiving the ramp reference voltage and providing a ramp signal in response to the ramp reference voltage,
wherein the ramp signal drops from a predetermined level to a stop level in response to the level switching of the reset signal.
2. The ramp generating circuit according to claim 1, wherein the driving stage comprises:
a first capacitor having a first terminal and a second terminal coupled to the ramp reference voltage;
a first transistor having a first terminal coupled to the second terminal of the first capacitor, a second terminal receiving a low gate voltage, and a control terminal coupled to the first terminal of the first capacitor;
a second transistor having a first terminal for receiving a first voltage, a second terminal coupled to the second terminal of the first capacitor, and a control terminal for receiving the reset signal;
a third transistor having a first terminal for receiving a first bias voltage, a second terminal coupled to the first terminal of the first capacitor, and a control terminal for receiving the switch signal; and
and a second capacitor coupled between the ramp reference voltage and the gate low voltage.
3. The ramp generating circuit as claimed in claim 2, wherein the first transistor is operated in an off region.
4. The ramp generating circuit as claimed in claim 2, wherein the falling slope of the ramp signal is controlled by the first voltage and the first bias voltage.
5. The ramp generating circuit according to claim 2, wherein the buffer stage comprises:
a fourth transistor having a first terminal for providing the ramp signal, a second terminal for receiving the gate low voltage, and a control terminal for receiving the ramp reference voltage; and
a fifth transistor having a first terminal receiving a gate high voltage, a second terminal coupled to the first terminal of the fourth transistor, and a control terminal receiving a second bias voltage.
6. The ramp wave generating circuit as claimed in claim 4, wherein the fourth transistor and the fifth transistor are operated in a saturation region.
7. The ramp wave generating circuit according to claim 4, wherein the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are each a P-type transistor.
8. The ramp generating circuit as claimed in claim 4, wherein the predetermined level of the ramp signal is controlled by the second bias voltage.
9. The ramp generating circuit as claimed in claim 1, wherein the switching signal and the reset signal are the same signal.
CN202110270595.2A 2020-10-23 2021-03-12 Ramp wave generating circuit Active CN112967672B (en)

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TW109136962A TWI749825B (en) 2020-10-23 2020-10-23 Sweep generator circuit
TW109136962 2020-10-23

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CN112967672B CN112967672B (en) 2022-12-06

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TWI818761B (en) * 2022-10-07 2023-10-11 友達光電股份有限公司 Sweep voltage generator

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CN104009628A (en) * 2013-02-22 2014-08-27 杰力科技股份有限公司 Voltage converter
JP2014207569A (en) * 2013-04-12 2014-10-30 エーシーテクノロジーズ株式会社 Ramp wave generation circuit
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US20180247590A1 (en) * 2015-09-30 2018-08-30 Sony Corporation Display element, method for driving display element, display device, and electronic device
CN110246451A (en) * 2018-03-08 2019-09-17 瑞鼎科技股份有限公司 Display device and voltage correction method
US10454461B1 (en) * 2018-05-23 2019-10-22 Anpec Electronics Corporation Frequency compensation circuit used in DC voltage converter

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US8294495B2 (en) * 2005-07-01 2012-10-23 Maxim Integrated Products, Inc. Constant slope ramp circuits for sampled-data circuits
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Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060290621A1 (en) * 2005-06-28 2006-12-28 Korea Advanced Institute Of Science And Technology Driving method and circuit for automatic voltage output of active matrix organic light emitting device and data drive circuit using the same
CN101452298A (en) * 2007-12-03 2009-06-10 英业达股份有限公司 Voltage regulator with oblique wave compensation
CN104009628A (en) * 2013-02-22 2014-08-27 杰力科技股份有限公司 Voltage converter
JP2014207569A (en) * 2013-04-12 2014-10-30 エーシーテクノロジーズ株式会社 Ramp wave generation circuit
CN106300978A (en) * 2015-05-13 2017-01-04 杰力科技股份有限公司 Voltage converter
US20180247590A1 (en) * 2015-09-30 2018-08-30 Sony Corporation Display element, method for driving display element, display device, and electronic device
CN110246451A (en) * 2018-03-08 2019-09-17 瑞鼎科技股份有限公司 Display device and voltage correction method
US10454461B1 (en) * 2018-05-23 2019-10-22 Anpec Electronics Corporation Frequency compensation circuit used in DC voltage converter

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CN112967672B (en) 2022-12-06
TW202218331A (en) 2022-05-01
TWI749825B (en) 2021-12-11

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