TWI830491B - Sweep voltage generator and operating method thereof - Google Patents

Abstract

A sweep voltage generator and an operating method thereof are provided. The sweep voltage generator includes an output stage circuit, a voltage regulator circuit, a voltage adjustment circuit and a load variation detection circuit. The output stage circuit generates a sweep signal at an output end according to a node voltage of a first control end. The voltage regulator circuit regulates the output end according to a clock signal. The voltage adjustment circuit adjusts the node voltages of a first detection end and the first control end according to a second control signal, a third control signal and a fourth control signal. The load variation detection circuit is configured to detect an output load variation on the output end through a detection path, and adjust the node voltages of the first detection end and the second detection end based on the output load variation and according to a first control signal and the fourth control signal.

Description

Ramp voltage generator and method of operation

The present invention relates to a voltage generator, and in particular to a ramp voltage generator and an operating method thereof.

In conventional display technology, the pixel circuit usually receives a ramp signal from an external digital-to-analog converter, and uses the ramp signal and written data to determine the current width or light-emitting time of the light-emitting diode. However, in the existing ramp voltage generator, the slope of the ramp signal generated by the ramp voltage generator is easily affected by the load variation at the output end and/or the critical voltage variation of the transistor, causing the pixels to be inconsistent. The gray scale control capability of the circuit is reduced.

In view of this, how to effectively compensate for the load variation and/or the critical voltage variation of the transistor so that the output waveform of the ramp signal is not affected by the variation, so as to improve the accuracy of the gray scale control of the pixel circuit, will be a relevant issue in this field. Important topics for technicians.

The invention provides a ramp voltage generator and an operating method thereof, which can detect and compensate for the load variation at the output end and the critical voltage variation of the transistor, so that the output waveform of the ramp signal is not affected by the variation, and the use of pulse width modulation is increased. The accuracy of grayscale control of the pixel circuit controlled by Pulse-width modulation (PWM).

The ramp voltage generator of the present invention includes: an output stage circuit, a voltage stabilizing circuit, a voltage adjustment circuit and a load variation detection circuit. The output stage circuit has a first control terminal and an output terminal, and generates a ramp signal at the output terminal according to the node voltage of the first control terminal. The voltage stabilizing circuit has a second control terminal. The voltage stabilizing circuit is coupled to the output terminal and regulates the voltage of the output terminal according to the clock signal. The voltage adjustment circuit has a first detection terminal. The voltage adjustment circuit is coupled to the first control terminal and the voltage stabilizing circuit, and adjusts the first detection terminal and the third control terminal according to the second control signal, the third control signal and the fourth control signal. A node voltage at the control end. The load variation detection circuit has a second detection terminal. The load variation detection circuit is coupled to the first detection terminal and the output terminal for detecting the output load variation at the output terminal through the detection path and based on the output load variation. And adjust the node voltages of the first detection terminal and the second detection terminal according to the first control signal and the fourth control signal.

The operation method of the ramp voltage generator of the present invention includes: providing an output stage circuit with a first control terminal and an output terminal, and causing the output stage circuit to generate a ramp signal at the output terminal according to the node voltage of the first control terminal; providing a A voltage stabilizing circuit with a second control terminal, and the voltage stabilizing circuit regulates the voltage of the output terminal according to the clock signal; a voltage adjustment circuit with a first detection terminal is provided, and the voltage adjustment circuit adjusts the voltage according to the second control signal and the third control terminal. signal and a fourth control signal to adjust the node voltage of the first detection terminal and the first control terminal; and provide a load variation detection circuit with a second detection terminal, and enable the load variation detection circuit to detect the output terminal through the detection path. Detect the output load variation, and adjust the node voltages of the first detection terminal and the second detection terminal based on the output load variation and the first control signal and the fourth control signal.

Based on the above, the ramp voltage generator and its operating method according to the embodiment of the present invention can effectively detect and compensate for the load variation at the output end and the critical voltage variation of the transistor, so that the output waveform of the ramp signal is not affected by the variation, and thus Increase the accuracy of grayscale control of pixel circuits controlled by pulse width modulation.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed to have meanings consistent with their meanings in the context of the relevant technology and the present invention, and are not to be construed as idealistic or excessive Formal meaning, unless expressly defined as such herein.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or sections or parts thereof shall not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element", "component", "region", "layer" or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms including "at least one" unless the content clearly dictates otherwise. "or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will also be understood that when used in this specification, the terms "comprises" and/or "includes" designate the presence of stated features, regions, integers, steps, operations, elements and/or components but do not exclude one or more The presence or addition of other features, regions, steps, operations, elements, parts and/or combinations thereof.

FIG. 1 is a schematic diagram of a ramp voltage generator according to an embodiment of the present invention. Referring to FIG. 1 , the ramp voltage generator 100 includes an output stage circuit 110 , a voltage stabilizing circuit 120 , a voltage adjustment circuit 130 and a load variation detection circuit 140 . In this embodiment, the output stage circuit 110 has a control terminal CT1 and an output terminal NOP.

Among them, the output stage circuit 110 includes transistors T1 to T5 and a capacitor C1. The first terminal of the transistor T1 is coupled to the low voltage VL, and the control terminal of the transistor T1 receives the light-emitting control signal EM[N]. The first terminal of the transistor T2 is coupled to the second terminal of the transistor T1, the second terminal of the transistor T2 is coupled to the control terminal CT1, and the control terminal of the transistor T2 receives the control signal S1[N-1] (i.e. , the second control signal). The first terminal of the transistor T3 is coupled to the second terminal of the transistor T1, and the control terminal of the transistor T3 is coupled to the control terminal CT1. The first terminal of the transistor T4 is coupled to the reference voltage VREF1, the second terminal of the transistor T4 is coupled to the second terminal of the transistor T3, and the control terminal of the transistor T4 receives the control signal S1[N-1]. The first terminal of the transistor T5 is coupled to the second terminal of the transistor T4, the second terminal of the transistor T5 is coupled to the output terminal NOP, and the control terminal of the transistor T5 receives the light-emitting control signal EM[N]. The capacitor C1 is coupled between the control terminal CT1 and the output terminal NOP.

Specifically, the output stage circuit 110 of this embodiment can generate the ramp signal SWEEP[N] at the output terminal NOP according to the node voltage Q[N] of the control terminal CT1 to the corresponding pixel circuit (not shown), Where N is a derivative.

The voltage stabilizing circuit 120 is coupled to the output terminal NOP. The voltage stabilizing circuit 120 has a control terminal CT2. The voltage stabilizing circuit 120 includes transistors T6 to T8 and a capacitor C2. The first terminal of the transistor T6 is coupled to the low voltage VL, the second terminal of the transistor T6 is coupled to the control terminal CT2, and the control terminal of the transistor T6 receives the control signal S1[N-2] (that is, the third control terminal signal). The first terminal of the transistor T7 is coupled to the high voltage VSH, the second terminal of the transistor T7 is coupled to the control terminal CT2, and the control terminal of the transistor T7 receives the light-emitting control signal EM[N]. The first terminal of the transistor T8 is coupled to the high voltage VSH, the second terminal of the transistor T8 is coupled to the output terminal NOP, and the control terminal of the transistor T8 is coupled to the control terminal CT2. The first terminal of the capacitor C2 is coupled to the control terminal CT2, and the second terminal of the capacitor C2 receives the clock signal CK.

Specifically, the voltage stabilizing circuit 120 of this embodiment can perform a voltage stabilizing action on the output terminal NOP according to the state of the clock signal CK (or the reverse clock signal XCK). An external clock generator (not shown) can provide a periodically changing clock signal CK or a reverse clock signal XCK to the ramp voltage generator 100 .

On the other hand, the voltage adjustment circuit 130 is coupled to the control terminal CT1 and the voltage stabilizing circuit 120 . The voltage adjustment circuit 130 has a detection terminal DT1. The voltage adjustment circuit 130 includes transistors T9 to T12 and a capacitor C3. The first terminal of the transistor T9 is coupled to the high voltage VSH, the second terminal of the transistor T9 is coupled to the detection terminal DT1, and the control terminal of the transistor T9 receives the control signal S1[N-4] (that is, the fourth control signal). The first terminal of the transistor T10 is coupled to the low voltage VL, the second terminal of the transistor T10 is coupled to the control terminal CT1, and the control terminal of the transistor T10 receives the control signal S1[N-2]. The first terminal of the transistor T11 is coupled to the high voltage VSH, the second terminal of the transistor T11 is coupled to the detection terminal DT1, and the control terminal of the transistor T11 receives the control signal S1[N-1]. The first terminal of the transistor T12 is coupled to the high voltage VSH, the second terminal of the transistor T12 is coupled to the detection terminal DT1, and the control terminal of the transistor T12 is coupled to the control terminal of the transistor T6 and receives the control signal S1[N -2]. Capacitor C3 is coupled between the detection terminal DT1 and the control terminal CT1.

Specifically, the voltage adjustment circuit 130 of this embodiment can adjust the node of the detection terminal DT1 according to the states of the control signal S1[N-1], the control signal S1[N-2] and the control signal S1[N-4]. The voltage K[N] and the node voltage Q[N] of the control terminal CT1.

The load variation detection circuit 140 is coupled to the detection terminal DT1. The load variation detection circuit 140 has a detection terminal DT2. The load variation detection circuit 140 includes transistors T13 to T15, a capacitor C4 and a current source IBIAS. The first terminal of the transistor T13 is coupled to the reference voltage VREF2, the second terminal of the transistor T13 is coupled to the detection terminal DT2, and the control terminal of the transistor T13 receives the control signal S1[N] (that is, the first control signal ). The first terminal of the transistor T14 is coupled to the output terminal NOP and receives the ramp signal SWEEP[N], the second terminal of the transistor T14 is coupled to the detection terminal DT2, and the control terminal of the transistor T14 is coupled to the transistor T9 The control terminal and receives the control signal S1[N-4]. The first terminal of the transistor T15 is coupled to the detection terminal DT2, and the control terminal of the transistor T15 receives the control signal S1[N-4]. The capacitor C4 is coupled between the detection terminal DT1 and the detection terminal DT2. The first terminal of the current source IBIAS is coupled to the second terminal of the transistor T15 , and the second terminal of the current source IBIAS is coupled to the low voltage VL.

Specifically, the load variation detection circuit 140 of this embodiment can detect the output load variation of the output terminal NOP through the detection path PT, and based on the output load variation and the control signal S1[N] and the control signal S1 [N-4] state to adjust the node voltage K[N] of the detection terminal DT1 and the node voltage T[N] of the detection terminal DT2.

Incidentally, in terms of the design of the transistors T1 - T15 , the transistors T1 - T15 in this embodiment may be P-type transistors, but the embodiment of the present invention is not limited to this. In addition, in this embodiment, the voltage level of the reference voltage VREF1 may be higher than the voltage level of the reference voltage VREF2.

In addition, in this embodiment, the control signal S1[N-2] and the control signal S1[N-1] differ by one delay unit (for example, half a clock cycle), and the control signal S1[N-1] The difference from the control signal S1[N] is one delay unit (for example, half a clock cycle). Among them, the control signal S1[N-1] is the control signal S1[N] of the previous stage, the control signal S1[N-2] is the control signal S1[N] of the previous stage, and the control signal S1[N-4] It is the control signal S1[N] of the first four levels.

FIG. 2 is an operation waveform diagram of the ramp voltage generator according to the embodiment of FIG. 1 of the present invention. Please refer to FIG. 1 and FIG. 2 at the same time. In this embodiment, one pixel period TFR of the ramp voltage generator 100 can be divided into a detection phase DP, a reset phase RP, a compensation phase CP, a voltage output phase VOP and a stabilization phase. Pressure phase SP. The ramp voltage generator 100 can continuously operate in the detection phase DP, the reset phase RP, the compensation phase CP, the voltage output phase VOP and the voltage stabilization phase SP. The detection phase DP, the reset phase RP, the compensation phase CP, the voltage output phase VOP and the voltage stabilization phase SP do not overlap with each other. The compensation phase CP may include sub-phase CP1 and sub-phase CP2.

For implementation details of the ramp voltage generator 100, please refer to FIG. 2 and FIG. 3A to FIG. 3F. FIG. 3A to FIG. 3F are equivalent circuit diagrams of the ramp voltage generator according to the embodiment of FIG. 1 of the present invention. It should be noted that, for convenience of illustration, the transistors that are disconnected in FIGS. 3A to 3F are indicated by a cross, while the transistors that are turned on are indicated by an uncrossed transistor.

Please refer to FIG. 2 and FIG. 3A at the same time. FIG. 3A is an equivalent circuit diagram when the ramp voltage generator 100 operates in the detection phase DP. Specifically, in the detection phase DP, the control signal S1[N-4] can be set to a low voltage level (equal to the gate low voltage VGL), and the clock signal CK, the control signal S1[N], and the control The signal S1[N-1], the control signal S1[N-2] and the light emission control signal EM[N] can be set to a high voltage level (equal to the gate high voltage VGH).

Specifically, in the detection phase DP, the load variation detection circuit 140 can detect the output load variation at the output terminal NOP via the detection path PT according to the pulled-down control signal S1[N-4]. The detection path PT in this embodiment may include a transistor T14, a transistor T15, and a current source IBIAS. In the embodiment of the present invention, the entire display panel can share the same current source IBIAS, and the current source IBIAS can discharge the load on the display panel during the detection phase DP to store its value in the capacitor C4.

For example, the load variation detection circuit 140 can detect the output load variation of the output terminal NOP through the detection path PT and according to the current source IBIAS, and provide variation through the conduction path of the transistor T14 according to the output load variation. The voltage △VRC reaches the detection terminal DT2, so that the node voltage T[N] of the detection terminal DT2 is adjusted to the voltage difference between the high voltage VSH and the variation voltage △VRC (that is, VSH-△VRC). Wherein, the above-mentioned variation voltage ΔVRC may be the voltage change amount of the output terminal NOP caused by the output load variation.

On the other hand, the voltage adjustment circuit 130 can provide the high voltage VSH to the detection terminal DT1 through the conduction path of the transistor T9 according to the pulled-down control signal S1[N-4], so that the node of the detection terminal DT1 The voltage K[N] is pulled up to the voltage level of the high voltage VSH. In other words, during the detection phase DP, the load variation detection circuit 140 can store the variation voltage ΔVRC in the capacitor C4.

Next, please refer to FIG. 2 and FIG. 3B simultaneously. FIG. 3B is an equivalent circuit diagram when the ramp voltage generator 100 operates in the reset phase RP. Specifically, in the reset phase RP, the control signal S1[N-2] can be set to a low voltage level (equal to the gate low voltage VGL), while the clock signal CK, the control signal S1[N], and the control The signal S1[N-1], the control signal S1[N-4] and the light emission control signal EM[N] can be set to a high voltage level (equal to the gate high voltage VGH).

Specifically, in the reset phase RP, the voltage adjustment circuit 130 can provide the low voltage VL to the control terminal CT1 through the conduction path of the transistor T10 according to the pulled-down control signal S1[N-2], so that the control The node voltage Q[N] of terminal CT1 is pulled down to the voltage level of low voltage VL.

Then, the voltage adjustment circuit 130 can provide the high voltage VSH to the detection terminal DT1 through the conduction path of the transistor T12 according to the pulled-down control signal S1[N-2], so that the node voltage K[ of the detection terminal DT1 N] is pulled up to the voltage level of the high voltage VSH.

On the other hand, the voltage stabilizing circuit 120 can provide the low voltage VL to the control terminal CT2 through the conduction path of the transistor T6 according to the pulled-down control signal S1[N-2], so that the node voltage P of the control terminal CT2 [N] is pulled down to the voltage level of the low voltage VL. In this case, the voltage stabilizing circuit 120 can turn on the transistor T8 according to the pulled-down node voltage P[N], and provide the high voltage VSH to the output terminal NOP through the conduction path of the transistor T8, so that the output stage circuit 110 generates a ramp signal SWEEP[N] that is pulled up to the voltage level of the high voltage VSH.

It is worth mentioning that since the detection terminal DT2 of the load variation detection circuit 140 is in a floating state at this time, the voltage level of the node voltage T[N] of the detection terminal DT2 can be maintained at the high voltage VSH and the variation. The voltage difference between voltage ΔVRC.

Next, please refer to FIG. 2 and FIG. 3C simultaneously. FIG. 3C is an equivalent circuit diagram when the ramp voltage generator 100 operates in the sub-stage CP1 of the compensation stage CP. Specifically, in the sub-phase CP1 of the compensation phase CP, the clock signal CK and the control signal S1[N-1] can be set to a low voltage level (equal to the gate low voltage VGL), and the control signal S1[N ], the control signal S1[N-2], the control signal S1[N-4] and the light-emitting control signal EM[N] can be set to a high voltage level (equal to the gate high voltage VGH).

Specifically, in the sub-phase CP1 of the compensation phase CP, the output stage circuit 110 can provide power through the conduction paths of the transistors T2, T3 and T4 according to the pulled-down control signal S1[N-1]. The reference voltage VREF1 is used to charge the control terminal CT1, so that the node voltage Q[N] of the control terminal CT1 is pulled down to the voltage difference between the reference voltage VREF1 and the critical voltage VTH3 of the transistor T3 (that is, VREF1 -|VTH3|).

Among them, the transistor T3 at this time can form a diode according to the connection method of the diode configuration (Diode Connection) through the conduction path of the transistor T2 to compensate the critical voltage VTH3, thereby improving the compensation accuracy. .

Then, the voltage adjustment circuit 130 can provide the high voltage VSH to the detection terminal DT1 through the conduction path of the transistor T11 according to the pulled-down control signal S1[N-1], so that the node voltage K[ of the detection terminal DT1 N] is maintained at the voltage level of the high voltage VSH.

On the other hand, since the clock signal CK transitions from a high voltage level to a low voltage level when the ramp voltage generator 100 operates in the sub-phase CP1 of the compensation phase CP, the voltage stabilizing circuit 120 can pass the capacitor. The coupling effect of C2 and according to the state of the clock signal CK, the voltage level of the node voltage P[N] of the control terminal CT2 is pulled down to the voltage between the low voltage VL and the voltage variation ΔVCK of the clock signal CK. difference (i.e., VL-ΔVCK). In this case, the voltage stabilizing circuit 120 can turn on the transistor T8 according to the pulled-down node voltage P[N], and provide the high voltage VSH to the output terminal NOP through the conduction path of the transistor T8, so that the output terminal NOP The ramp signal SWEEP[N] is maintained at the voltage level of the high voltage VSH.

It is worth mentioning that since the detection terminal DT2 of the load variation detection circuit 140 is in a floating state at this time, the voltage level of the node voltage T[N] of the detection terminal DT2 can still be maintained at the high voltage VSH and Variation voltage The voltage difference between △VRC.

Next, please refer to FIG. 2 and FIG. 3D simultaneously. FIG. 3D is an equivalent circuit diagram when the ramp voltage generator 100 operates in the sub-stage CP2 of the compensation stage CP. Specifically, in the sub-phase CP2 of the compensation phase CP, the control signal S1[N] can be set to a low voltage level (equal to the gate low voltage VGL), while the clock signal CK, the control signal S1[N-1 ], the control signal S1[N-2], the control signal S1[N-4] and the light-emitting control signal EM[N] can be set to a high voltage level (equal to the gate high voltage VGH).

Specifically, in the sub-stage CP2 of the compensation stage CP, the load variation detection circuit 140 can provide the reference voltage VREF2 to the detection terminal DT2 through the conduction path of the transistor T13 according to the pulled-down control signal S1[N]. , so that the node voltage T[N] of the detection terminal DT2 is adjusted to the voltage level of the reference voltage VREF2.

Then, the voltage adjustment circuit 130 can use the coupling effect of the capacitor C4, based on the output load variation of the output terminal NOP, and based on the node voltage T[N], the variation voltage ΔVRC stored in the capacitor C4, the capacitor C1, the capacitor C3 and the capacitor C4. The voltage division state between C4 is used to adjust the node voltage K[N] of the detection terminal DT1. Among them, the voltage level of the node voltage K[N] at this time can be expressed as the following formula (1): K[N]= (1)

In addition, the voltage adjustment circuit 130 can further utilize the coupling effect of the capacitor C3, based on the output load variation of the output terminal NOP, and based on the node voltage K[N], the variation voltage ΔVRC stored in the capacitor C4, and the relationship between the capacitor C3 and the capacitor C4. The node voltage Q[N] of the control terminal CT1 is adjusted by the voltage division state between them. Among them, the voltage level of the node voltage Q[N] at this time can be expressed as the following formula (2): Q[N]=VREF1-|VTH3|+ (2)

Among them, the above K[N] and Q[N] are the voltage values of the node voltages K[N] and Q[N] respectively; VSH is the voltage value of the high voltage VSH; VREF1 and VREF2 are the reference voltages VREF1 and VREF2 respectively. Voltage value; △VRC is the voltage value of the variation voltage △VRC; VTH3 is the voltage value of the critical voltage VTH3 of the transistor T3; C1, C3 and C4 are the capacitance values of the capacitors C1, C3 and C4 respectively.

According to the above description, it can be known that when the ramp voltage generator 100 operates in the sub-stage CP2 of the compensation stage CP, the voltage adjustment circuit 130 and the load variation detection circuit 140 can use the coupling effect of the capacitor C3 and the capacitor C4 to The variation voltage ΔVRC stored in the capacitor C4 is coupled to the control terminal CT1 and causes the transistor T3 to operate in the saturation region.

On the other hand, since the clock signal CK transitions from a low voltage level to a high voltage level when the ramp voltage generator 100 operates in the sub-phase CP2 of the compensation phase CP, the voltage stabilizing circuit 120 can pass the capacitor C2 The coupling effect and according to the state of the clock signal CK, the node voltage P[N] of the control terminal CT2 is readjusted back to the voltage level of the low voltage VL. In this case, the voltage stabilizing circuit 120 can turn on the transistor T8 according to the node voltage P[N], and provide the high voltage VSH to the output terminal NOP through the conduction path of the transistor T8, so that the ramp signal of the output terminal NOP SWEEP[N] is maintained at the voltage level of the high voltage VSH.

Next, please refer to FIG. 2 and FIG. 3E simultaneously. FIG. 3E is an equivalent circuit diagram when the ramp voltage generator 100 operates in the voltage output stage VOP. Specifically, in the voltage output stage VOP, the light-emitting control signal EM[N] can be set to a low voltage level (equal to the gate low voltage VGL), and the control signal S1[N], the control signal S1[N-1 ], the control signal S1[N-2], and the control signal S1[N-4] can be set to a high voltage level (equal to the gate high voltage VGH), and the clock signal CK can be periodically transitioned.

Specifically, in the voltage output stage VOP, the output stage circuit 110 can make the output terminal NOP pass the conduction path of the transistor T1, the transistor T3 and the transistor T5 according to the pulled-down light emission control signal EM[N]. Low voltage VL performs discharge operation. Furthermore, the output stage circuit 110 can fix the cross voltage between the second terminal of the transistor T3 and the control terminal (ie, the control terminal CT1) through the coupling of the capacitor C1, and at the same time compensate for the variation of the threshold voltage VTH3 of the transistor T3. . Moreover, the transistor T3 can operate in the saturation region according to the node voltage Q[N] and generate a fixed current, so that the output stage circuit 110 can generate an image driven based on pulse-width modulation (PWM). The ramp signal SWEEP[N] with the required fixed slope.

Then, the voltage adjustment circuit 130 can use the coupling effect of the capacitor C1 to base on the voltage change ΔVI when the ramp signal SWEEP[N] is discharging, and based on the node voltage Q[N] in the sub-stage CP2 of the compensation stage CP. status to adjust the node voltage Q[N] of the control terminal CT1. Among them, the voltage level of the node voltage Q[N] at this time can be expressed as the following formula (3): Q[N]=VREF1-|VTH3|+ -△VI (3)

In addition, the voltage adjustment circuit 130 can further utilize the coupling effect of the capacitor C3, based on the voltage change ΔVI when the ramp signal SWEEP[N] is discharging, and based on the node voltage K[N] during the sub-stage CP2 of the compensation stage CP. state to adjust the node voltage K[N] of the detection terminal DT1. Among them, the voltage level of the node voltage K[N] at this time can be expressed as the following formula (4): K[N]= -△VI (4)

Then, the load variation detection circuit 140 can use the coupling effect of the capacitor C4, based on the voltage change ΔVI when the ramp signal SWEEP[N] is discharged, and based on the node voltage T[N] in the sub-stage CP2 of the compensation stage CP. In this state, the voltage level of the node voltage T[N] of the detection terminal DT2 is adjusted to the voltage difference between the reference voltage VREF2 and the voltage variation ΔVI (that is, VREF2-ΔVI).

According to the above description, it can be known that when the ramp voltage generator 100 operates in the voltage output stage VOP, the voltage adjustment circuit 130 can adjust according to the state of the output load variation (ie, variation voltage ΔVRC) of the output terminal NOP The voltage of the control terminal of transistor T3 (ie, control terminal CT1). In this way, the transistor T3 of the output stage circuit 110 can operate in the saturation region according to the node voltage Q[N], and can further compensate for the variation of the output load, thereby achieving the ability to accurately control the gray scale of the pixel.

On the other hand, the voltage stabilizing circuit 120 can provide the high voltage VSH to the control terminal CT2 through the conduction path of the transistor T7 according to the pulled-down light emission control signal EM[N], so that the node voltage P[ of the control terminal CT2 N] is pulled up to the voltage level of the high voltage VSH. In this case, the voltage stabilizing circuit 120 can turn off the transistor T8 according to the pulled-up node voltage P[N].

Next, please refer to FIG. 2 and FIG. 3F simultaneously. FIG. 3F is an equivalent circuit diagram when the ramp voltage generator 100 operates in the voltage stabilization stage SP. Specifically, in the voltage stabilization phase SP, the control signal S1[N], the control signal S1[N-1], the control signal S1[N-2], the control signal S1[N-4] and the light-emitting control signal EM[ N] can be set to a high voltage level (equal to the gate high voltage VGH), and the clock signal CK can be periodically changed.

Specifically, during the voltage stabilization phase SP, the voltage stabilization circuit 120 may couple the clock signal CK to the node voltage P[N] through the capacitor C2 and periodically turn on the transistor T8. In this case, the voltage stabilizing circuit 120 can provide the high voltage VSH to the output terminal NOP through the conduction path of the transistor T8 to stabilize the voltage of the output terminal NOP.

On the other hand, regarding the voltage states of the node voltages Q[N], K[N] and T[N] in the ramp voltage generator 100 of FIG. 3F , reference can be made to the voltage states of the ramp voltage generator 100 shown in FIG. 3D . The relevant descriptions of the voltage states of node voltages Q[N], K[N] and T[N] are by analogy, so they will not be described again.

FIG. 4 is a flowchart of an operating method of a ramp voltage generator according to an embodiment of the present invention. Please refer to FIG. 1 and FIG. 4 at the same time. In step S410, the ramp voltage generator 100 can provide an output stage circuit 110 having a control terminal CT1 and an output terminal NOP, and make the output stage circuit 110 depend on the node voltage Q of the control terminal CT1. [N] to generate a ramp signal SWEEP[N] at the output terminal NOP. In step S420, the ramp voltage generator 100 may provide the voltage stabilizing circuit 120 with the control terminal CT2, and enable the voltage stabilizing circuit 120 to regulate the voltage of the output terminal NOP according to the clock signal CK.

In step S430, the ramp voltage generator 100 may provide the voltage adjustment circuit 130 with the detection terminal DT1, and enable the voltage adjustment circuit 130 to operate according to the control signal S1[N-1], the control signal S1[N-2] and the control signal S1[N-1]. The signal S1[N-4] is used to adjust the node voltage K[N] of the detection terminal DT1 and the node voltage Q[N] of the control terminal CT1. In step S440, the ramp voltage generator 100 may provide the load variation detection circuit 140 with the detection terminal DT2, and enable the load variation detection circuit 140 to detect the output load variation at the output terminal NOP through the detection path PT, And based on the output load variation and the control signal S1[N] and the control signal S1[N-4], the node voltage K[N] of the detection terminal DT1 and the node voltage T[N] of the detection terminal DT2 are adjusted.

The implementation details of each step in Figure 4 have been described in detail in the foregoing embodiments and implementations, and will not be described again here.

In summary, the ramp voltage generator and its operating method according to embodiments of the present invention can effectively detect and compensate for the load variation at the output end and the critical voltage variation of the transistor, and prevent the output waveform of the ramp signal from being affected by the variation. , thereby increasing the accuracy of grayscale control of pixel circuits controlled by pulse width modulation.

100: Ramp voltage generator 110: Output stage circuit 120: Voltage stabilizing circuit 130: Voltage adjustment circuit 140: Load variation detection circuit C1～C4: capacitor CT1, CT2: control terminal CK: clock signal CP: Compensation stage CP1, CP2: sub-stages DT1, DT2: Detection terminal DP: Detection phase EM[N]: Luminous control signal IBIAS: current source K[N], P[N], Q[N], T[N]: node voltage NOP: output terminal PT: Detection path RP: reset phase S1[N], S1[N-1], S1[N-2], S1[N-4]: control signal SWEEP[N]: ramp signal SP: Stabilization stage T1～T15: transistor TFR: pixel period VREF1, VREF2: reference voltage VL: low voltage VSH: high voltage VOP: voltage output stage XCK: reverse clock signal

FIG. 1 is a schematic diagram of a ramp voltage generator according to an embodiment of the present invention. FIG. 2 is an operation waveform diagram of the ramp voltage generator according to the embodiment of FIG. 1 of the present invention. 3A to 3F are equivalent circuit diagrams of the ramp voltage generator according to the embodiment of FIG. 1 of the present invention. FIG. 4 is a flowchart of an operating method of a ramp voltage generator according to an embodiment of the present invention.

100: Ramp voltage generator

110: Output stage circuit

120: Voltage stabilizing circuit

130: Voltage adjustment circuit

140: Load variation detection circuit

C1~C4: capacitor

CT1, CT2: control terminal

CK: clock signal

DT1, DT2: Detection terminal

EM[N]: Luminous control signal

IBIAS: current source

K[N], P[N], Q[N], T[N]: node voltage

NOP: output terminal

PT: Detection path

S1[N], S1[N-1], S1[N-2], S1[N-4]: control signal

SWEEP[N]: ramp signal

T1~T15: transistor

VREF1, VREF2: reference voltage

VL: low voltage

VSH: high voltage

Claims (18)

A ramp voltage generator including: An output stage circuit has a first control terminal and an output terminal, and generates a ramp signal at the output terminal according to the node voltage of the first control terminal; A voltage stabilizing circuit has a second control terminal, the voltage stabilizing circuit is coupled to the output terminal, and regulates the voltage of the output terminal according to a clock signal; A voltage adjustment circuit has a first detection terminal, the voltage adjustment circuit is coupled to the first control terminal and the voltage stabilizing circuit, and is based on a second control signal, a third control signal and a fourth control signal To adjust the node voltage of the first detection terminal and the first control terminal; and A load variation detection circuit has a second detection terminal, the load variation detection circuit is coupled to the first detection terminal and the output terminal, and is used to detect a detection event on the output terminal through a detection path. The output load varies, and the node voltages of the first detection terminal and the second detection terminal are adjusted based on the output load variation and according to a first control signal and the fourth control signal. The ramp voltage generator of claim 1, wherein in a detection stage, the load variation detection circuit detects the output load variation at the output terminal based on the fourth control signal being pulled low, and A variation voltage is provided according to the variation of the output load to adjust the node voltage of the second detection terminal. The ramp voltage generator as claimed in claim 1, wherein in a reset phase, the voltage adjustment circuit provides a low voltage according to the third control signal being pulled down to pull down the node voltage of the first control terminal. , and the voltage stabilizing circuit provides the low voltage according to the pulled-down third control signal to pull down the node voltage of the second control terminal. The ramp voltage generator of claim 1, wherein in a first sub-stage of a compensation stage, the output stage circuit provides a first reference voltage to pull down based on the second control signal that is pulled down. The node voltage of the first control terminal. The ramp voltage generator of claim 4, wherein in a second sub-stage of the compensation stage, the load variation detection circuit provides a second reference voltage to The second detection terminal, and the voltage adjustment circuit adjusts the node voltage of the first detection terminal and the first control terminal based on the output load variation and according to the node voltage of the second detection terminal. The ramp voltage generator of claim 1, wherein in a voltage output stage, the output stage circuit generates a pulled-down node voltage based on a pulled-down node voltage of the first control terminal and a pulled-down light-emitting control signal. The ramp signal is low. The ramp voltage generator of claim 1, wherein in a voltage stabilization stage, the voltage stabilizing circuit provides a high voltage according to the clock signal, so that the output stage circuit generates the ramp signal that is pulled up. . The ramp voltage generator of claim 1, wherein the output stage circuit includes: a first transistor, the first end of which is coupled to a low voltage, and the control end of which receives a light-emitting control signal; a second transistor, the first terminal of which is coupled to the second terminal of the first transistor, the second terminal of which is coupled to the first control terminal, and the control terminal of which receives the second control signal; a third transistor, the first terminal of which is coupled to the second terminal of the first transistor, and the control terminal of which is coupled to the first control terminal; a fourth transistor with a first terminal coupled to a first reference voltage, a second terminal coupled to the second terminal of the third transistor, and a control terminal receiving the second control signal; a fifth transistor, the first terminal of which is coupled to the second terminal of the fourth transistor, the second terminal of which is coupled to the output terminal, and the control terminal of which receives the light-emitting control signal; and A first capacitor is coupled between the first control terminal and the output terminal. The ramp voltage generator of claim 8, wherein the voltage stabilizing circuit includes: a sixth transistor with a first terminal coupled to the low voltage, a second terminal coupled to the second control terminal, and a control terminal receiving the third control signal; A seventh transistor, its first terminal is coupled to a high voltage, its second terminal is coupled to the second control terminal, and its control terminal receives the light-emitting control signal; An eighth transistor has a first terminal coupled to the high voltage, a second terminal coupled to the output terminal, and a control terminal coupled to the second control terminal; and A second capacitor has a first end coupled to the second control end and a second end receiving the clock signal. The ramp voltage generator of claim 9, wherein the voltage adjustment circuit includes: A ninth transistor, its first terminal is coupled to the high voltage, its second terminal is coupled to the first detection terminal, and its control terminal receives the fourth control signal; a tenth transistor with a first terminal coupled to the low voltage, a second terminal coupled to the first control terminal, and a control terminal receiving the third control signal; An eleventh transistor, its first terminal is coupled to the high voltage, its second terminal is coupled to the first detection terminal, and its control terminal receives the second control signal; a twelfth transistor with a first terminal coupled to the high voltage, a second terminal coupled to the first detection terminal, and a control terminal coupled to the control terminal of the sixth transistor; and A third capacitor is coupled between the first detection terminal and the first control terminal. The ramp voltage generator of claim 10, wherein the load variation detection circuit includes: A thirteenth transistor, its first terminal is coupled to a second reference voltage, its second terminal is coupled to the second detection terminal, and its control terminal receives the first control signal; A fourteenth transistor, its first terminal is coupled to the output terminal, its second terminal is coupled to the second detection terminal, and its control terminal is coupled to the control terminal of the ninth transistor; a fifteenth transistor, the first terminal of which is coupled to the second detection terminal, and the control terminal of which receives the fourth control signal; a current source with a first terminal coupled to the second terminal of the fifteenth transistor and a second terminal coupled to the low voltage; and A fourth capacitor is coupled between the first detection terminal and the second detection terminal. A method of operating a ramp voltage generator, including: Provide an output stage circuit having a first control terminal and an output terminal, and enable the output stage circuit to generate a ramp signal at the output terminal according to the node voltage of the first control terminal; Provide a voltage stabilizing circuit with a second control terminal, and enable the voltage stabilizing circuit to regulate the voltage of the output terminal according to a clock signal; Provide a voltage adjustment circuit with a first detection terminal, and enable the voltage adjustment circuit to adjust the first detection terminal and the first control signal according to a second control signal, a third control signal and a fourth control signal the node voltage at the terminal; and Provide a load variation detection circuit with a second detection terminal, and enable the load variation detection circuit to detect an output load variation on the output terminal through a detection path, and based on the output load variation and according to a first A control signal and the fourth control signal are used to adjust the node voltages of the first detection terminal and the second detection terminal. The operation method as described in request item 12 further includes: In a detection stage, the load variation detection circuit detects the output load variation at the output terminal according to the fourth control signal that is pulled low, and provides a variation voltage according to the output load variation to adjust the output load variation. The node voltage of the second detection terminal. The operation method as described in request item 12 further includes: In a reset phase, the voltage adjustment circuit is caused to provide a low voltage according to the third control signal that is pulled down to pull down the node voltage of the first control terminal; and The voltage stabilizing circuit is caused to provide the low voltage according to the pulled-down third control signal to pull down the node voltage of the second control terminal. The operation method as described in request item 12 further includes: In a first sub-stage of a compensation stage, the output stage circuit is caused to provide a first reference voltage according to the pulled-down second control signal to pull down the node voltage of the first control terminal. The operation method as described in request item 15 further includes: In a second sub-stage of the compensation stage, the load variation detection circuit is caused to provide a second reference voltage to the second detection terminal according to the first control signal that is pulled down; and The voltage adjustment circuit is configured to adjust the node voltage of the first detection terminal and the first control terminal based on the output load variation and the node voltage of the second detection terminal. The operation method as described in request item 12 further includes: In a voltage output stage, the output stage circuit is caused to generate the pulled-down ramp signal according to the pulled-down node voltage of the first control terminal and a pulled-down light-emitting control signal. The operation method as described in request item 12 further includes: In a voltage stabilizing stage, the voltage stabilizing circuit is caused to provide a high voltage according to the clock signal, so that the output stage circuit generates the ramp signal that is pulled up.

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