CN113077754B - Pixel drive circuit - Google Patents

Abstract

The invention provides a pixel driving circuit, which comprises a light-emitting unit, twelve switches and three capacitors. The driving current of the light emitting unit only flows through one of the switches, thereby saving power consumption. In addition, the pixel driving circuit can compensate the critical voltage and the operating voltage, so that the light-emitting unit can provide consistent brightness.

Description

Pixel drive circuit

technical field

The present disclosure relates to pixel driving circuits of light emitting diodes.

Background technique

At present, light-emitting diodes have been widely used in various types of displays. The brightness of the light-emitting diode when it emits light is related to the size of its driving current, and the size of its driving current is controlled by the driving transistor. However, due to process variation, the threshold voltage (Vth) of the driving transistors of each pixel in the display is not the same, so that the light-emitting diodes in different pixels have different driving currents. The brightness of each light-emitting diode is different, which in turn causes the problem of uneven brightness when the display displays a picture. In addition, the driving current is shown to be provided by the operating voltage, and the operating voltage is likely to have a voltage drop due to the line resistance in the transmission path, so that the operating voltage of each pixel is different, which causes an error in the driving current.

Therefore, how to compensate the threshold voltage of the driving transistor of the display pixel and also compensate the operating voltage is the goal of those skilled in the art.

SUMMARY OF THE INVENTION

An embodiment of the present invention provides a pixel driving circuit, which includes the following elements. The light-emitting unit has a first end and a second end, and the first end of the light-emitting unit is connected to the first operating voltage. The first switch has a first terminal, a second terminal and a control terminal, the first terminal of the first switch is connected to the second terminal of the light emitting unit, and the second terminal of the first switch is connected to the second operating voltage. The second switch has a first end, a second end and a control end, the first end of the second switch is connected to the control end of the first switch, and the second end of the second switch is connected to the second end and the second end of the first switch The operating voltage, the control terminal of the second switch is connected to the first control signal. The first capacitor has a first end and a second end, and the first end of the first capacitor is connected to the control end of the first switch and the first end of the second switch. The second capacitor has a first terminal and a second terminal, the first terminal of the second capacitor is connected to the second terminal of the first capacitor, and the second terminal of the second capacitor is connected to a reference voltage. The third switch has a first end, a second end and a control end, the first end of the third switch is connected to the control end of the first switch, the first end of the second switch and the first end of the first capacitor, the third switch The control terminal is connected to the second control signal. The fourth switch has a first terminal, a second terminal and a control terminal, the first terminal of the fourth switch is connected to the control terminal of the fourth switch, and the second terminal of the fourth switch is connected to the reference voltage. The fifth switch has a first end, a second end and a control end, the first end of the fifth switch is connected to the second end of the first switch and the second end of the second switch, and the second end of the fifth switch is connected to the second end of the fifth switch. The second end of a capacitor and the first end of the second capacitor. The sixth switch has a first terminal, a second terminal and a control terminal. The first terminal of the sixth switch is connected to the second terminal of the fifth switch, the second terminal of the first capacitor and the first terminal of the second capacitor. The second terminal of the switch is connected to the diode voltage, and the control terminal of the sixth switch is connected to the third control signal. The seventh switch has a first end, a second end and a control end, the first end of the seventh switch is connected to the control end of the fifth switch, the second end of the seventh switch is connected to the diode voltage, and the control end of the seventh switch is connected to the third control signal. The eighth switch has a first end, a second end and a control end, and the first end of the eighth switch is connected to the control end of the fifth switch and the first end of the seventh switch. The third capacitor has a first terminal and a second terminal, the first terminal of the third capacitor is connected to the second terminal of the eighth switch, and the second terminal of the third capacitor is connected to the reference voltage. The ninth switch has a first end, a second end and a control end, the first end of the ninth switch is connected to the first end of the third capacitor and the second end of the eighth switch, and the second end of the ninth switch is connected to the first end of the ninth switch. A control signal, the control terminal of the ninth switch is connected to the first control signal. The tenth switch has a first terminal, a second terminal and a control terminal. The first terminal of the tenth switch is connected to the second terminal of the eighth switch, the first terminal of the third capacitor and the first terminal of the ninth switch. The second end of the switch is connected to the control end of the eighth switch, and the control end of the tenth switch is connected to the first control signal. The eleventh switch has a first end, a second end and a control end. The first end of the eleventh switch is connected to the control end of the eighth switch and the second end of the tenth switch, and the second end of the eleventh switch is connected to To the fourth control signal, the control terminal of the eleventh switch is connected to the third control signal. The twelfth switch has a first end, a second end and a control end, the first end of the twelfth switch is connected to the control end of the eighth switch, the second end of the tenth switch and the first end of the eleventh switch, The second terminal of the twelfth switch is connected to a data voltage, and the control terminal of the twelfth switch is connected to the second control signal.

In some embodiments, the pixel driving circuit operates in the first period, the second period, the third period and the fourth period in sequence. During the first period, the second switch, the fourth switch, the sixth switch, the seventh switch, the ninth switch and the tenth switch are in a conducting state, and the first switch, the third switch, the fifth switch and the eighth switch , the eleventh switch and the twelfth switch are in an off state. During the second period, the third switch, the fourth switch, the sixth switch, the seventh switch, the eighth switch, and the twelfth switch are in an on state, and the first switch, the second switch, the fifth switch, and the ninth switch , the tenth switch and the eleventh switch are in the off state. In the first sub-period of the third period, the eleventh switch is in an on state, and the first to third switches, the fifth to tenth switches, and the twelfth switch are in an off state. In the second sub-period of the third period, the first switch, the fifth switch, the eighth switch and the eleventh switch are in the ON state, the second switch, the third switch, the sixth switch, the seventh switch, the first switch The ninth switch, the tenth switch and the twelfth switch are in the off state. During the fourth period, the sixth switch and the seventh switch are in an on state, and the first switch, the second switch, the third switch, the fifth switch, and the eighth switch to the twelfth switch are in an off state.

In some embodiments, the eighth switch and the eleventh switch are P-type transistors, and the first to seventh switches, the ninth switch, the tenth switch and the twelfth switch are N-type transistors.

In some embodiments, the threshold voltage of the first switch is matched to the threshold voltage of the fourth switch.

In some embodiments, during the first period, the first control signal and the third control signal are at a first high level, the second control signal is at a first low level, and the fourth control signal is at a second high level. During the second period, the first control signal is at a first low level, the second control signal and the third control signal are at a first high level, and the fourth control signal is at a second high level. During the third period, the first control signal, the second control signal and the third control signal are at the first low level, and the fourth control signal gradually decreases from the second high level to the second low level. During the fourth period, the first control signal and the second control signal are at a first low level, the third control signal is at a first high level, and the fourth control signal is at a second high level.

In some embodiments, the first operating voltage is greater than the second operating voltage.

In some embodiments, the above-mentioned light-emitting units are light-emitting diodes.

In some embodiments, the size of the above-mentioned light emitting diodes is sub-millimeter.

In some embodiments, the above-mentioned pixel driving circuit is disposed in the display panel.

In some embodiments, the above-mentioned pixel driving circuit is disposed in a backlight module.

In the above-mentioned pixel driving circuit, the threshold voltage and the operating voltage can be compensated, and the technical effect of saving power consumption is achieved.

Description of drawings

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following specific embodiments are given and described in detail as follows in conjunction with the accompanying drawings.

FIG. 1 is a circuit structure diagram illustrating a pixel driving circuit according to an embodiment.

FIG. 2 is a timing diagram illustrating various control signals in a pixel driving circuit according to an embodiment.

FIG. 3 is a schematic diagram illustrating switching of a pixel driving circuit in a first period according to an embodiment.

FIG. 4 is a schematic diagram illustrating switching of a pixel driving circuit in a second period according to an embodiment.

FIG. 5 is a schematic switch diagram illustrating a pixel driving circuit in a first sub-period in a third period according to an embodiment.

FIG. 6 is a schematic diagram illustrating the switching of the pixel driving circuit in the second sub-period in the third period according to an embodiment.

FIG. 7 is a schematic diagram illustrating switching of a pixel driving circuit in a fourth period according to an embodiment.

Description of reference numbers:

100: Pixel drive circuit

110: Lighting unit

C1: first capacitor

C2: second capacitor

C3: the third capacitor

T1～T12: switch

I _LED : Current

110-1,C1-1,C2-1,C3-1,T1-1,T2-1,T3-1,T4-1,T5-1,T6-1,T7-1,T8-1,T9- 1, T10-1, T11-1, T12-1: the first end

110-2,C1-2,C2-2,C3-2,T1-2,T2-2,T3-2,T4-2,T5-2,T6-2,T7-2,T8-2,T9- 2, T10-2, T11-2, T12-2: the second end

T1-3, T2-3, T3-3, T4-3, T5-3, T6-3, T7-3, T8-3, T9-3, T10-3, T11-3, T12-3: Control terminal

A,B,C,D,E: Nodes

VDD, VSS: operating voltage

S1,S2,EM,V _sweep : Control signal

V _DATA : data voltage

V _LED : Diode voltage

V _ref : reference voltage

210: first period

220: Second period

230: third period

230-1: First sub-period

230-2: Second sub-period

240: Fourth period

V _GH , V _{sweep_H} : high level

V _GL ,V _{sweep_L} : low level

Detailed ways

Regarding the "first", "second" and the like used herein, it does not mean a particular order or order, but only for distinguishing elements or operations described in the same technical terms.

FIG. 1 is a circuit structure diagram illustrating a pixel driving circuit according to an embodiment. The pixel driving circuit 100 can be disposed on a backlight module of a display device to provide a backlight source, or disposed in a display panel as a pixel, which is not limited in the present disclosure. The pixel driving circuit 100 includes a light emitting unit 110, switches T1-T12, a first capacitor C1, a second capacitor C2 and a third capacitor C3. The light-emitting unit 110 is, for example, a light-emitting diode, and the size of the light-emitting diode may be sub-millimeter or other suitable sizes, which is not limited in the present disclosure.

The light-emitting unit 110 has a first terminal 110-1 and a second terminal 110-2, and the first terminal 110-1 of the light-emitting unit 110 is connected to the operating voltage VDD. The switch T1 has a first terminal T1-1, a second terminal T1-2 and a control terminal T1-3, the first terminal T1-1 of the switch T1 is connected to the second terminal 110-2 of the light-emitting unit 110, and the second terminal T1-1 of the switch T1 The terminal T1-2 is connected to the operation voltage VSS, where the operation voltage VSS is smaller than the operation voltage VSS. The switch T2 has a first terminal T2-1, a second terminal T2-2 and a control terminal T2-3, the first terminal T2-1 of the switch T2 is connected to the control terminal T1-3 of the switch T1, and the second terminal T2 of the switch T2 -2 is connected to the second terminal T1-2 of the switch T1 and the operating voltage VSS, and the control terminal T2-3 of the switch T2 is connected to the control signal S1. The first capacitor C1 has a first terminal C1-1 and a second terminal C1-2, and the first terminal C1-1 of the first capacitor C1 is connected to the control terminal T1-3 of the switch T1 and the first terminal T2-1 of the switch T2 . The second capacitor C2 has a first terminal C2-1 and a second terminal C2-2. The first terminal C2-1 of the second capacitor C2 is connected to the second terminal C1-2 of the first capacitor C1. The two terminals C2-2 are connected to the reference voltage V _ref . The switch T3 has a first terminal T3-1, a second terminal T3-2 and a control terminal T3-3. The first terminal T3-1 of the switch T3 is connected to the control terminal T1-3 of the switch T1 and the first terminal T2 of the switch T2 -1 and the first terminal C1-1 of the first capacitor C1, and the control terminal T3-3 of the switch T3 are connected to the control signal S2. The switch T4 has a first terminal T4-1, a second terminal T4-2 and a control terminal T4-3, the first terminal T4-1 of the switch T4 is connected to the control terminal T4-3 of the switch T4, and the second terminal T4 of the switch T4 -2 is connected to the reference voltage V _ref . The switch T5 has a first terminal T5-1, a second terminal T5-2 and a control terminal T5-3, the first terminal T5-1 of the switch T5 is connected to the second terminal T1-2 of the switch T1 and the second terminal of the switch T2 T2-2, the second terminal T5-2 of the switch T5 is connected to the second terminal C1-2 of the first capacitor C1 and the first terminal C2-1 of the second capacitor C2. The switch T6 has a first terminal T6-1, a second terminal T6-2 and a control terminal T6-3. The first terminal T6-1 of the switch T6 is connected to the second terminal T5-2 of the switch T5 and the first terminal T5-2 of the first capacitor C1. The two terminals C1-2 and the first terminal C2-1 of the second capacitor C2, the second terminal T6-2 of the switch T6 is connected to the diode voltage V _LED , and the control terminal T6-3 of the switch T6 is connected to the control signal EM.

The switch T7 has a first terminal T7-1, a second terminal T7-2 and a control terminal T7-3, the first terminal T7-1 of the switch T7 is connected to the control terminal T5-3 of the switch T5, and the second terminal T7 of the switch T7 -2 is connected to the diode voltage VLED and the control terminal _T7-3 of the switch T7 is connected to the control signal EM. The switch T8 has a first terminal T8-1, a second terminal T8-2 and a control terminal T8-3, the first terminal T8-1 of the switch T8 is connected to the control terminal T5-3 of the switch T5 and the first terminal T7 of the switch T7 -1. The third capacitor C3 has a first terminal C3-1 and a second terminal C3-2, the first terminal C3-1 of the third capacitor C3 is connected to the second terminal T8-2 of the switch T8, and the second terminal of the third capacitor C3 C3-2 is connected to the reference voltage _Vref . The switch T9 has a first terminal T9-1, a second terminal T9-2 and a control terminal T9-3. The first terminal T9-1 of the switch T9 is connected to the first terminal C3-1 of the third capacitor C3 and the first terminal C3-1 of the switch T8. Two terminals T8-2, the second terminal T9-2 of the switch T9 is connected to the control signal S1, and the control terminal T9-3 of the switch T9 is connected to the control signal S1. The switch T10 has a first terminal T10-1, a second terminal T10-2 and a control terminal T10-3. The first terminal T10-1 of the switch T10 is connected to the second terminal T8-2 of the switch T8 and the third terminal T10-2 of the third capacitor C3. One terminal C3-1 and the first terminal T9-1 of the switch T9, the second terminal T10-2 of the switch T10 is connected to the control terminal T8-3 of the switch T8, and the control terminal T10-3 of the switch T10 is connected to the control signal S1. The switch T11 has a first terminal T11-1, a second terminal T11-2 and a control terminal T11-3, and the first terminal T11-1 of the switch T11 is connected to the control terminal T8-3 of the switch T8 and the second terminal T10 of the switch T10 -2, the second terminal T11-2 of the switch T11 is connected to the control signal V _sweep , and the control terminal T11-3 of the switch T11 is connected to the control signal EM. The switch T12 has a first terminal T12-1, a second terminal T12-2 and a control terminal T12-3. The first terminal T12-1 of the switch T12 is connected to the control terminal T8-3 of the switch T8 and the second terminal T10 of the switch T10. -2 and the first terminal T11-1 of the switch T11, the second terminal T12-2 of the switch T12 is connected to the data voltage V _DATA , and the control terminal T12-3 of the switch T12 is connected to the control signal S2.

In this embodiment, the switches T1-T12 are, for example, thin film transistors, wherein the switches T8 and T11 are P-type transistors, and the switches T1-T7, T9, T10, and T12 are N-type transistors. In addition, the threshold voltage of the switch T1 is matched to the threshold voltage of the switch T4, and the technical effect of the threshold voltage matching will be described in detail below.

FIG. 2 is a timing diagram illustrating various control signals in a pixel driving circuit according to an embodiment. Referring to FIG. 2 , the pixel driving circuit operates in the first period 210 , the second period 220 , the third period 230 and the fourth period 240 in sequence, and returns to the first period 210 after the fourth period 240 ends.

FIG. 3 is a schematic diagram illustrating switching of a pixel driving circuit in a first period according to an embodiment. Please refer to FIG. 2 and FIG. 3 , the first period 210 is used to reset the pixel driving circuit 100 . During the first period 210 , the control signal S1 and the control signal EM are at a high level V _GH , the control signal S2 is at a low level V _GL , and the control signal V _sweep is at a high level V _{sweep_H} , wherein the high level V _GH may be the same Or different from the high level V _{sweep_H} , the disclosure is not limited thereto. Therefore, the switches T2, T4, T6, T7, T9, and T10 are turned on, and the switches T1, T3, T5, T8, T11, and T12 are turned off. During the first period 210, the potential of the node A is the same as the reference voltage VSS. The potentials of the node B and the node C are the same as the diode voltage V _LED . The potentials of the node D and the node E are the same as the high level V _GH .

FIG. 4 is a schematic diagram illustrating switching of a pixel driving circuit in a second period according to an embodiment. Please refer to FIG. 2 and FIG. 4 , the second period 220 is used for voltage compensation. During the second period 220 , the control signal S1 is at the low level V _GL , the control signal S2 and the control signal EM are at the high level V _GH , and the control signal V _sweep is at the high level V _{sweep_H} . Therefore, the switches T3, T4, T6, T7, T8, and T12 are turned on, and the switches T1, T2, T5, T9, T10, and T11 are turned off. During this period, the potential of node A is the same as V _ref +V _{TH_T4} , where V _{TH_T4} is the threshold voltage of switch T4 . The potentials of the nodes B and C are the same as the diode voltage V _LED . The potential of the node D is the same as the data voltage V _DATA . The potential of the node E will increase due to the charging of the third capacitor C3 until the potential of the node E is equal to V _DATA +|V _{TH_T8} | and the switch T8 is switched to the off state, where V _{TH_T8} is the threshold voltage of the switch T8.

FIG. 5 is a schematic switch diagram illustrating a pixel driving circuit in a first sub-period in a third period according to an embodiment. Referring to FIGS. 2 and 5 , the third period 230 is divided into a first subperiod 230-1 and a second subperiod 230-2. In the first subperiod 230-1, the light emitting unit 110 is turned off, and in the second subperiod 230-1 230-2 The light-emitting unit 110 is turned on and emits light. The lengths of the first sub-period 230-1 and the second sub-period 230-2 are determined by the data voltage V _DATA . In other words, in this embodiment, the light-emitting unit 110 is driven in a pulse width modulation (PWM) manner, thereby determining the brightness of the pixels. Specifically, in the third period 230 , the control signal S1 , the control signal S2 and the control signal EM are at the low level V _GL , and the control signal V _sweep gradually decreases from the high level V _{sweep_H} to the low level V _{sweep_L} .

In the first sub-period 230-1, the switch T11 is in the ON state, and the switches T1-T3, T5-T10, and T12 are in the OFF state. The potential of node A remains unchanged at V _ref +V _{TH_T4} . The potentials of the nodes B and C are the same as the diode voltage V _LED . The potential of the node D is the same as the control signal V _sweep . The potential of node E is the same as V _DATA +|V _{TH_T8} |. The potential of the node D gradually decreases until the switch T8 is switched to the ON state when the following equation 1 is established, and then the second sub-period 230-2 is entered.

[Mathematical formula 1]

Where _VE represents the potential of node E, and V _D represents the potential of node D. Since the threshold voltage of the switch T8 is self-compensated, the establishment condition of the above equation 1 is not affected by the threshold voltage of the switch T8. When the data voltage V _DATA is larger, the earlier the mathematical formula 1 is established, the earlier the second sub-period 230 - 2 is entered.

FIG. 6 is a schematic diagram illustrating the switching of the pixel driving circuit in the second sub-period in the third period according to an embodiment. Referring to FIG. 2 and FIG. 6 , in the second sub-period 230 - 2 , the switches T1 , T5 , T8 , and T11 are in the on state, and the switches T2 , T3 , T6 , T7 , T9 , T10 , and T12 are in the off state. During this period, the potentials of node E and node C are the same as V _DATA +|V _{TH_T8} |, which turns on switch T5, which makes the potential of node B equal to the operating voltage VSS. The potential of node B changes from VLED to VSS in the first sub-period 230-1 by VSS- _VLED , so the potential of node A changes from _Vref + _{VTH_T4} to _Vref + _{VTH_T4} + _VSS- V _LED , this potential turns on the switch T1 to generate a current I _LED , the current I _LED flows through the light-emitting unit 110 and the switch T1 , and the magnitude of the current I _LED is shown in the following equation 2.

[Mathematical formula 2]

Where K is a constant, VA is the potential of node _A , and V _{TH_T1} is the threshold voltage of switch T1. It is worth noting that since the threshold voltage of the switch T1 matches the threshold voltage of the switch T4, the two threshold voltages V _{TH_T4} and V _{TH_T1 cancel} each other in Equation 2, and the magnitude of the current I _LED is not affected by the threshold voltage V _{TH_T1} Impact. In addition, since the operation voltage VSS is compensated in Equation 2, the magnitude of the current I _LED is also not affected by the operation voltage VSS. In the prior art, the driving current passes through more than two switches. When the current is large, a voltage drop will occur, so that the switches may enter the linear region. Increasing the cross-voltage between the operating voltages VDD and VSS can solve this problem, but it increases the power consumption. In contrast, the current I _LED only flows through one switch T1, thus having the technical effect of reducing power consumption.

FIG. 7 is a schematic diagram illustrating switching of a pixel driving circuit in a fourth period according to an embodiment. Referring to FIG. 2 and FIG. 7 , the fourth period 240 is used to turn off the light-emitting unit 110 . During the fourth period 240, the control signal S1 and the control signal S2 are at the low level V _GL , the control signal EM is at the high level V _GH , and the control signal V _sweep is at the high level V _{sweep_H} . Therefore, the switches T6 and T7 are turned on, and the switches T1 , T2 , T3 , T5 , and T8 to T12 are turned off. During this period, the potentials of the node B and the node C are the diode voltage V _LED . The potential of node B changes from VSS in the second sub-period 230-2 to _{VLED in the fourth period 240 by VLED-VSS, so the potential of node A is Vref+VTH_T4 + from} this period _230-2 The VSS-V _LED changes to V _ref +V _{TH_T4} . The potential of the node D is the same as the control signal V _sweep . The potential of node E is the same as V _DATA +|V _{TH_T8} |.

In the above-described embodiments, "connection" may be a direct connection.

Although the present invention has been disclosed by the above examples, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to those defined in the claims.

Claims (10)

1. A pixel drive circuit, comprising: a light-emitting unit having a first end and a second end, the first end of the light-emitting unit is connected to a first operating voltage; A first switch has a first end, a second end and a control end, the first end of the first switch is connected to the second end of the light-emitting unit, and the second end of the first switch is connected to the second operating voltage; A second switch has a first end, a second end and a control end, the first end of the second switch is connected to the control end of the first switch, and the second end of the second switch is connected to to the second terminal of the first switch and the second operating voltage, the control terminal of the second switch is connected to a first control signal; a first capacitor having a first end and a second end, the first end of the first capacitor is connected to the control end of the first switch and the first end of the second switch; A second capacitor has a first end and a second end, the first end of the second capacitor is connected to the second end of the first capacitor, and the second end of the second capacitor is connected to a reference Voltage; A third switch has a first end, a second end and a control end, the first end of the third switch is connected to the control end of the first switch, the first end of the second switch and The first end of the first capacitor and the control end of the third switch are connected to a second control signal; A fourth switch has a first end, a second end and a control end, the first end of the fourth switch is connected to the control end of the fourth switch, and the second end of the fourth switch is connected to the reference voltage; A fifth switch has a first end, a second end and a control end, the first end of the fifth switch is connected to the second end of the first switch and the second end of the second switch , the second end of the fifth switch is connected to the second end of the first capacitor and the first end of the second capacitor; A sixth switch has a first end, a second end and a control end, the first end of the sixth switch is connected to the second end of the fifth switch and the second end of the first capacitor and the first end of the second capacitor, the second end of the sixth switch is connected to a diode voltage, and the control end of the sixth switch is connected to a third control signal; A seventh switch has a first end, a second end and a control end, the first end of the seventh switch is connected to the control end of the fifth switch, and the second end of the seventh switch is connected to the diode voltage, the control terminal of the seventh switch is connected to the third control signal; an eighth switch, having a first end, a second end and a control end, the first end of the eighth switch is connected to the control end of the fifth switch and the first end of the seventh switch; a third capacitor having a first terminal and a second terminal, the first terminal of the third capacitor is connected to the second terminal of the eighth switch, and the second terminal of the third capacitor is connected to the reference Voltage; a ninth switch, having a first terminal, a second terminal and a control terminal, the first terminal of the ninth switch is connected to the first terminal of the third capacitor and the second terminal of the eighth switch , the second end of the ninth switch is connected to the first control signal, and the control end of the ninth switch is connected to the first control signal; A tenth switch has a first end, a second end and a control end, the first end of the tenth switch is connected to the second end of the eighth switch and the first end of the third capacitor and the first end of the ninth switch, the second end of the tenth switch is connected to the control end of the eighth switch, and the control end of the tenth switch is connected to the first control signal; An eleventh switch has a first end, a second end and a control end, the first end of the eleventh switch is connected to the control end of the eighth switch and the second end of the tenth switch terminal, the second terminal of the eleventh switch is connected to a fourth control signal, and the control terminal of the eleventh switch is connected to the third control signal; A twelfth switch has a first end, a second end and a control end, the first end of the twelfth switch is connected to the control end of the eighth switch and the second end of the tenth switch terminal and the first terminal of the eleventh switch, the second terminal of the twelfth switch is connected to a data voltage, and the control terminal of the twelfth switch is connected to the second control signal. 2. The pixel driving circuit of claim 1, wherein the pixel driving circuit operates in a first period, a second period, a third period and a fourth period in sequence, During the first period, the second switch, the fourth switch, the sixth switch, the seventh switch, the ninth switch and the tenth switch are in an on state, the first switch, the first switch The third switch, the fifth switch, the eighth switch, the eleventh switch and the twelfth switch are in an off state, Wherein in the second period, the third switch, the fourth switch, the sixth switch, the seventh switch, the eighth switch and the twelfth switch are in the on state, the first switch, the The second switch, the fifth switch, the ninth switch, the tenth switch and the eleventh switch are in the off state, Wherein in a first sub-period of the third period, the eleventh switch is in the on state, the first switch to the third switch, the fifth switch to the tenth switch and the twelfth switch The switch is in this cut-off state, Wherein in a second sub-period of the third period, the first switch, the fifth switch, the eighth switch and the eleventh switch are in the on state, the second switch, the third switch , the sixth switch, the seventh switch, the ninth switch, the tenth switch and the twelfth switch are in the off state, During the fourth period, the sixth switch and the seventh switch are in the on state, the first switch, the second switch, the third switch, the fifth switch, the eighth switch to the first switch The twelve switches are in this off state. 3. The pixel driving circuit of claim 2, wherein the eighth switch and the eleventh switch are P-type transistors, the first switch to the seventh switch, the ninth switch, the tenth switch and the The twelfth switch is an N-type transistor. 4. The pixel driving circuit of claim 3, wherein a threshold voltage of the first switch is matched to a threshold voltage of the fourth switch. 5. The pixel driving circuit of claim 3, wherein during the first period, the first control signal and the third control signal are at a first high level, and the second control signal is at a first low level level, the fourth control signal is a second high level, During the second period, the first control signal is at the first low level, the second control signal and the third control signal are at the first high level, and the fourth control signal is at the second high level level, During the third period, the first control signal, the second control signal and the third control signal are at the first low level, and the fourth control signal gradually decreases from the second high level to a The second low level, During the fourth period, the first control signal and the second control signal are at the first low level, the third control signal is at the first high level, and the fourth control signal is at the second high level level. 6. The pixel driving circuit of claim 5, wherein the first operating voltage is greater than the second operating voltage. 7. The pixel driving circuit of claim 1, wherein the light emitting unit is a light emitting diode. 8. The pixel driving circuit of claim 7, wherein the size of the light emitting diode is sub-millimeter. 9. The pixel driving circuit of claim 1, wherein the pixel driving circuit is disposed in a display panel. 10. The pixel driving circuit of claim 1, wherein the pixel driving circuit is disposed in a backlight module.

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