CN110767151A - Light emitting diode display panel - Google Patents
Light emitting diode display panel Download PDFInfo
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- CN110767151A CN110767151A CN201910995007.4A CN201910995007A CN110767151A CN 110767151 A CN110767151 A CN 110767151A CN 201910995007 A CN201910995007 A CN 201910995007A CN 110767151 A CN110767151 A CN 110767151A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
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Abstract
The invention discloses a light emitting diode display panel. The light emitting diode display panel comprises a plurality of data lines, a plurality of gate lines, a plurality of pixels and a second transistor. The plurality of pixels are arranged in an effective display area of the light-emitting diode display panel. A first pixel of the plurality of pixels includes a light emitting diode and a first transistor. The light emitting diode is coupled to a ground voltage. The first transistor is coupled between a first data line of the plurality of data lines and the light emitting diode. The gate of the first transistor is coupled to a first gate line of the plurality of gate lines and is controlled by a driving signal provided by the first gate line. The second transistor is disposed outside the effective display area. The second transistor is coupled to the first data line and a gate of the second transistor is controlled by a switching signal.
Description
Technical Field
The present invention relates to a display, and more particularly, to a Light-Emitting Diode (LED) display panel.
Background
Referring to fig. 1 and 2, fig. 1 is a schematic diagram illustrating a pixel design of a conventional led display panel; fig. 2 is a timing diagram illustrating the control signals of the second transistor in fig. 1.
As shown in fig. 1, a pixel 1 of a conventional led display panel adopts a "2T 1C" structure, i.e., each pixel includes a first transistor T1, a second transistor T2 and a storage capacitor CS. The first transistor T1 is disposed between the operating voltage VDD and the light emitting diode LED, and the first transistor T1 is controlled by the gate voltage VG; the second transistor T2 is disposed between the gate of the first transistor T1 and the data signal VDAT, and the second transistor T2 is controlled by the driving signal s (n); one end of the storage capacitor CS is coupled between the second transistor T2 and the gate of the first transistor T1, and the other end of the storage capacitor CS is coupled between the first transistor T1 and the light emitting diode LED.
In general, the existing "2T 1C" architecture is better suited for pixels that employ voltage-Holding-mode (Holding-type) imaging. However, since the driving current (of the order of mA) of the light Emitting Diode LED is much larger than that (of the order of uA) of the organic light-Emitting Diode (OLED), the total current of the light Emitting Diode display panel adopting the voltage holding mode is too high, and thus the power consumption is increased.
In addition, since the width of the first transistor T1 disposed between the operating voltage VDD and the light emitting diode LED in each pixel is relatively large, with the development trend of high-resolution display panels, when the pixel density (PPI) is increased, the circuit layout difficulty of the pixel is greatly increased due to the limitation of each element and routing, which needs to be overcome.
Disclosure of Invention
Therefore, the present invention provides a light emitting diode display panel to solve the above problems encountered in the prior art.
An embodiment of the present invention is an led display panel. In this embodiment, the led display panel includes a plurality of data lines, a plurality of gate lines, a plurality of pixels and a second transistor. The plurality of pixels are arranged in an effective display area of the light-emitting diode display panel. A first pixel of the plurality of pixels includes a light emitting diode and a first transistor. The light emitting diode is coupled to a ground voltage. The first transistor is coupled between a first data line of the plurality of data lines and the light emitting diode. The gate of the first transistor is coupled to a first gate line of the plurality of gate lines and is controlled by a driving signal provided by the first gate line. The second transistor is disposed outside the effective display area. The second transistor is coupled to the first data line and a gate of the second transistor is controlled by a switching signal.
In one embodiment, a coupling capacitor is disposed between the first data line and the first gate line for storing charges.
In one embodiment, a second pixel of the plurality of pixels includes another light emitting diode and another first transistor. The other light emitting diode is coupled to a ground voltage. The other first transistor is coupled between the first data line and the other light emitting diode, and a gate of the first transistor is coupled to a second gate line of the plurality of gate lines and controlled by another driving signal provided by the second gate line. The first pixel and the second pixel share the second transistor through the first data line.
In one embodiment, the first pixel further includes a storage capacitor having one end coupled to the first data line and the other end coupled between the light emitting diode and a ground voltage for storing charges.
In an embodiment, the second transistor is further coupled to the driving circuit and receives a data signal provided by the driving circuit, and when the second transistor is controlled by the switching signal to be turned on, the second transistor outputs the data signal to the first data line.
In an embodiment, the led display panel further includes a third transistor disposed outside the active display area, the third transistor is coupled between the first data line and the driving circuit, and a gate of the third transistor is controlled by a reference signal.
In one embodiment, when the third transistor is controlled by the reference signal to be turned on, the third transistor detects a current of the first data line and outputs a feedback signal to the driving circuit as a reference for compensation.
In one embodiment, when the first transistor is controlled by the driving signal to be turned on, the current passing through the first transistor drives the light emitting diode to emit light.
In an embodiment, the led display panel further includes another second transistor disposed outside the effective display area, the another second transistor is coupled to a second data line of the plurality of data lines, and a gate of the another second transistor is controlled by another switching signal.
In an embodiment, the third pixel and the fourth pixel of the plurality of pixels are coupled to the second data line and share the other second transistor through the second data line.
Compared with the prior art, the pixel design of the light emitting diode display panel adopts a 1T1C structure or a 1T structure, but not a traditional 2T1C structure, namely, each pixel comprises a first transistor and a storage capacitor or only comprises the first transistor, and the second transistor is shared outside an effective display area, so that the circuit layout is easier, and even under the condition of improving the pixel density, the circuit layout difficulty is not easily limited by each element and routing and is greatly increased, so that the light emitting diode display panel is suitable for the panel design with high resolution.
In addition, since the led display panel of the present invention adopts the pulse driving mode (Impulse driving mode) to drive all the pixels in a divisional manner, and the required current is lower than that of the conventional voltage Holding mode (Holding-type), the total power consumption of the led display panel can be effectively reduced, and a multiplexer can be disposed between the driving circuit and the second transistor to reduce the number of the required driving circuits.
The advantages and spirit of the present invention can be further understood by the following detailed description of the invention and the accompanying drawings.
Drawings
Fig. 1 is a schematic diagram showing a pixel design of a conventional led display panel.
Fig. 2 is a timing diagram illustrating control signals of the second transistor in fig. 1.
FIG. 3 is a schematic diagram of an LED display panel according to an embodiment of the invention.
Fig. 4 is a timing diagram illustrating the switching signals, the data signals and the driving signals in fig. 3.
FIG. 5 is a schematic diagram of an LED display panel according to another embodiment of the invention.
Fig. 6 is a timing diagram illustrating the switching signals, the data signals and the driving signals in fig. 5.
FIG. 7 is a schematic diagram of an LED display panel according to another embodiment of the invention.
FIG. 8 is a timing diagram illustrating the switching signals, the data signals, the driving signals and the reference voltages in FIG. 7.
Wherein, the reference numbers:
1: pixel
VDD: operating voltage
VD: drain voltage
VS: source voltage
VG: grid voltage
3. 5, 7: light emitting diode display panel
AA: effective display area
PX 1-PX 4: pixel
DL (i-1) to DL (i): data line
GL (N-1) to GL (N): gate line
S (N-1) to S (N + 1): drive signal
SW (i-1) to SW (i): switching signal
T1: a first transistor
LED: light emitting diode
CC: coupling capacitor
VSS: ground voltage
T2: second transistor
VDAT: data signal
CS: storage capacitor
I: electric current
VGH: high level
VGL: low level of electricity
And (3) LEP: during the light emitting period
VREF: reference voltage
T3: a third transistor
IC: driving circuit
Detailed Description
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, without departing from the spirit or scope of the present invention.
In the drawings, portions of regions are exaggerated for clarity. Like reference numerals refer to like elements throughout the specification. It will be understood that when an element such as a region or substrate is referred to as being "on" or "connected (or coupled)" to another element or "electrically connected" to another element, it can be directly on or connected (or coupled) to the other element or electrically connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected (or referred to as coupled)" may refer to physical and/or electrical connections.
An embodiment of the present invention is an led display panel. Referring to fig. 3, fig. 3 is a schematic diagram illustrating an led display panel in this embodiment.
As shown in fig. 3, the led display panel 3 includes a plurality of data lines DL (i-1) to DL (i), a plurality of gate lines GL (N-1) to GL (N), a plurality of pixels PX1 to PX4, and a plurality of second transistors T2, where i and N are positive integers. It should be noted that, although two data lines, two gate lines, four pixels and two second transistors are taken as examples in this embodiment, the invention is not limited thereto.
The led display panel 3 includes an effective display area AA. The plurality of pixels PX 1-PX 4 are disposed in the effective display area AA of the led display panel 3 and the plurality of second transistors T2 are disposed outside the effective display area AA of the led display panel 3.
A first data line DL (i-1) of the data lines DL (i-1) -DL (i) is coupled to the first pixel PX1 and the second pixel PX2 of the pixels PX 1-PX 4 and a second transistor T2 of the second transistors T2; a second data line DL (i) of the plurality of data lines DL (i-1) to DL (i) is coupled to a third pixel PX3 and a fourth pixel PX4 of the plurality of pixels PX1 to PX4 and another second transistor T2 of the plurality of second transistors T2; a first gate line GL (N-1) of the gate lines GL (N-1) -GL (N) is coupled to a first pixel PX1 and a third pixel PX3 of the pixels PX 1-PX 4; a second gate line GL (N) of the gate lines GL (N-1) to GL (N) is coupled to a second pixel PX2 and a fourth pixel PX4 of the pixels PX1 to PX 4.
That is, the first pixel PX1 of the plurality of pixels PX 1-PX 4 is respectively coupled to the first data line DL (i-1) of the plurality of data lines DL (i-1) -DL (i) and the first gate line GL (N-1) of the plurality of gate lines GL (N-1) -GL (N); a second pixel PX2 of the plurality of pixels PX 1-PX 4 is respectively coupled to a first data line DL (i-1) of the plurality of data lines DL (i-1) -DL (i) and a second gate line GL (N) of the plurality of gate lines GL (N-1) -GL (N); a third pixel PX3 of the plurality of pixels PX 1-PX 4 is respectively coupled to a second data line DL (i) of the plurality of data lines DL (i-1) -DL (i) and a first gate line GL (N-1) of the plurality of gate lines GL (N-1) -GL (N); the fourth pixel PX4 of the plurality of pixels PX 1-PX 4 is respectively coupled to the second data line DL (i) of the plurality of data lines DL (i-1) -DL (i) and the second gate line GL (N) of the plurality of gate lines GL (N-1) -GL (N). A second transistor T2 coupled to the first data line DL (i-1) in common for the first pixel PX1 and the second pixel PX2 of the plurality of pixels PX 1-PX 4; the third pixel PX3 and the fourth pixel PX4 of the plurality of pixels PX 1-PX 4 share the second transistor T2 coupled to the second data line dl (i).
In this embodiment, the pixels PX 1-PX 4 are designed as "1T 1C" pixels, that is, each of the pixels PX 1-PX 4 includes a transistor and a capacitor.
Taking the first pixel PX1 as an example, the first pixel PX1 includes a light emitting diode LED, a first transistor T1, and a storage capacitor CS. The light emitting diode LED is coupled to a ground voltage VSS. The first transistor T1 is coupled between the first data line DL (i-1) of the data lines DL (i-1) -DL (i) and the light emitting diode LED. The gate of the first transistor T1 is coupled to a first gate line GL (N-1) of the gate lines GL (N-1) -GL (N) and controlled by a driving signal S (N-1) provided by the first gate line GL (N-1). One end of the storage capacitor CS is coupled to the first data line DL (i-1) and the other end of the storage capacitor CS is coupled between the light emitting diode LED and the ground voltage VSS for storing charges.
Similarly, if the second pixel PX2 is taken as an example, the second pixel PX2 also includes a light emitting diode LED, a first transistor T1 and a storage capacitor CS. The light emitting diode LED is coupled to a ground voltage VSS. The first transistor T1 is coupled between the first data line DL (i-1) of the data lines DL (i-1) -DL (i) and the light emitting diode LED. The gate of the first transistor T1 is coupled to a second gate line GL (N) of the plurality of gate lines GL (N-1) to GL (N) and is controlled by a driving signal s (N) provided by the second gate line GL (N). One end of the storage capacitor CS is coupled to the first data line DL (i-1) and the other end of the storage capacitor CS is coupled between the light emitting diode LED and the ground voltage VSS for storing charges.
Similarly, if the third pixel PX3 is taken as an example, the third pixel PX3 also includes a light emitting diode LED, a first transistor T1 and a storage capacitor CS. The light emitting diode LED is coupled to a ground voltage VSS. The first transistor T1 is coupled between a second data line DL (i) of the data lines DL (i-1) to DL (i) and the light emitting diode LED. The gate of the first transistor T1 is coupled to a first gate line GL (N-1) of the gate lines GL (N-1) -GL (N) and controlled by a driving signal S (N-1) provided by the first gate line GL (N-1). One end of the storage capacitor CS is coupled to the second data line dl (i) and the other end of the storage capacitor CS is coupled between the light emitting diode LED and the ground voltage VSS for storing charges.
Similarly, if the fourth pixel PX4 is taken as an example, the fourth pixel PX4 also includes a light emitting diode LED, a first transistor T1 and a storage capacitor CS. The light emitting diode LED is coupled to a ground voltage VSS. The first transistor T1 is coupled between a second data line DL (i) of the data lines DL (i-1) to DL (i) and the light emitting diode LED. The gate of the first transistor T1 is coupled to a second gate line GL (N) of the plurality of gate lines GL (N-1) to GL (N) and is controlled by a driving signal s (N) provided by the second gate line GL (N). One end of the storage capacitor CS is coupled to the second data line dl (i) and the other end of the storage capacitor CS is coupled between the light emitting diode LED and the ground voltage VSS for storing charges.
The second transistor T2 coupled to the first data line DL (i-1) is also coupled to the data signal VDAT and the gate of the second transistor T2 is controlled by the switching signal SW (i-1); the second transistor T2 coupled to the second data line dl (i) is also coupled to the data signal VDAT and the gate of the second transistor T2 is controlled by the switching signal sw (i).
In practical applications, the plurality of second transistors T2 may be coupled to the driving circuit through a multiplexer and receive the data signal VDAT provided by the driving circuit, and the multiplexer may be of one-to-two, one-to-three or other design, so as to reduce the number of driving circuits, but not limited thereto.
Please refer to fig. 1 and fig. 2. Taking the first pixel PX1 as an example, when the switching signal SW (i-1) changes from the low level VGL to the high level VGH, and the other switching signal SW (i) still maintains the low level VGL, the second transistor T2 controlled by the switching signal SW (i-1) is turned on, so as to charge the storage capacitors CS in the first pixel PX1 and the second pixel PX2 through the first data line DL (i-1), respectively. After the switching signal SW (i-1) changes from the high level VGH to the low level VGL, when another switching signal SW (i) changes from the low level VGL to the high level VGH, the second transistor T2 controlled by the switching signal SW (i) is turned on, so as to charge the storage capacitors CS in the third pixel PX3 and the fourth pixel PX4 through the second data line dl (i), respectively.
Then, when the driving signal S (N-1) originally maintained at the low level VGL changes to the high level VGH, the first transistor T1 controlled by the driving signal S (N-1) in the first pixel PX1 is turned on, so that the charges stored in the storage capacitors CS of the first pixel PX1 and the second pixel PX2 flow to the first transistor T1 in the first pixel PX1 to form a current I passing through the first transistor T1, so as to drive the light emitting diode LED in the first pixel PX1 to emit light. Therefore, a period during which the driving signal S (N-1) is at the high level VGH for the first pixel PX1 may be referred to as a "light emitting period LEP".
Similarly, for the third pixel PX3, when the driving signal S (N-1) is at the high level VGH, the first transistor T1 controlled by the driving signal S (N-1) in the third pixel PX3 is also turned on, so that the charges stored in the storage capacitor CS of the third pixel PX3 and the fourth pixel PX4 flow to the first transistor T1 in the third pixel PX3 to form a current I through the first transistor T1, so as to drive the light emitting diode LED in the third pixel PX3 to emit light. Therefore, the period of the third pixel PX3 during which the driving signal S (N-1) is at the high level VGH may also be referred to as a "light emitting period LEP".
Similarly, for the second pixel PX2, when the driving signal s (n) is at the high level VGH, the first transistor T1 controlled by the driving signal s (n) in the second pixel PX2 is also turned on, so that the charges stored in the storage capacitor CS of the first pixel PX1 and the second pixel PX2 flow to the first transistor T1 in the second pixel PX2 to form a current I through the first transistor T1, so as to drive the light emitting diode LED in the second pixel PX2 to emit light. Therefore, for the second pixel PX2, the period during which the driving signal s (n) is at the high level VGH may also be referred to as the "light-emitting period LEP".
Similarly, for the fourth pixel PX4, when the driving signal s (n) is at the high level VGH, the first transistor T1 controlled by the driving signal s (n) in the fourth pixel PX4 is also turned on, so that the charges stored in the storage capacitors CS of the third pixel PX3 and the fourth pixel PX4 flow to the first transistor T1 in the fourth pixel PX4 to form a current I through the first transistor T1, so as to drive the light emitting diode LED in the fourth pixel PX4 to emit light. Therefore, for the fourth pixel PX4, the period during which the driving signal s (n) is at the high level VGH may also be referred to as the "light-emitting period LEP".
In another embodiment, referring to fig. 5, the pixels PX 1-PX 4 in the led display panel 5 are all designed as "1T" pixels, i.e., each of the pixels PX 1-PX 4 in the led display panel 5 includes the first transistor T1 but does not include the storage capacitor CS in the previous embodiment.
Please refer to fig. 5 and fig. 6. For example, in the case of the first pixel PX1, when the switching signal SW (i-1) changes from the low level VGL to the high level VGH, the other switching signal SW (i) still maintains the low level VGL, and the second transistor T2 controlled by the switching signal SW (i-1) is turned on, at this time, the charges transmitted through the first data line DL (i-1) can be stored in the coupling capacitor CC, such as the coupling capacitor CC between the first data line DL (i-1) and the first gate line GL (N-1) and the coupling capacitor CC between the first data line DL (i-1) and the second gate line GL (N), but not limited thereto. In fact, the coupling capacitor CC may be another capacitor coupled to the first data line DL (i-1), but not limited thereto.
After the switching signal SW (i-1) is changed from the high level VGH to the low level VGL, when another switching signal SW (i) is changed from the low level VGL to the high level VGH, the second transistor T2 controlled by the switching signal SW (i) is turned on, and at this time, the charges transmitted through the second data line dl (i) can be stored in the coupling capacitor CC, such as the coupling capacitor CC between the second data line dl (i) and the first gate line GL (N-1) and the coupling capacitor CC between the second data line dl (i) and the second gate line GL (N), but not limited thereto. In fact, the coupling capacitor CC may be another capacitor coupled to the second data line dl (i), but not limited thereto.
Then, when the driving signal S (N-1) originally maintained at the low level VGL changes to the high level VGH, the first transistor T1 controlled by the driving signal S (N-1) in the first pixel PX1 is turned on, so that the charges stored in the coupling capacitor CC between the first data line DL (I-1) and the first gate line GL (N-1) and the coupling capacitor CC between the first data line DL (I-1) and the second gate line GL (N) flow to the first transistor T1 in the first pixel PX1 to form a current I passing through the first transistor T1, so as to drive the light emitting diode LED in the first pixel PX1 to emit light. Therefore, a period during which the driving signal S (N-1) is at the high level VGH for the first pixel PX1 may be referred to as a "light emitting period LEP".
Similarly, for the third pixel PX3, when the driving signal S (N-1) is at the high level VGH, the first transistor T1 of the third pixel PX3 controlled by the driving signal S (N-1) is also turned on, so that the charges stored in the coupling capacitor CC between the second data line dl (I) and the first gate line GL (N-1) and the coupling capacitor CC between the second data line dl (I) and the second gate line GL (N) flow to the first transistor T1 of the third pixel PX3 to form a current I passing through the first transistor T1, so as to drive the light emitting diode LED of the third pixel PX3 to emit light. Therefore, the period of the third pixel PX3 during which the driving signal S (N-1) is at the high level VGH may also be referred to as a "light emitting period LEP".
Similarly, for the second pixel PX2, when the driving signal s (N) is at the high level VGH, the first transistor T1 controlled by the driving signal s (N) in the second pixel PX2 is also turned on, so that the charges stored in the coupling capacitor CC between the first data line DL (I-1) and the first gate line GL (N-1) and the coupling capacitor CC between the first data line DL (I-1) and the second gate line GL (N) flow to the first transistor T1 in the second pixel PX2 to form a current I through the first transistor T1, so as to drive the light emitting diode LED in the second pixel PX2 to emit light. Therefore, for the second pixel PX2, the period during which the driving signal s (n) is at the high level VGH may also be referred to as the "light-emitting period LEP".
Similarly, for the fourth pixel PX4, when the driving signal s (N) is at the high level VGH, the first transistor T1 controlled by the driving signal s (N) in the fourth pixel PX4 is also turned on, so that the charges stored in the coupling capacitor CC between the second data line dl (I) and the first gate line GL (N-1) and the coupling capacitor CC between the second data line dl (I) and the second gate line GL (N) flow to the first transistor T1 in the fourth pixel PX4 to form a current I passing through the first transistor T1, so as to drive the light emitting diode LED in the fourth pixel PX4 to emit light. Therefore, for the fourth pixel PX4, the period during which the driving signal s (n) is at the high level VGH may also be referred to as the "light-emitting period LEP".
In another embodiment, referring to fig. 7, the pixels PX 1-PX 4 of the led display panel 7 and the pixels PX 1-PX 4 of the led display panel 3 of fig. 3 are all designed as "1T 1C" pixels, that is, each of the pixels PX 1-PX 4 of the led display panel 7 includes a first transistor T1 and a storage capacitor CS.
The led display panel 7 in fig. 7 is different from the led display panel 3 in fig. 3 in that: the led display panel 7 of fig. 7 further designs a compensation loop around the effective display area AA, for example, the led display panel 7 of fig. 7 further includes a plurality of third transistors T3 disposed outside the effective display area AA.
As shown in fig. 7, a third transistor T3 of the plurality of third transistors T3 included in the led display panel 7 is coupled between the first data line DL (i-1) and the driving circuit IC, and the gate of the third transistor T3 is controlled by the reference signal VREF; another third transistor T3 of the plurality of third transistors T3 is coupled between the second data line dl (i) and the driving circuit IC, and the gate of the third transistor T3 is also controlled by the reference signal VREF.
Please also refer to fig. 7 and fig. 8. During the period when the switching signal SW (i-1) is at the high level VGH to charge the first data line DL (i-1), when the reference signal VREF changes from the low level VGL to the high level VGH, the third transistor T3 coupled to the first data line DL (i-1) is controlled by the reference signal VREF to be turned on, so as to detect the current of the first data line DL (i-1) and output the feedback signal to the driving circuit IC for the compensation reference of the driving circuit IC.
Similarly, during the period when the switching signal sw (i) is at the high level VGH to charge the second data line dl (i), when the reference signal VREF changes from the low level VGL to the high level VGH, the third transistor T3 coupled to the second data line dl (i) is controlled by the reference signal VREF to be turned on, so as to detect the current of the second data line dl (i) and output the feedback signal to the driving circuit IC for the compensation reference of the driving circuit IC.
Compared with the prior art, the pixel design of the light emitting diode display panel adopts a 1T1C structure or a 1T structure, but not a traditional 2T1C structure, namely, each pixel comprises a first transistor and a storage capacitor or only comprises the first transistor, and the second transistor is shared outside an effective display area, so that the circuit layout is easier, and even under the condition of improving the pixel density, the circuit layout difficulty is not easily limited by each element and routing and is greatly increased, so that the light emitting diode display panel is suitable for the panel design with high resolution.
In addition, since the led display panel of the present invention adopts the pulse driving mode (Impulse driving mode) to drive all the pixels in a divisional manner, and the required current is lower than that of the conventional voltage Holding mode (Holding-type), the total power consumption of the led display panel can be effectively reduced, and a multiplexer can be disposed between the driving circuit and the second transistor to reduce the number of the required driving circuits.
The above detailed description of the preferred embodiments is intended to more clearly illustrate the features and spirit of the present invention, and is not intended to limit the scope of the present invention by the preferred embodiments disclosed above. On the contrary, it is intended to cover various modifications and equivalent arrangements included within the scope of the claims.
Claims (10)
1. A light emitting diode display panel, comprising:
a plurality of data lines;
a plurality of gate lines;
a plurality of pixels disposed in an effective display area of the led display panel, a first pixel of the plurality of pixels comprising:
a light emitting diode coupled to a ground voltage; and
a first transistor coupled between a first data line of the data lines and the light emitting diode, a gate of the first transistor being coupled to a first gate line of the gate lines and controlled by a driving signal provided by the first gate line; and
and a second transistor disposed outside the effective display area, the second transistor being coupled to the first data line and having a gate controlled by a switching signal.
2. The light-emitting diode display panel of claim 1, wherein a coupling capacitor is disposed between the first data line and the first gate line for storing charges.
3. The led display panel of claim 1, wherein a second pixel of the plurality of pixels comprises:
another LED coupled to the grounding voltage; and
another first transistor, coupled between the first data line and the another light emitting diode, having a gate coupled to a second gate line of the plurality of gate lines and controlled by another driving signal provided by the second gate line;
the first pixel and the second pixel share the second transistor through the first data line.
4. The led display panel of claim 1, wherein the first pixel further comprises:
and one end of the storage capacitor is coupled with the first data line, and the other end of the storage capacitor is coupled between the light-emitting diode and the grounding voltage for storing charges.
5. The light-emitting diode display panel according to claim 1, wherein the second transistor is further coupled to a driving circuit and receives a data signal provided by the driving circuit, and when the second transistor is turned on by the switching signal, the second transistor outputs the data signal to the first data line.
6. The light-emitting diode display panel according to claim 1, further comprising:
and a third transistor disposed outside the effective display area, wherein the third transistor is coupled between the first data line and a driving circuit and has a gate controlled by a reference signal.
7. The light emitting diode display panel of claim 6, wherein when the third transistor is turned on by the reference signal, the third transistor detects a current of the first data line and outputs a feedback signal to the driving circuit for compensation reference.
8. The light-emitting diode display panel according to claim 1, wherein when the first transistor is turned on by the driving signal, a current through the first transistor drives the light-emitting diode to emit light.
9. The light-emitting diode display panel according to claim 1, further comprising:
and another second transistor disposed outside the effective display area, the another second transistor being coupled to a second data line of the plurality of data lines and having a gate controlled by another switching signal.
10. The led display panel of claim 9, wherein a third pixel and a fourth pixel of the plurality of pixels are coupled to the second data line and share the second transistor via the second data line.
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| TW108109870A TWI736862B (en) | 2019-03-21 | 2019-03-21 | Light-emitting diode display panel |
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| CN110767151B CN110767151B (en) | 2024-02-27 |
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Also Published As
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| TW202036519A (en) | 2020-10-01 |
| CN110767151B (en) | 2024-02-27 |
| TWI736862B (en) | 2021-08-21 |
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