TWI736862B - Light-emitting diode display panel - Google Patents
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- TWI736862B TWI736862B TW108109870A TW108109870A TWI736862B TW I736862 B TWI736862 B TW I736862B TW 108109870 A TW108109870 A TW 108109870A TW 108109870 A TW108109870 A TW 108109870A TW I736862 B TWI736862 B TW I736862B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
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Abstract
Description
本發明係與顯示器有關,尤其是關於一種發光二極體(Light-Emitting Diode, LED)顯示面板。The present invention relates to displays, and particularly relates to a light-emitting diode (LED) display panel.
請參照圖1及圖2,圖1係繪示習知的發光二極體顯示面板的畫素設計示意圖;圖2則係繪示圖1中之第二電晶體的控制訊號的時序圖。Please refer to FIGS. 1 and 2. FIG. 1 is a schematic diagram of the pixel design of a conventional light emitting diode display panel; FIG. 2 is a timing diagram of the control signal of the second transistor in FIG.
如圖1所示,目前常見的發光二極體顯示面板的畫素1係採用「2T1C」架構,亦即每一畫素包括第一電晶體T1、第二電晶體T2及儲存電容CS。其中,第一電晶體T1設置於工作電壓VDD與發光二極體LED之間,且第一電晶體T1受控於閘極電壓VG;第二電晶體T2設置於第一電晶體T1的閘極與資料訊號VDAT之間,且第二電晶體T2受控於驅動訊號S(N);儲存電容CS之一端耦接至第二電晶體T2與第一電晶體T1的閘極之間且儲存電容CS之另一端耦接至第一電晶體T1與發光二極體LED之間。As shown in FIG. 1, the
一般而言,習知的「2T1C」架構較適用於採用電壓保持模式(Holding-type)成像的畫素。然而,由於發光二極體LED的驅動電流(約為mA等級)遠大於有機發光二極體(Organic Light-Emitting Diode, OLED)的驅動電流(約為uA等級),導致採用電壓保持模式的發光二極體顯示面板的總電流過高而增加功耗。Generally speaking, the conventional "2T1C" architecture is more suitable for pixels that adopt the holding-type imaging. However, because the driving current of the light-emitting diode LED (approximately mA level) is much larger than the driving current (approximately uA level) of the organic light-emitting diode (Organic Light-Emitting Diode, OLED), the voltage holding mode is used for light emission. The total current of the diode display panel is too high and the power consumption is increased.
此外,由於每一畫素中設置於工作電壓VDD與發光二極體LED之間的第一電晶體T1所需的寬度較大,隨著高解析度顯示面板之發展趨勢,當畫素密度(PPI)提高時,將會導致畫素的電路佈局難度受限於各元件及走線而大幅增加,亟待克服。In addition, since the width of the first transistor T1 provided between the operating voltage VDD and the light-emitting diode LED in each pixel is relatively large, with the development trend of high-resolution display panels, when the pixel density ( When the PPI is increased, the difficulty of the circuit layout of the pixel will be greatly increased due to the limitation of various components and wiring, which needs to be overcome urgently.
因此,本發明提出一種發光二極體顯示面板,以解決先前技術所遭遇的上述問題。Therefore, the present invention proposes a light emitting diode display panel to solve the above-mentioned problems encountered in the prior art.
根據本發明之一具體實施例為一種發光二極體顯示面板。於此實施例中,發光二極體顯示面板包括複數條資料線、複數條閘極線、複數個畫素及第二電晶體。該複數個畫素設置於發光二極體顯示面板之有效顯示區域內。該複數個畫素中之第一畫素包括發光二極體及第一電晶體。發光二極體耦接至接地電壓。第一電晶體耦接於該複數條資料線中之第一資料線與發光二極體之間。第一電晶體之閘極耦接該複數條閘極線中之第一閘極線並受控於第一閘極線所提供之驅動訊號。第二電晶體設置於有效顯示區域之外。第二電晶體耦接第一資料線且第二電晶體之閘極受控於切換訊號。A specific embodiment according to the present invention is a light emitting diode display panel. In this embodiment, the light emitting diode display panel includes a plurality of data lines, a plurality of gate lines, a plurality of pixels, and a second transistor. The plurality of pixels are arranged in the effective display area of the light-emitting diode display panel. The first pixel of the plurality of pixels includes a light-emitting diode and a first transistor. The light emitting diode is coupled to the ground voltage. The first transistor is coupled between the first data line of the plurality of data lines and the light emitting diode. The gate of the first transistor is coupled to the first gate line of the plurality of gate lines and controlled by the driving signal provided by the first gate line. The second transistor is arranged outside the effective display area. The second transistor is coupled to the first data line and the gate of the second transistor is controlled by the switching signal.
於一實施例中,第一資料線與第一閘極線之間具有耦合電容,用以儲存電荷。In one embodiment, there is a coupling capacitor between the first data line and the first gate line for storing charge.
於一實施例中,該複數個畫素中之第二畫素包括另一發光二極體及另一第一電晶體。該另一發光二極體耦接至接地電壓。該另一第一電晶體耦接於第一資料線與該另一發光二極體之間,第一電晶體之閘極耦接該複數條閘極線中之第二閘極線並受控於第二閘極線所提供之另一驅動訊號。第一畫素與第二畫素透過第一資料線共用第二電晶體。In one embodiment, the second pixel of the plurality of pixels includes another light-emitting diode and another first transistor. The other light-emitting diode is coupled to the ground voltage. The other first transistor is coupled between the first data line and the other light-emitting diode, and the gate of the first transistor is coupled to the second gate line of the plurality of gate lines and controlled Another driving signal provided by the second gate line. The first pixel and the second pixel share the second transistor through the first data line.
於一實施例中,第一畫素還包括儲存電容,其一端耦接第一資料線且其另一端耦接至發光二極體與接地電壓之間,用以儲存電荷。In one embodiment, the first pixel further includes a storage capacitor, one end of which is coupled to the first data line and the other end of which is coupled between the light emitting diode and the ground voltage for storing charges.
於一實施例中,第二電晶體還耦接驅動電路並接收驅動電路所提供之資料訊號,當第二電晶體受控於切換訊號而導通時,第二電晶體輸出資料訊號至第一資料線。In one embodiment, the second transistor is also coupled to the drive circuit and receives the data signal provided by the drive circuit. When the second transistor is turned on under the control of the switching signal, the second transistor outputs the data signal to the first data String.
於一實施例中,發光二極體顯示面板還包括第三電晶體,設置於有效顯示區域之外,第三電晶體耦接於第一資料線與驅動電路之間且第三電晶體之閘極受控於參考訊號。In one embodiment, the light emitting diode display panel further includes a third transistor disposed outside the effective display area, the third transistor is coupled between the first data line and the driving circuit and the gate of the third transistor Extremely controlled by the reference signal.
於一實施例中,當第三電晶體受控於參考訊號而導通時,第三電晶體檢測第一資料線之電流並輸出回饋訊號至驅動電路,以作為補償之參考。In one embodiment, when the third transistor is controlled by the reference signal and is turned on, the third transistor detects the current of the first data line and outputs a feedback signal to the driving circuit as a reference for compensation.
於一實施例中,當第一電晶體受控於驅動訊號而導通時,通過第一電晶體的電流驅動發光二極體發光。In one embodiment, when the first transistor is controlled by the driving signal and is turned on, the current through the first transistor drives the light-emitting diode to emit light.
於一實施例中,發光二極體顯示面板還包括另一第二電晶體,設置於有效顯示區域之外,該另一第二電晶體耦接該複數條資料線中之第二資料線且該另一第二電晶體之閘極受控於另一切換訊號。In one embodiment, the light emitting diode display panel further includes another second transistor disposed outside the effective display area, the other second transistor is coupled to the second data line of the plurality of data lines and The gate of the other second transistor is controlled by another switching signal.
於一實施例中,複數個畫素中之第三畫素及第四畫素均耦接第二資料線並透過第二資料線共用該另一第二電晶體。In one embodiment, the third pixel and the fourth pixel of the plurality of pixels are both coupled to the second data line and share the other second transistor through the second data line.
相較於先前技術,本發明之發光二極體顯示面板的畫素設計係採用「1T1C」架構或「1T」架構,而非傳統的「2T1C」架構,亦即每一畫素包括第一電晶體及儲存電容或僅包括第一電晶體,且於有效顯示區域之外共用第二電晶體,因此其電路佈局較為容易,即使在畫素密度提高的情況下,其電路佈局難度不易受限於各元件及走線而大幅增加,故可適用於高解析度之面板設計。Compared with the prior art, the pixel design of the LED display panel of the present invention adopts the "1T1C" architecture or the "1T" architecture instead of the traditional "2T1C" architecture, that is, each pixel includes the first electrical The crystal and storage capacitor may only include the first transistor, and share the second transistor outside the effective display area. Therefore, the circuit layout is relatively easy. Even when the pixel density is increased, the circuit layout difficulty is not easily limited by The number of components and traces has been greatly increased, so it is suitable for high-resolution panel design.
此外,由於本發明之發光二極體顯示面板係採用脈衝驅動模式(Impulse driving mode)對所有畫素分區驅動,其所需電流較傳統的電壓保持模式(Holding-type)來得低,故可有效減少發光二極體顯示面板的總功耗,並可在驅動電路與第二電晶體之間設置多工器來減少所需驅動電路之數量。In addition, since the light-emitting diode display panel of the present invention adopts the impulse driving mode (Impulse driving mode) to drive all the pixel partitions, the required current is lower than the traditional holding-type mode (Holding-type), so it is effective The total power consumption of the light-emitting diode display panel is reduced, and a multiplexer can be arranged between the driving circuit and the second transistor to reduce the number of required driving circuits.
關於本發明之優點與精神可以藉由以下的發明詳述及所附圖式得到進一步的瞭解。The advantages and spirit of the present invention can be further understood from the following detailed description of the invention and the accompanying drawings.
在下文中將參照附圖更全面地描述本發明,在附圖中示出了本發明的示例性實施例。如本領域技術人員將認識到的,可以以各種不同的方式修改所描述的實施例,而不脫離本發明的精神或範圍。Hereinafter, the present invention will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the present invention are shown. As those skilled in the art would realize, the described embodiments may be modified in various different ways without departing from the spirit or scope of the present invention.
在附圖中,為了清楚起見,放大了部份區域。在整個說明書中,相同的附圖標記表示相同的元件。應當理解,當諸如區域或基板的元件被稱為在另一元件“上”或者“連接(或稱為耦接)”又或者“電性連接”另一元件時,其可以直接在另一元件上或與另一元件連接(或稱為耦接)或電性連接,或者中間元件可以也存在。相反,當元件被稱為“直接在另一元件上”或“直接連接到”另一元件時,不存在中間元件。如本文所使用的,“連接(或稱為耦接)”可以指物理及/或電連接。In the drawings, some areas are enlarged for clarity. Throughout the specification, the same reference numerals denote the same elements. It should be understood that when an element such as a region or a substrate is referred to as being "on" or "connected (or referred to as coupled)" or "electrically connected" to another element, it may be directly connected to the other element. It is connected to or electrically connected to another element (or referred to as being coupled) or electrically connected, or intermediate elements may also exist. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. As used herein, "connected (or referred to as coupled)" can refer to physical and/or electrical connections.
根據本發明之一具體實施例為一種發光二極體顯示面板。請參照圖3,圖3係繪示此實施例中之發光二極體顯示面板的示意圖。A specific embodiment according to the present invention is a light emitting diode display panel. Please refer to FIG. 3, which is a schematic diagram of the light-emitting diode display panel in this embodiment.
如圖3所示,發光二極體顯示面板3包括複數條資料線DL(i-1)~DL(i)、複數條閘極線GL(N-1)~GL(N)、複數個畫素PX1~PX4及複數個第二電晶體T2,其中i與N均為正整數。需說明的是,此實施例中雖以兩條資料線、兩條閘極線、四個畫素及兩個第二電晶體為例進行說明,但本發明並不以此為限。As shown in FIG. 3, the light-emitting diode display panel 3 includes a plurality of data lines DL(i-1)~DL(i), a plurality of gate lines GL(N-1)~GL(N), and a plurality of pictures. PX1~PX4 and a plurality of second transistors T2, where i and N are both positive integers. It should be noted that although two data lines, two gate lines, four pixels, and two second transistors are taken as examples for description in this embodiment, the present invention is not limited to this.
發光二極體顯示面板3包括有效顯示區域AA。該複數個畫素PX1~PX4係設置於發光二極體顯示面板3之有效顯示區域AA內且該複數個第二電晶體T2係設置於發光二極體顯示面板3之有效顯示區域AA之外。The light emitting diode display panel 3 includes an effective display area AA. The plurality of pixels PX1~PX4 are arranged in the effective display area AA of the light-emitting diode display panel 3 and the plurality of second transistors T2 are arranged outside the effective display area AA of the light-emitting diode display panel 3 .
該複數條資料線DL(i-1)~DL(i)中之第一資料線DL(i-1)耦接該複數個畫素PX1~PX4中之第一畫素PX1及第二畫素PX2以及該複數個第二電晶體T2中之一第二電晶體T2;該複數條資料線DL(i-1)~DL(i)中之第二資料線DL(i)耦接該複數個畫素PX1~PX4中之第三畫素PX3及第四畫素PX4以及該複數個第二電晶體T2中之另一第二電晶體T2;該複數條閘極線GL(N-1)~GL(N)中之第一閘極線GL(N-1)耦接該複數個畫素PX1~PX4中之第一畫素PX1及第三畫素PX3;該複數條閘極線GL(N-1)~GL(N)中之第二閘極線GL(N)耦接該複數個畫素PX1~PX4中之第二畫素PX2及第四畫素PX4。The first data line DL(i-1) of the plurality of data lines DL(i-1)~DL(i) is coupled to the first pixel PX1 and the second pixel of the plurality of pixels PX1~PX4 PX2 and a second transistor T2 of the plurality of second transistors T2; the second data line DL(i) of the plurality of data lines DL(i-1)~DL(i) is coupled to the plurality of data lines DL(i-1)~DL(i) The third pixel PX3 and the fourth pixel PX4 among the pixels PX1~PX4 and the other second transistor T2 among the plurality of second transistors T2; the plurality of gate lines GL(N-1)~ The first gate line GL(N-1) in GL(N) is coupled to the first pixel PX1 and the third pixel PX3 of the plurality of pixels PX1~PX4; the plurality of gate lines GL(N -1) The second gate line GL(N) in ~GL(N) is coupled to the second pixel PX2 and the fourth pixel PX4 of the plurality of pixels PX1~PX4.
也就是說,該複數個畫素PX1~PX4中之第一畫素PX1分別耦接該複數條資料線DL(i-1)~DL(i)中之第一資料線DL(i-1)及該複數條閘極線GL(N-1)~GL(N)中之第一閘極線GL(N-1);該複數個畫素PX1~PX4中之第二畫素PX2分別耦接該複數條資料線DL(i-1)~DL(i)中之第一資料線DL(i-1)及該複數條閘極線GL(N-1)~GL(N)中之第二閘極線GL(N);該複數個畫素PX1~PX4中之第三畫素PX3分別耦接該複數條資料線DL(i-1)~DL(i)中之第二資料線DL(i)及該複數條閘極線GL(N-1)~GL(N)中之第一閘極線GL(N-1);該複數個畫素PX1~PX4中之第四畫素PX4分別耦接該複數條資料線DL(i-1)~DL(i)中之第二資料線DL(i)及該複數條閘極線GL(N-1)~GL(N)中之第二閘極線GL(N)。該複數個畫素PX1~PX4中之第一畫素PX1及第二畫素PX2共用第一資料線DL(i-1)耦接的第二電晶體T2;該複數個畫素PX1~PX4中之第三畫素PX3及第四畫素PX4共用第二資料線DL(i)耦接的第二電晶體T2。That is, the first pixel PX1 of the plurality of pixels PX1~PX4 is respectively coupled to the first data line DL(i-1) of the plurality of data lines DL(i-1)~DL(i) And the first gate line GL(N-1) of the plurality of gate lines GL(N-1)~GL(N); the second pixel PX2 of the plurality of pixels PX1~PX4 is respectively coupled The first data line DL(i-1) among the plurality of data lines DL(i-1)~DL(i) and the second among the plurality of gate lines GL(N-1)~GL(N) Gate line GL(N); the third pixel PX3 of the plurality of pixels PX1~PX4 is respectively coupled to the second data line DL( of the plurality of data lines DL(i-1)~DL(i) i) and the first gate line GL(N-1) among the plurality of gate lines GL(N-1)~GL(N); the fourth pixel PX4 among the plurality of pixels PX1~PX4 respectively Coupled to the second data line DL(i) of the plurality of data lines DL(i-1)~DL(i) and the second of the plurality of gate lines GL(N-1)~GL(N) Gate line GL(N). The first pixel PX1 and the second pixel PX2 of the plurality of pixels PX1~PX4 share the second transistor T2 coupled to the first data line DL(i-1); among the plurality of pixels PX1~PX4 The third pixel PX3 and the fourth pixel PX4 share the second transistor T2 coupled to the second data line DL(i).
於此實施例中,該複數個畫素PX1~PX4均採用「1T1C」架構的畫素設計,亦即每一畫素PX1~PX4均包括一個電晶體及一個電容。In this embodiment, the plurality of pixels PX1 to PX4 all adopt a pixel design of the "1T1C" architecture, that is, each pixel PX1 to PX4 includes a transistor and a capacitor.
若以第一畫素PX1為例,第一畫素PX1包括發光二極體LED、第一電晶體T1及儲存電容CS。發光二極體LED耦接至接地電壓VSS。第一電晶體T1耦接於該複數條資料線DL(i-1)~DL(i)中之第一資料線DL(i-1)與發光二極體LED之間。第一電晶體T1之閘極耦接該複數條閘極線GL(N-1)~GL(N)中之第一閘極線GL(N-1)並受控於第一閘極線GL(N-1)所提供之驅動訊號S(N-1)。儲存電容CS之一端耦接第一資料線DL(i-1)且儲存電容CS之另一端耦接至發光二極體LED與接地電壓VSS之間,用以儲存電荷。Taking the first pixel PX1 as an example, the first pixel PX1 includes a light emitting diode LED, a first transistor T1 and a storage capacitor CS. The light emitting diode LED is coupled to the ground voltage VSS. The first transistor T1 is coupled between the first data line DL(i-1) among the plurality of data lines DL(i-1)~DL(i) and the light emitting diode LED. The gate of the first transistor T1 is coupled to the first gate line GL(N-1) among the plurality of gate lines GL(N-1)~GL(N) and controlled by the first gate line GL (N-1) The drive signal S(N-1) provided. One end of the storage capacitor CS is coupled to the first data line DL(i-1) and the other end of the storage capacitor CS is coupled between the light emitting diode LED and the ground voltage VSS for storing charges.
同理,若以第二畫素PX2為例,第二畫素PX2亦包括發光二極體LED、第一電晶體T1及儲存電容CS。發光二極體LED耦接至接地電壓VSS。第一電晶體T1耦接於該複數條資料線DL(i-1)~DL(i)中之第一資料線DL(i-1)與發光二極體LED之間。第一電晶體T1之閘極耦接該複數條閘極線GL(N-1)~GL(N)中之第二閘極線GL(N)並受控於第二閘極線GL(N)所提供之驅動訊號S(N)。儲存電容CS之一端耦接第一資料線DL(i-1)且儲存電容CS之另一端耦接至發光二極體LED與接地電壓VSS之間,用以儲存電荷。Similarly, if the second pixel PX2 is taken as an example, the second pixel PX2 also includes a light emitting diode LED, a first transistor T1 and a storage capacitor CS. The light emitting diode LED is coupled to the ground voltage VSS. The first transistor T1 is coupled between the first data line DL(i-1) among the plurality of data lines DL(i-1)~DL(i) and the light emitting diode LED. The gate of the first transistor T1 is coupled to the second gate line GL(N) among the plurality of gate lines GL(N-1)~GL(N) and is controlled by the second gate line GL(N) ) The drive signal S(N) provided. One end of the storage capacitor CS is coupled to the first data line DL(i-1) and the other end of the storage capacitor CS is coupled between the light emitting diode LED and the ground voltage VSS for storing charges.
同理,若以第三畫素PX3為例,第三畫素PX3亦包括發光二極體LED、第一電晶體T1及儲存電容CS。發光二極體LED耦接至接地電壓VSS。第一電晶體T1耦接於該複數條資料線DL(i-1)~DL(i)中之第二資料線DL(i)與發光二極體LED之間。第一電晶體T1之閘極耦接該複數條閘極線GL(N-1)~GL(N)中之第一閘極線GL(N-1)並受控於第一閘極線GL(N-1)所提供之驅動訊號S(N-1)。儲存電容CS之一端耦接第二資料線DL(i)且儲存電容CS之另一端耦接至發光二極體LED與接地電壓VSS之間,用以儲存電荷。Similarly, if the third pixel PX3 is taken as an example, the third pixel PX3 also includes a light emitting diode LED, a first transistor T1 and a storage capacitor CS. The light emitting diode LED is coupled to the ground voltage VSS. The first transistor T1 is coupled between the second data line DL(i) among the plurality of data lines DL(i-1)~DL(i) and the light emitting diode LED. The gate of the first transistor T1 is coupled to the first gate line GL(N-1) among the plurality of gate lines GL(N-1)~GL(N) and controlled by the first gate line GL (N-1) The drive signal S(N-1) provided. One end of the storage capacitor CS is coupled to the second data line DL(i) and the other end of the storage capacitor CS is coupled between the light emitting diode LED and the ground voltage VSS for storing charges.
同理,若以第四畫素PX4為例,第四畫素PX4亦包括發光二極體LED、第一電晶體T1及儲存電容CS。發光二極體LED耦接至接地電壓VSS。第一電晶體T1耦接於該複數條資料線DL(i-1)~DL(i)中之第二資料線DL(i)與發光二極體LED之間。第一電晶體T1之閘極耦接該複數條閘極線GL(N-1)~GL(N)中之第二閘極線GL(N)並受控於第二閘極線GL(N)所提供之驅動訊號S(N)。儲存電容CS之一端耦接第二資料線DL(i)且儲存電容CS之另一端耦接至發光二極體LED與接地電壓VSS之間,用以儲存電荷。Similarly, if the fourth pixel PX4 is taken as an example, the fourth pixel PX4 also includes a light-emitting diode LED, a first transistor T1 and a storage capacitor CS. The light emitting diode LED is coupled to the ground voltage VSS. The first transistor T1 is coupled between the second data line DL(i) among the plurality of data lines DL(i-1)~DL(i) and the light emitting diode LED. The gate of the first transistor T1 is coupled to the second gate line GL(N) among the plurality of gate lines GL(N-1)~GL(N) and is controlled by the second gate line GL(N) ) The drive signal S(N) provided. One end of the storage capacitor CS is coupled to the second data line DL(i) and the other end of the storage capacitor CS is coupled between the light emitting diode LED and the ground voltage VSS for storing charges.
耦接第一資料線DL(i-1)的第二電晶體T2亦耦接資料訊號VDAT且此第二電晶體T2的閘極受控於切換訊號SW(i-1);耦接第二資料線DL(i)的第二電晶體T2亦耦接資料訊號VDAT且此第二電晶體T2的閘極受控於切換訊號SW(i)。The second transistor T2 coupled to the first data line DL(i-1) is also coupled to the data signal VDAT and the gate of this second transistor T2 is controlled by the switching signal SW(i-1); coupled to the second The second transistor T2 of the data line DL(i) is also coupled to the data signal VDAT and the gate of this second transistor T2 is controlled by the switching signal SW(i).
於實際應用中,該複數個第二電晶體T2可透過多工器耦接驅動電路並接收驅動電路所提供之資料訊號VDAT,且多工器可以是一對二、一對三或其它設計,藉以減少驅動電路的數量,但不以此為限。In practical applications, the plurality of second transistors T2 can be coupled to the drive circuit through a multiplexer and receive the data signal VDAT provided by the drive circuit, and the multiplexer can be one-to-two, one-to-three or other designs. In order to reduce the number of driving circuits, but not limited to this.
請同時參照圖3及圖4。若以第一畫素PX1為例,當切換訊號SW(i-1)由低位準VGL變為高位準VGH時,另一切換訊號SW(i)仍維持低位準VGL,受控於切換訊號SW(i-1)的第二電晶體T2會導通,藉以透過第一資料線DL(i-1)分別對第一畫素PX1及第二畫素PX2中之儲存電容CS充電。於切換訊號SW(i-1)由高位準VGH變回低位準VGL之後,當另一切換訊號SW(i)由低位準VGL變為高位準VGH時,受控於切換訊號SW(i)的第二電晶體T2會導通,藉以透過第二資料線DL(i)分別對第三畫素PX3及第四畫素PX4中之儲存電容CS充電。 Please refer to Figure 3 and Figure 4 at the same time. Taking the first pixel PX1 as an example, when the switching signal SW(i-1) changes from a low level VGL to a high level VGH, the other switching signal SW(i) still maintains a low level VGL and is controlled by the switching signal SW The second transistor T2 of (i-1) is turned on to charge the storage capacitor CS in the first pixel PX1 and the second pixel PX2 through the first data line DL(i-1). After the switching signal SW(i-1) changes from the high level VGH to the low level VGL, when another switching signal SW(i) changes from the low level VGL to the high level VGH, it is controlled by the switching signal SW(i) The second transistor T2 is turned on to charge the storage capacitor CS in the third pixel PX3 and the fourth pixel PX4 through the second data line DL(i).
接著,當原本一直維持於低位準VGL的驅動訊號S(N-1)變為高位準VGH時,第一畫素PX1中之受控於驅動訊號S(N-1)的第一電晶體T1會導通,使得儲存於第一畫素PX1及第二畫素PX2中之儲存電容CS的電荷流向第一畫素PX1中之第一電晶體T1而形成通過第一電晶體T1的電流I,以驅動第一畫素PX1中之發光二極體LED發光。因此,對第一畫素PX1而言,驅動訊號S(N-1)處於高位準VGH的這段期間可稱為「發光期間LEP」。 Then, when the driving signal S(N-1) that was originally maintained at the low level VGL changes to the high level VGH, the first transistor T1 in the first pixel PX1 controlled by the driving signal S(N-1) Will be turned on, so that the charge stored in the storage capacitor CS in the first pixel PX1 and the second pixel PX2 flows to the first transistor T1 in the first pixel PX1 to form a current I through the first transistor T1, Drive the light-emitting diode LED in the first pixel PX1 to emit light. Therefore, for the first pixel PX1, the period during which the driving signal S(N-1) is at the high level VGH can be referred to as the "light emitting period LEP".
同理,對第三畫素PX3而言,當驅動訊號S(N-1)處於高位準VGH時,第三畫素PX3中之受控於驅動訊號S(N-1)的第一電晶體T1亦會導通,使得儲存於第三畫素PX3及第四畫素PX4中之儲存電容CS的電荷流向第三畫素PX3中之第一電晶體T1而形成通過第一電晶體T1的電流I,以驅動第三畫素PX3中之發光二極體LED發光。因此,對第三畫素PX3而言,驅動訊號S(N-1)處於高位準VGH的這段期間亦可稱為「發光期間LEP」。 Similarly, for the third pixel PX3, when the driving signal S(N-1) is at the high level VGH, the first transistor in the third pixel PX3 is controlled by the driving signal S(N-1) T1 will also be turned on, so that the charge stored in the storage capacitor CS in the third pixel PX3 and the fourth pixel PX4 flows to the first transistor T1 in the third pixel PX3 to form a current I through the first transistor T1 , To drive the light-emitting diode LED in the third pixel PX3 to emit light. Therefore, for the third pixel PX3, the period during which the driving signal S(N-1) is at the high level VGH can also be referred to as the "light emitting period LEP".
類似地,對第二畫素PX2而言,當驅動訊號S(N)處於高位準VGH時,第二畫素PX2中之受控於驅動訊號S(N)的第一電晶體T1亦會導通, 使得儲存於第一畫素PX1及第二畫素PX2中之儲存電容CS的電荷流向第二畫素PX2中之第一電晶體T1而形成通過第一電晶體T1的電流I,以驅動第二畫素PX2中之發光二極體LED發光。因此,對第二畫素PX2而言,驅動訊號S(N)處於高位準VGH的這段期間亦可稱為「發光期間LEP」。 Similarly, for the second pixel PX2, when the driving signal S(N) is at the high level VGH, the first transistor T1 in the second pixel PX2 controlled by the driving signal S(N) will also be turned on , The charge stored in the storage capacitor CS in the first pixel PX1 and the second pixel PX2 flows to the first transistor T1 in the second pixel PX2 to form a current I through the first transistor T1 to drive the second pixel. The light-emitting diode LED in the pixel PX2 emits light. Therefore, for the second pixel PX2, the period during which the driving signal S(N) is at the high level VGH can also be referred to as the "light emitting period LEP".
同理,對第四畫素PX4而言,當驅動訊號S(N)處於高位準VGH時,第四畫素PX4中之受控於驅動訊號S(N)的第一電晶體T1亦會導通,使得儲存於第三畫素PX3及第四畫素PX4中之儲存電容CS的電荷流向第四畫素PX4中之第一電晶體T1而形成通過第一電晶體T1的電流I,以驅動第四畫素PX4中之發光二極體LED發光。因此,對第四畫素PX4而言,驅動訊號S(N)處於高位準VGH的這段期間亦可稱為「發光期間LEP」。 Similarly, for the fourth pixel PX4, when the driving signal S(N) is at the high level VGH, the first transistor T1 in the fourth pixel PX4 controlled by the driving signal S(N) will also be turned on , So that the charge stored in the storage capacitor CS in the third pixel PX3 and the fourth pixel PX4 flows to the first transistor T1 in the fourth pixel PX4 to form a current I passing through the first transistor T1 to drive the first transistor T1 The light-emitting diode LED in the four-pixel PX4 emits light. Therefore, for the fourth pixel PX4, the period during which the driving signal S(N) is at the high level VGH can also be referred to as the "light emitting period LEP".
於另一具體實施例中,請參照圖5,發光二極體顯示面板5中之該複數個畫素PX1~PX4均採用「1T」架構的畫素設計,亦即發光二極體顯示面板5中之每一畫素PX1~PX4均包括第一電晶體T1,但並未包括前一實施例中之儲存電容CS。 In another specific embodiment, please refer to FIG. 5, the plurality of pixels PX1~PX4 in the light-emitting diode display panel 5 all adopt the pixel design of the "1T" architecture, that is, the light-emitting diode display panel 5 Each of the pixels PX1 to PX4 includes the first transistor T1, but does not include the storage capacitor CS in the previous embodiment.
請同時參照圖5及圖6。若以第一畫素PX1為例,當切換訊號SW(i-1)由低位準VGL變為高位準VGH時,另一切換訊號SW(i)仍維持低位準VGL,受控於切換訊號SW(i-1)的第二電晶體T2會導通,此時,透過第一資料線DL(i-1)所傳送的電荷可儲存於耦合電容CC,例如第一資料線DL(i-1)與第一閘極線GL(N-1)之間的耦合電容CC以及第一資料線DL(i-1)與第二閘極線GL(N)之間的耦合電容CC,但不以此為限。實際上,耦合電容CC亦可以是其它與第一資料線DL(i-1)耦合的電容,但不以此為限。 Please refer to Figure 5 and Figure 6 at the same time. Taking the first pixel PX1 as an example, when the switching signal SW(i-1) changes from a low level VGL to a high level VGH, the other switching signal SW(i) still maintains a low level VGL and is controlled by the switching signal SW The second transistor T2 of (i-1) will be turned on. At this time, the charge transferred through the first data line DL(i-1) can be stored in the coupling capacitor CC, such as the first data line DL(i-1) The coupling capacitor CC between the first gate line GL(N-1) and the coupling capacitor CC between the first data line DL(i-1) and the second gate line GL(N), but not Is limited. In fact, the coupling capacitor CC can also be other capacitors coupled to the first data line DL(i-1), but it is not limited to this.
於切換訊號SW(i-1)由高位準VGH變回低位準VGL之後,當另一切換訊號SW(i)由低位準VGL變為高位準VGH時,受控於切換訊號SW(i)的第二電晶體T2會導通,此時,透過第二資料線DL(i)所傳送的電荷可儲存於耦合電容CC,例如第二資料線DL(i)與第一閘極線GL(N-1)之間的耦合電容CC以及第二資料線DL(i)與第二閘極線GL(N)之間的耦合電容CC,但不以此為限。實際上,耦合電容CC亦可以是其它與第二資料線DL(i)耦合的電容,但不以此為限。After the switching signal SW(i-1) changes from the high level VGH to the low level VGL, when another switching signal SW(i) changes from the low level VGL to the high level VGH, it is controlled by the switching signal SW(i) The second transistor T2 will be turned on. At this time, the charge transferred through the second data line DL(i) can be stored in the coupling capacitor CC, such as the second data line DL(i) and the first gate line GL(N- 1) The coupling capacitor CC between the second data line DL(i) and the second gate line GL(N), but not limited to this. In fact, the coupling capacitor CC can also be other capacitors coupled to the second data line DL(i), but it is not limited to this.
接著,當原本一直維持於低位準VGL的驅動訊號S(N-1)變為高位準VGH時,第一畫素PX1中之受控於驅動訊號S(N-1)的第一電晶體T1會導通,使得儲存於第一資料線DL(i-1)與第一閘極線GL(N-1)之間的耦合電容CC以及第一資料線DL(i-1)與第二閘極線GL(N)之間的耦合電容CC的電荷流向第一畫素PX1中之第一電晶體T1而形成通過第一電晶體T1的電流I,以驅動第一畫素PX1中之發光二極體LED發光。因此,對第一畫素PX1而言,驅動訊號S(N-1)處於高位準VGH的這段期間可稱為「發光期間LEP」。Then, when the driving signal S(N-1) that was originally maintained at the low level VGL changes to the high level VGH, the first transistor T1 in the first pixel PX1 controlled by the driving signal S(N-1) Will be turned on, so that the coupling capacitor CC stored between the first data line DL(i-1) and the first gate line GL(N-1) and the first data line DL(i-1) and the second gate The charge of the coupling capacitor CC between the lines GL(N) flows to the first transistor T1 in the first pixel PX1 to form a current I through the first transistor T1 to drive the light-emitting diode in the first pixel PX1 The body LED emits light. Therefore, for the first pixel PX1, the period during which the driving signal S(N-1) is at the high level VGH can be referred to as the "light emitting period LEP".
同理,對第三畫素PX3而言,當驅動訊號S(N-1)處於高位準VGH時,第三畫素PX3中之受控於驅動訊號S(N-1)的第一電晶體T1亦會導通,使得儲存於第二資料線DL(i)與第一閘極線GL(N-1)之間的耦合電容CC以及第二資料線DL(i)與第二閘極線GL(N)之間的耦合電容CC的電荷流向第三畫素PX3中之第一電晶體T1而形成通過第一電晶體T1的電流I,以驅動第三畫素PX3中之發光二極體LED發光。因此,對第三畫素PX3而言,驅動訊號S(N-1)處於高位準VGH的這段期間亦可稱為「發光期間LEP」。Similarly, for the third pixel PX3, when the driving signal S(N-1) is at the high level VGH, the first transistor in the third pixel PX3 is controlled by the driving signal S(N-1) T1 will also be turned on, so that the coupling capacitor CC stored between the second data line DL(i) and the first gate line GL(N-1) and the second data line DL(i) and the second gate line GL The charge of the coupling capacitor CC between (N) flows to the first transistor T1 in the third pixel PX3 to form a current I through the first transistor T1 to drive the light-emitting diode LED in the third pixel PX3 Glow. Therefore, for the third pixel PX3, the period during which the driving signal S(N-1) is at the high level VGH can also be referred to as the "light emitting period LEP".
類似地,對第二畫素PX2而言,當驅動訊號S(N)處於高位準VGH時,第二畫素PX2中之受控於驅動訊號S(N)的第一電晶體T1亦會導通,使得儲存於第一資料線DL(i-1)與第一閘極線GL(N-1)之間的耦合電容CC以及第一資料線DL(i-1)與第二閘極線GL(N)之間的耦合電容CC的電荷流向第二畫素PX2中之第一電晶體T1而形成通過第一電晶體T1的電流I,以驅動第二畫素PX2中之發光二極體LED發光。因此,對第二畫素PX2而言,驅動訊號S(N)處於高位準VGH的這段期間亦可稱為「發光期間LEP」。Similarly, for the second pixel PX2, when the driving signal S(N) is at the high level VGH, the first transistor T1 in the second pixel PX2 controlled by the driving signal S(N) will also be turned on , So that the coupling capacitor CC stored between the first data line DL(i-1) and the first gate line GL(N-1) and the first data line DL(i-1) and the second gate line GL The charge of the coupling capacitor CC between (N) flows to the first transistor T1 in the second pixel PX2 to form a current I through the first transistor T1 to drive the light-emitting diode LED in the second pixel PX2 Glow. Therefore, for the second pixel PX2, the period during which the driving signal S(N) is at the high level VGH can also be referred to as the "light emitting period LEP".
同理,對第四畫素PX4而言,當驅動訊號S(N)處於高位準VGH時,第四畫素PX4中之受控於驅動訊號S(N)的第一電晶體T1亦會導通,使得儲存於第二資料線DL(i)與第一閘極線GL(N-1)之間的耦合電容CC以及第二資料線DL(i)與第二閘極線GL(N)之間的耦合電容CC的電荷流向第四畫素PX4中之第一電晶體T1而形成通過第一電晶體T1的電流I,以驅動第四畫素PX4中之發光二極體LED發光。因此,對第四畫素PX4而言,驅動訊號S(N)處於高位準VGH的這段期間亦可稱為「發光期間LEP」。Similarly, for the fourth pixel PX4, when the driving signal S(N) is at the high level VGH, the first transistor T1 in the fourth pixel PX4 controlled by the driving signal S(N) will also be turned on , So that the coupling capacitor CC stored between the second data line DL(i) and the first gate line GL(N-1) and the second data line DL(i) and the second gate line GL(N) The charge of the coupling capacitor CC flows to the first transistor T1 in the fourth pixel PX4 to form a current I through the first transistor T1 to drive the light-emitting diode LED in the fourth pixel PX4 to emit light. Therefore, for the fourth pixel PX4, the period during which the driving signal S(N) is at the high level VGH can also be referred to as the "light emitting period LEP".
於另一具體實施例中,請參照圖7,發光二極體顯示面板7中之該複數個畫素PX1~PX4與圖3的發光二極體顯示面板3中之該複數個畫素PX1~PX4一樣均採用「1T1C」架構的畫素設計,亦即發光二極體顯示面板7中之每一畫素PX1~PX4均包括第一電晶體T1及儲存電容CS。In another specific embodiment, please refer to FIG. 7, the plurality of pixels PX1~PX4 in the light-emitting
需說明的是,圖7的發光二極體顯示面板7與圖3的發光二極體顯示面板3不同之處在於:圖7的發光二極體顯示面板7還在有效顯示區域AA週邊設計補償迴路,例如圖7的發光二極體顯示面板7還包括設置於有效顯示區域AA之外的複數個第三電晶體T3。It should be noted that the difference between the
如圖7所示,發光二極體顯示面板7所包括的該複數個第三電晶體T3中之一第三電晶體T3係耦接於第一資料線DL(i-1)與驅動電路IC之間且此第三電晶體T3之閘極受控於參考訊號VREF;該複數個第三電晶體T3中之另一第三電晶體T3係耦接於第二資料線DL(i)與驅動電路IC之間且此第三電晶體T3之閘極亦受控於參考訊號VREF。As shown in FIG. 7, one of the plurality of third transistors T3 included in the light emitting
亦請同時參照圖7及圖8。在切換訊號SW(i-1)處於高位準VGH而對第一資料線DL(i-1)充電的期間,當參考訊號VREF由低位準VGL變為高位準VGH時,耦接第一資料線DL(i-1)的第三電晶體T3受控於參考訊號VREF而導通,藉以檢測第一資料線DL(i-1)之電流並輸出回饋訊號至驅動電路IC,以作為驅動電路IC進行補償之參考。Please also refer to Figure 7 and Figure 8 at the same time. While the switching signal SW(i-1) is at the high level VGH and the first data line DL(i-1) is charged, when the reference signal VREF changes from the low level VGL to the high level VGH, the first data line is coupled The third transistor T3 of DL(i-1) is controlled by the reference signal VREF and turned on, so as to detect the current of the first data line DL(i-1) and output the feedback signal to the driving circuit IC to perform as the driving circuit IC. Reference for compensation.
同理,在切換訊號SW(i)處於高位準VGH而對第二資料線DL(i)充電的期間,當參考訊號VREF由低位準VGL變為高位準VGH時,耦接第二資料線DL(i)的第三電晶體T3受控於參考訊號VREF而導通,藉以檢測第二資料線DL(i)之電流並輸出回饋訊號至驅動電路IC,以作為驅動電路IC進行補償之參考。Similarly, when the switching signal SW(i) is at the high level VGH and the second data line DL(i) is charged, when the reference signal VREF changes from the low level VGL to the high level VGH, the second data line DL is coupled The third transistor T3 of (i) is controlled by the reference signal VREF and turned on, so as to detect the current of the second data line DL(i) and output a feedback signal to the driving circuit IC as a reference for the compensation of the driving circuit IC.
相較於先前技術,本發明之發光二極體顯示面板的畫素設計係採用「1T1C」架構或「1T」架構,而非傳統的「2T1C」架構,亦即每一畫素包括第一電晶體及儲存電容或僅包括第一電晶體,且於有效顯示區域之外共用第二電晶體,因此其電路佈局較為容易,即使在畫素密度提高的情況下,其電路佈局難度不易受限於各元件及走線而大幅增加,故可適用於高解析度之面板設計。Compared with the prior art, the pixel design of the LED display panel of the present invention adopts the "1T1C" architecture or the "1T" architecture instead of the traditional "2T1C" architecture, that is, each pixel includes the first electrical The crystal and storage capacitor may only include the first transistor, and share the second transistor outside the effective display area. Therefore, the circuit layout is relatively easy. Even when the pixel density is increased, the circuit layout difficulty is not easily limited by The number of components and traces has been greatly increased, so it is suitable for high-resolution panel design.
此外,由於本發明之發光二極體顯示面板係採用脈衝驅動模式(Impulse driving mode)對所有畫素分區驅動,其所需電流較傳統的電壓保持模式(Holding-type)來得低,故可有效減少發光二極體顯示面板的總功耗,並可在驅動電路與第二電晶體之間設置多工器來減少所需驅動電路之數量。In addition, since the light-emitting diode display panel of the present invention adopts the impulse driving mode (Impulse driving mode) to drive all the pixel partitions, the required current is lower than the traditional holding-type mode (Holding-type), so it is effective The total power consumption of the light-emitting diode display panel is reduced, and a multiplexer can be arranged between the driving circuit and the second transistor to reduce the number of required driving circuits.
藉由以上較佳具體實施例之詳述,係希望能更加清楚描述本發明之特徵與精神,而並非以上述所揭露的較佳具體實施例來對本發明之範疇加以限制。相反地,其目的是希望能涵蓋各種改變及具相等性的安排於本發明所欲申請之專利範圍的範疇內。Through the detailed description of the above preferred embodiments, it is hoped that the characteristics and spirit of the present invention can be described more clearly, and the scope of the present invention is not limited by the preferred embodiments disclosed above. On the contrary, the purpose is to cover various changes and equivalent arrangements within the scope of the patent for which the present invention is intended.
1:畫素 VDD:工作電壓 VD:汲極電壓 VS:源極電壓 VG:閘極電壓 3、5、7:發光二極體顯示面板 AA:有效顯示區域 PX1~PX4:畫素 DL(i-1)~DL(i):資料線 GL(N-1)~GL(N):閘極線 S(N-1)~S(N+1):驅動訊號 SW(i-1)~SW(i):切換訊號 T1:第一電晶體 LED:發光二極體 CC:耦合電容 VSS:接地電壓 T2:第二電晶體 VDAT:資料訊號 CS:儲存電容 I:電流 VGH:高位準 VGL:低位準 LEP:發光期間 VREF:參考電壓 T3:第三電晶體 IC:驅動電路 1: Pixel VDD: working voltage VD: Drain voltage VS: source voltage VG: Gate voltage 3, 5, 7: LED display panel AA: effective display area PX1~PX4: pixel DL(i-1)~DL(i): data line GL(N-1)~GL(N): gate line S(N-1)~S(N+1): drive signal SW(i-1)~SW(i): switch signal T1: The first transistor LED: light emitting diode CC: Coupling capacitor VSS: Ground voltage T2: second transistor VDAT: Data signal CS: storage capacitor I: current VGH: High level VGL: Low level LEP: During light emission VREF: Reference voltage T3: third transistor IC: drive circuit
圖1係繪示目前常見的發光二極體顯示面板的畫素設計示意圖。FIG. 1 is a schematic diagram showing the pixel design of the current common light-emitting diode display panel.
圖2係繪示圖1中之第二電晶體的控制訊號的時序圖。FIG. 2 is a timing diagram of the control signal of the second transistor in FIG. 1.
圖3係繪示根據本發明之一具體實施例的發光二極體顯示面板的示意圖。FIG. 3 is a schematic diagram of a light emitting diode display panel according to a specific embodiment of the present invention.
圖4係繪示圖3中之切換訊號、資料訊號及驅動訊號的時序圖。FIG. 4 is a timing diagram of the switching signal, the data signal and the driving signal in FIG. 3.
圖5係繪示根據本發明之另一具體實施例的發光二極體顯示面板的示意圖。FIG. 5 is a schematic diagram of a light emitting diode display panel according to another embodiment of the present invention.
圖6係繪示圖5中之切換訊號、資料訊號及驅動訊號的時序圖。FIG. 6 is a timing diagram of the switching signal, the data signal and the driving signal in FIG. 5.
圖7係繪示根據本發明之又一具體實施例的發光二極體顯示面板的示意圖。FIG. 7 is a schematic diagram of a light-emitting diode display panel according to another embodiment of the present invention.
圖8係繪示圖7中之切換訊號、資料訊號、驅動訊號及參考電壓的時序圖。FIG. 8 is a timing diagram of the switching signal, the data signal, the driving signal and the reference voltage in FIG. 7.
5:發光二極體顯示面板 5: LED display panel
AA:有效顯示區域 AA: effective display area
PX1~PX4:畫素 PX1~PX4: pixel
DL(i-1)~DL(i):資料線 DL(i-1)~DL(i): data line
GL(N-1)~GL(N):閘極線 GL(N-1)~GL(N): gate line
S(N-1)~S(N):驅動訊號 S(N-1)~S(N): drive signal
SW(i-1)~SW(i):切換訊號 SW(i-1)~SW(i): switch signal
T1:第一電晶體 T1: The first transistor
LED:發光二極體 LED: light emitting diode
CC:耦合電容 CC: Coupling capacitor
VSS:接地電壓 VSS: Ground voltage
T2:第二電晶體 T2: second transistor
VDAT:資料訊號 VDAT: Data signal
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Also Published As
Publication number | Publication date |
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TW202036519A (en) | 2020-10-01 |
CN110767151A (en) | 2020-02-07 |
CN110767151B (en) | 2024-02-27 |
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