TWI413085B - Single-cell-gap type transfective liquid crystal display and driving method thereof - Google Patents

Abstract

The present invention relates to a signal-cell-gap type transfective liquid crystal display (TRLCD) and driving method therefore. A TFT panel of the TRLCD defines multiple pixel areas, each of which has a multiplexer. The multiplexer respectively supplies different voltages to a transmissive region and a reflective region of the corresponding pixel after receiving a modulated gate driving signal. Therefore, a VT curve of the transmissive region and a VR curve of the reflective region are identical.

Description

Single crystal hole gap type semi-transparent liquid crystal display and driving method thereof

The present invention relates to a transflective liquid crystal display, and more particularly to a single crystal hole gap type transflective liquid crystal display having the same transmittance of a reflective region and a transmissive region and a driving method thereof.

According to the electronic products that are used in different environments, the liquid crystal display is divided into transmissive, reflective and trans-transverse according to different light source environments, and the trans-transparent liquid crystal display is combined with the backlight module, but some display light sources are used. It depends on the ambient light. For electronic products that require high-end mobile display (such as mobile phones and digital cameras), they are often used outdoors because of their use. Therefore, most of these electronic products use semi-transparent LCDs as high-end mobile display requirements. A better solution for electronic products.

The following is a further explanation of the evolution of the driving principle and technology of the semi-transparent liquid crystal display.

First, referring to FIG. 1 , the early half-transflective liquid crystal display 10 includes a substrate (Substrate hereinafter referred to as an upper plate) 11 , a thin film transistor substrate (TFT Substrate hereinafter referred to as a lower plate) 12 , and a liquid crystal layer 13 interposed therebetween. The lower panel 12 defines a pixel area in which a plurality of pixels are arranged. Each pixel area includes a penetrating region 121 and a reflecting region 122. The reflective layer 122 is formed with a reflective layer 123 on the substrate of the lower plate 12. Therefore, after the external light penetrates from the upper plate 11 to the reflective layer 123, the reflective layer 123 is formed by the reflective layer 123. After being reflected, it is then ejected from the upper plate 11. Since the liquid crystal layer 13 is interposed between the upper plate 11 and the lower plate 12, the reflected external light can be used as a light source for display. As for the backlight source behind the lower plate 12, it directly passes through the penetrating region 121 and then passes through the liquid crystal layer 13 from the upper plate 11. Therefore, the so-called transflective liquid crystal display 10 effectively utilizes the backlight source and the external light source as display light sources. Compared with penetrating liquid crystal displays, high-power backlight sources are not used. In addition to power saving, it also helps to reduce the size of the overall electronic products.

However, the above-described transflective liquid crystal display 10 has a technical disadvantage of poor development quality due to the increase in the reflective layer due to the gray level inversion phenomenon. In the case of a single prime picture, since the external light enters the reflective area to be reflected to the upper plate 11, the optical path difference is twice that of the backlight source, resulting in gray scale inversion. Therefore, as shown in FIG. 2, in order to make the optical path difference of the penetration region 121 and the reflection region 122 coincide, the existing products on the market have adopted a so-called double cell gap pixel half-transflective liquid crystal display 10a. The feature is that an overcoat layer 124 is formed downward at the position corresponding to the reflective region 122 of the upper plate, so that the cell gap D2 of the reflective region 122 is about half of the interstitial space D1 of the penetrating region. In this way, the optical path difference between the transmission area 121 and the reflection area 122 is adjusted to be substantially equal. Please refer to FIG. 3 for the reflection area to have four different cell gaps (4.0 um / 2.2 um / 2.0 um / 1.8 um). The results of the analog voltage versus reflectance (hereinafter referred to as VR) curve are obtained. From this figure, it can be seen that the voltage versus the transmittance (hereinafter referred to as VT) curve of the hole gap of the penetration region (4.0 um) is the same as 4.0 um crystal. The VR curve of the hole gap is obviously affected by the double stroke difference and the penetration zone. The VT curve is obviously inconsistent. However, only the hole spacing D2 (2.0um) of the reflection area which is half the gap of the hole spacing D1 (4.0um) in the penetrating zone is closer to the VT curve of the penetrating zone, so the double crystal hole The gap pixel architecture does align the stroke of the backlight with the reflected light to improve the grayscale inversion. However, this double-cavity gap matrix structure also has other disadvantages, such as complex process, low yield and easy to produce liquid crystal leakage at the edge of the insulating bump 124, etc., and still can not effectively improve the imaging quality of the transflective liquid crystal display. .

In view of the problems arising from the above-mentioned double-cavity gap pixel structure, each panel factory returns to design a single cell gap pixel structure, but cooperates with another to reduce the reflection region voltage to achieve the adjustment of the reflection region. The VR area line is consistent with the VT curve of the penetration area to solve the gray scale inversion problem.

One of the above methods for reducing the voltage of the reflection region is a capacitive coupled type (CC), as shown in FIG. 4, which is a single pixel equivalent circuit diagram of the mode, and the pixel of the single thin film transistor TFT1 of the pixel The pole D is respectively connected to the storage capacitor C _ST , the penetration area storage capacitor C _CLC1 and the reflection area liquid crystal capacitor C _LC2 , wherein a coupling capacitor C _C is further added to the reflection region, and the coupling capacitor C _C and the reflective region liquid crystal capacitor are connected. C _{LC2 is} connected in series. Therefore, the reflected region voltage VR can be adjusted to be smaller than the voltage of the transmissive region V _{D by the} voltage division of the coupling capacitor C _C and the liquid crystal capacitor C _LC2 in series, and the voltages of the reflective region and the transmissive region are different. It can reduce the difference between the penetration rate of the penetration zone and the reflectance of the reflection zone, as shown in Figure 5. However, this capacitive coupling also has many fatal shortcomings, such as the following:

1. The liquid crystal inversion threshold voltage (Threshold Voltage) of the penetrating zone and the reflecting zone is still different from V _th1 , V _th2 , as shown in FIG. 5 , so the VT curve of the penetrating zone is still inconsistent with the reflecting zone VR curve.

2. The pixel electrode V _{R of the} reflection area is always in a floating state, and it is impossible to avoid the accumulation of electric charge, thereby causing image sticking.

Therefore, there is another way to solve the above disadvantages of the capacitive coupling type. Referring to FIG. 6, an additional common electrode line V _com2 and a compensation are added to each pixel in the above-mentioned electrically coupled infrastructure. capacitor C _2, the system compensation capacitor C ₂ is connected to the second common electrode line V _com2, thus the voltage variation of the second common electrode line V _com2 the coupling effect compensation capacitor C ₂ so that the reflective region and the transmissive region The liquid crystal inversion threshold voltages V _th1 and V _th2 are relatively close, as shown in FIG. However, the gray-scale inversion problem is also solved by adjusting the penetration region voltage V _D and the reflection region voltage V _R by the capacitance division principle. However, since the partial voltage of the reflection region is still a fixed value, only some technologies can be solved. There are still many problems in the development, such as the following:

1. The VT curve of the penetrating zone and the VT curve of the reflecting zone are still not exactly the same, as shown in Figure 7, especially in the case of high grayscale images, the difference of VT curves in the two regions is more significant.

2. The pixel electrode V _{R of the} reflection region also exhibits a floating state, and therefore there is still an image sticking phenomenon due to charge accumulation.

3. Since the second common electrode line V _COM2 is in a floating state, it is easy to have a horizontal cross-talk phenomenon.

In summary, at present, a transflective liquid crystal display using a single crystal aperture gap pixel structure still needs a better technical solution to overcome the gray scale inversion problem.

In view of the above-mentioned technical problems arising from the method of driving the voltage of the reflection-reducing region in the transflective liquid crystal display having the single crystal aperture gap structure, the main object of the present invention is to provide a path for ensuring the reflection region and the penetration region. The driving method of the transflective liquid crystal display having the same transmittance, and the present invention adopts the driving circuit, which has low cost, high yield, no image sticking and no horizontal cross-talk, etc. advantage.

The main technical hand used to achieve the above purpose is to enable the semi-transflective liquid crystal display driving method to add a multiplexer to each pixel of the lower panel, together with the modulated scanning signal and different voltage data signals, to separately control The voltage of the penetrating zone and the reflecting zone of each pixel is adjusted to be consistent with the VT curve and the VR curve of the penetrating zone and the reflecting zone.

Preferably, the design of the multiplexer used in the present invention comprises two types, one of which is formed in a penetrating region of each pixel to form a single thin film transistor, the gate of which is connected to the pixel scanning line, and then Forming two series connected thin film transistors in the reflective region, and the gates of the two series connected thin film transistors are respectively connected to the scanning line of the pixel and the next scanning line of the pixel; The modulation scan signal input to the pixel and the next pixel scan line can control the opening and closing sequence and the opening time of the penetration zone and the reflection zone. Since the opening and closing sequence and the opening time of the penetration zone and the reflection zone are different, That is, different voltage data can be written into the penetrating zone and the reflecting zone respectively. number. Therefore, the pixel reflection region voltage and the transmissive region voltage of the present invention can write data signals of different voltages when displaying the same gray scale, thereby realizing the adjustment of the VT curve and the VR curve of the penetration region and the reflection region. purpose.

Preferably, another multiplexer design method of the present invention is to form a plurality of sub-scanning lines on the lower plate to be staggered with the original complex scanning lines, so that each pixel has a scanning line and a sub-scanning line, and then A single thin film transistor gate in the reflection region and a single thin film transistor gate of the penetration region are respectively connected to the sub-scanning line and the scanning line of the pixel, and the modulated scanning signal sequentially sent to control the penetration region The opening and closing sequence and the opening time of the thin film transistor are different from those of the reflective region, and different voltage signals are written to the storage capacitors of the transmissive region and the reflective region. Therefore, the pixel reflection power and the penetration region voltage can write different data signals when displaying the same gray level, thereby achieving the purpose of adjusting the VT curve and the VR curve of the penetration region and the reflection region.

Referring to FIG. 8 , a transflective liquid crystal display 20 for a single crystal cavity gap of the present invention includes a half-transflective liquid crystal panel 21 , a timing controller 22 , a scan driving circuit 23 , a data driving circuit 24 , and a common The voltage generating circuit 25 and a gamma voltage generator 26.

The transflective liquid crystal panel 21 includes an upper plate (not shown) and a lower plate 211 with a liquid crystal layer (not shown) interposed therebetween, and the lower plate 211 is formed with a common electrode (V _com ). And a plurality of scanning lines (G ₁ to G _N ) and data lines D ₁ to D _M arranged in a horizontal and vertical staggered manner, wherein intersections of the scanning lines G ₁ to G _N and the data lines D ₁ to D _M are defined as one pixel 212 Further, please refer to FIG. 9 , which is a single pixel equivalent circuit diagram of the first preferred embodiment of the lower plate 211 of the present invention, which includes a penetration area A _T , a reflection area A _R and a multiplexer. The plurality of scanning lines G ₁ to G _N and the data lines D ₁ to D _{M of the} lower plate 211 are respectively connected to the scan driving circuit 23 and the data driving circuit 24, and the scanning driving circuit 23 periodically outputs the modulated scanning signals to the sequence. The plurality of scanning lines G ₁ to G _N , and the data driving circuit 24 outputs two sets of different voltage data signals to the data lines D _m corresponding to the pixels 212 for each pixel 212 to display gray scales (m is 1) One of ~M). Again, the common electrode (V _com ) is coupled to the common voltage generating circuit 25 to provide the same low voltage level for each pixel 212.

In the embodiment, the multiplexer of each pixel includes: a transmissive area thin film transistor TFT1 formed in the transmissive area A _T , and the drain D and the transmissive area storage capacitor C _ST1 and A penetrating region liquid crystal capacitor C _{LC1 is} connected, and a gate G is connected to the lower plate 211 of the present pixel scanning line G _n (n is one of 1 to N), and the source S is connected to the lower plate 211. Prime data line D _m .

A first reflective region thin film transistor TFT2, lines formed in the reflective region AR, a source S is connected to the lower plate lines 211 pixel data line D _m, while the gate is connected to the G pixels present scan line G _n.

a reflective region second thin film transistor TFT3 is formed in the reflective region A _R , the source S is connected to the drain D of the first thin film transistor TFT 2 of the reflective region, and the gate G is connected to the pixel The next pixel scan line G _n+1 , and the drain D is connected to a reflective area storage capacitor C _ST2 and a reflective area liquid crystal capacitor C _LC2 .

Please refer to FIG. 10 for the modulation scan signal and data signal waveform used in this embodiment. Since the first and second thin film transistors TFT2 of the reflective region, the gate G of the TFT3 is respectively connected to the pixel scan line G. _n and the next pixel scan line G _n+1 of the present pixel, so the waveform diagram reveals the previous scan line G _n-1 , the pixel scan line G _n and the next pixel scan line G _{n . +1} waveform. As can be seen from the waveform diagram, the scan signal outputted by the scan driving circuit 23 to each of the scanning lines G ₁ to G _{N has} a pulse length of 2H, wherein the 0H-0.5H time is the first high potential signal P1 and 1H-2H. a second high potential signal P2, and the scanning line G _n-front, the scanning signal line G _{n + 1} 1H holding time difference; is, this gate and the second region of the first reflective pixel thin film transistor TFT2, TFT3 G will be very The first scanning potential signal G _n is turned on during the first high potential P2 between 1H-1.5H and the first high potential P1 of the next scanning signal 0H-0.5H, and the 0.5H time difference is sent to the picture. The voltage data signal V _{R of the} data line is written into the storage capacitor C _ST2 of the reflection region; further, since the gate transistor G1 of the transmissive region is also connected to the pixel scanning line G _n , the penetration is The thin film transistor TFT1 of the region is turned on, so that the voltage information signal V _{R of the} corresponding reflection region is written to the transmissive region storage capacitor C _ST2 at 1H-1.5H of the scanning signal G _n . Write the corresponding transmissive area voltage data signal V _T to the transmissive area storage capacitor C _ST1 at 1.5H-2.0H to store the reflective area and the transmissive area. Capacitors C _ST1 , C _ST2 store different voltage values V _R , V _T that exhibit the same gray scale value; therefore, the VT curve and the VR curve of the adjustment penetration region and the reflection region are identical.

In the above embodiment, the modulated scan signal can be further obtained by the following method. Referring to FIG. 11 , the complex scan lines G ₁ G G _{N of the} lower plate 211 are divided into odd scan lines G ₁ according to the position sequence. G ₃ ... and even scanning lines G ₂ , G ₄ ... G _n , wherein the outgoing ends of the odd scanning lines G ₁ , G ₃ ... are formed on the left side of the lower plate 211 substrate, and the even scanning lines G _2, G ₄ ... G _n is the outlet end of the lower plate 211 is formed on the right side of the substrate, thus further increasing the scan driving circuit 23a, so that two scan driving circuits respectively connected 23,23a odd scan lines G ₁ , G ₃ ... and even scan lines G ₂ , G ₄ ... G _n . In addition, please refer to FIG. 12, together with a timing controller 22a that provides a first timing signal OE_L and a second timing signal OE_R, wherein the first timing signal OE_L and the second timing signal OE_R have the same frequency. The timing differs by 1H, with the pulse wave occupying 0.5H. The first and second timing signals are respectively output to the two scan driving circuits 23, 23a, so that the scan driving circuits 23, 23a adjust the scanning signals originally occupying the high potential of 1H to the 2H high-potential scanning signals G ₁ ', G ₂ ', G ₃ '.....G _n ', and then subtracted from the first and second timing signals OE_L, OE_R corresponding to the order, respectively, to obtain the modulated scanning signal G ₁ , G as shown in FIG. ₂ , G ₃ ..... G _n .

Furthermore, in this embodiment, since different voltage data signals V _R , V _T must be separately supplied to the reflection area and the penetration area, the data driving circuit 24 is increased to twice the operating frequency, and the two groups of different outputs can be respectively output in 1H time. Voltage data signals V _R , V _T to each data signal line D _m . Please refer to Figure 13. As the data driving circuit of the designed multiplier is more complicated, it is necessary to write the same gray scale value of the reflective area and the transmissive area to provide different voltage modes for each data line. The gamma voltage γ 0, γ 1 provided by the voltage generator 26 to the data driving circuit 24 has different gray scale values, so that the data driving circuit 24 does not have to increase the operating frequency, and the data driving circuit 24 can also output the corresponding voltage data signal. To the reflection zone and the penetration zone.

As shown in Figure 14, the voltage and gray-scale curves of the penetrating zone and the reflection zone of the single crystal hole-type transflective liquid crystal display before the compensation technique is added, as shown in the figure, if the single pixel is When the penetrating zone and the reflecting zone are written with the same voltage, they will respectively have different grayscale values. Therefore, the present invention adjusts the same data line to write two different voltage data signals by the voltage difference of different gray levels in the penetration area and the reflection area, so that the single pixel penetration area and the reflection area exhibit the same gray level. value. As shown in Fig. 15, the VT curve and the VR curve of the penetration region and the reflection region obtained by the driving method of the present invention can be exactly the same when any gray scale value is presented.

The above is a first preferred embodiment of the lower panel of the present invention. A second preferred embodiment of one of the pixels 212a of the lower panel of the present invention will be described hereinafter with reference to FIG.

The lower panel pixel 212a of the present embodiment has substantially the same structure as the first preferred embodiment, but the plurality of scanning lines G ₁ to G _{N of the} lower panel are horizontally staggered to form a plurality of sub-scanning lines G ₁ '~G _N ', i.e., corresponding to each pixel 212a has a scanning line G _n and a sub-scanning line G _n '; wherein a plurality of scan lines G ₁ ~ G _N and a plurality of scan line G _1' ~ G _N 'and the scan driving circuit (FIG. not shown) are connected, as for the multiplexer-based single pixel 212a of the present embodiment further comprises: a thin film transistor TFT1 transmissive region being formed on the transmissive region a _T and the present scan line pixels G _n, The data line D _m , the transmissive area storage capacitor C _ST1 and the transmissive area liquid crystal capacitor C _{LC1 are} connected, and are driven and turned on by the modulated scan signal of the pixel scanning line G _n , and the current pixel data line D is turned on. The voltage data of _m is written into the transmissive area storage capacitor C _ST1 ; and a reflective area thin film transistor TFT 2 is formed in the reflective area A _R and is adjacent to the picture scanning line G _n ', the data line D _m , and the reflective area The storage capacitor C _ST2 and the reflection area liquid crystal capacitor C _{LC2 are} connected, and are driven and turned on by the modulation scan signal of the picture scanning line G _n ', and Turn on the voltage data of the current data line D _m at the time and write it into the reflection area storage capacitor C _ST2 .

Please refer to FIG. 17 for the modulation scan signal and data signal waveform used in this embodiment. The scan driving circuit (not shown) alternately outputs the modulated scan signal to the sub-scanning line G _n ' and the scanning line G _{n of} each pixel in sequence. Each sub-scanning signal G _n 'and each scanning signal G _n includes a 0.5H high-potential signal, and the adjacent sub-scanning signal G _n 'and the scanning signal G _n are 0.5H time difference, so the sub-scan of the same pixel The total time of the high-level signal of the signal G _n ' and the scanning signal G _n is 1H. Since the high-potential signal of the sub-scanning signal G _n ' of the single pixel is 0.5H earlier than the scanning signal G _n , and the reflective film transistor TFT 2 gate G is connected to the sub-scanning line G _n ', the reflective area The gate of the thin film transistor TFT2 is turned on first, and the voltage data signal V _R on the pixel data line D _m is written to the reflective area storage capacitor C _ST2 for 0.5H time, and then the thin film of the penetrating region crystal TFT1 gate G is driven scanning line G _n is high potential signal is turned on, and at this time a voltage corresponding to the data signals present on the V _T pixels written to the data line D _m to penetrate the storage capacitor C _ST1. In addition, as shown in FIG. 18, the scan driving circuit can also maintain the output 1H high-potential signal to each scanning line G _n , but still maintain the output 0.5H high-potential signal to each sub-scanning line G _n ', so that a single pixel The sub-scanning signal G _n ' has a 0.5H time overlap with the scanning signal G _n .

It can be seen from the waveform diagrams of FIG. 17 and FIG. 18 that since different voltage data signals V _T , V _R must be separately supplied to the reflection area and the penetration area, the data driving circuit is increased to twice the operating frequency, respectively, in 1H time. Two sets of different voltage data signals V _T , V _{R are} outputted to each data signal line D _m , so the data driving circuit for simplifying the design of the frequency multiplication is also provided by directly adjusting the gamma voltage generator to the data driving circuit. The gamma voltage of the order value does not require the data driving circuit to increase the operating frequency, and the data driving circuit respectively outputs the corresponding voltage data signal to the reflection area and the penetration area.

As the second preferred embodiment of the above-described semi-transparent liquid crystal display device of the present invention, since the scanning line of the lower board is twice as large as the scanning line of the lower board of the first preferred embodiment, the problem that the layout area of the peripheral line of the lower board is insufficient is directly emphasized. ; Thus, as shown in FIG nineteen, schematic layout pattern plate oriented scanning lines G ₁ ~ G _N and the sub-scanning line G ₁ '~ G _N' of the second embodiment of the invention. In this embodiment the lower plate 211 corresponding to the respective display area 213 striped scanning lines G ₁ '~ G _N' segment and all scan lines G ₁ ~ G _N channel segment to a first metal forming process, the display area 21 and the lower plate Each of the sub-scanning lines G ₁ '~G _N ' line segments outside the range of 213 and the respective scanning lines G ₁ to G _N line segments are alternately formed by a second metal process. For example, each of the scanning lines G ₁ -G _{N in the} range of the lower panel display area 213 is still formed by the first metal process, and the sub-scanning lines G ₁ '~G _N outside the range of the lower panel display area 213 are formed. The line segment is formed by a second metal process, wherein the intersections of the respective sub-scan lines G ₁ '~G _N ' formed by the first and second metal processes are electrically connected through the conductive holes 214. Since the first and second metal processes are separated by an insulating layer, the lateral spacing of each of the sub-scanning lines G ₁ '~G _N ' outside the lower display area 213 and the scanning lines G ₁ -G _N can be shortened. Increase the wiring density over a limited area. Although the scanning lines G ₁ to G _N and the sub-scanning lines G ₁ '~G _N ' are formed by the first and second metal processes, the RC delay time is not the same, but the penetration area of the present invention The voltage with the reflection area is originally different, and the condition seen by each pixel is the same, so the mura problem of the development picture is not caused by the RC delay time.

In summary, the driving method for the transflective liquid crystal display of the present invention is to add a multiplexer to each pixel of the lower panel to match the modulated scanning signal and different voltage data signals to respectively control the wearing of each pixel. The voltage of the transmissive area and the reflective area are adjusted to match the VT curve and the VR curve of the transmissive area and the reflective area. In addition, the present invention adopts the driving circuit, which has low cost, high yield, no residual image and There is no advantage such as horizontal cross-talk.

10‧‧‧Semi-anti-liquid crystal display

11‧‧‧Upper board

12‧‧‧ Lower board

121‧‧‧ penetration zone

122‧‧‧Reflective zone

123‧‧‧reflective layer

124‧‧‧Insulated bumps

20‧‧‧Semi-transparent LCD

21‧‧‧Semi-transparent LCD panel

211‧‧‧ Lower board

212,212a‧‧‧ pixels

213‧‧‧Display area

22, 22a‧‧‧ timing controller

23,23a‧‧‧Scan drive circuit

24‧‧‧Data Drive Circuit

25‧‧‧Common voltage generating circuit

26‧‧‧Gamma Voltage Generator

214‧‧‧Electrical hole

Figure 1: is a longitudinal sectional view of a single pixel of a single-cell gap-type transflective liquid crystal display.

Figure 2: is a longitudinal cross-sectional view of another single-pixel gap-type transflective liquid crystal display.

Figure 3: Figure 2 shows the VR curve and VT curve of different gap sizes.

Figure 4: An equivalent circuit diagram of a single pixel of a single-cell gap-type transflective liquid crystal display.

Figure 5: The VT curve and VR curve of the liquid crystal display of Figure 4 are implemented.

Fig. 6 is an equivalent circuit diagram of a single pixel of a single-cell gap-type semi-transflective liquid crystal display.

Figure 7: The VT curve and VR curve of the liquid crystal display of Figure 6 are implemented.

Figure 8 is a schematic view showing the structure of a first preferred embodiment of the single crystal hole gap type transflective liquid crystal display of the present invention.

Figure 9: Figure 8 is a single pixel equivalent circuit diagram.

Figure 10: Diagram of the modulation scan signal and data signal waveform of Figure 8.

Figure 11 is a schematic view showing another structure of the single crystal hole gap type transflective liquid crystal display of the present invention.

Figure 12: The first and second timing signals and the odd/even scan signal waveforms of Figure 11.

Figure 13: Figure 8 shows another waveform of the modulated scan signal and data signal.

Figure 14: Figure 1 shows the voltage and gray-scale plots of the simulated penetration and reflection zones before the compensation technique is added.

Figure 15: Figure 8 shows the voltage and grayscale curves of the simulated penetration zone and the reflection zone.

Figure 16 is a single pixel equivalent circuit diagram of a second preferred embodiment of the single crystal hole gap type transflective liquid crystal display of the present invention.

Figure 17: Figure 16 shows the waveform of the modulated scan signal and data signal.

Figure 18: Another modified scan signal and data signal waveform diagram of Figure 16.

Fig. 19 is a schematic diagram showing the layout pattern of the scanning lines G ₁ to G _N and the sub-scanning lines G ₁ '~G _N ' of the lower panel of Fig. 16.

212‧‧‧ pixels

Claims (18)

A driving method for a single-cell hole-type transflective liquid crystal display, wherein the transflective liquid crystal display comprises a thin film transistor substrate on which a plurality of matrix array pixels are defined, each pixel comprising a reflective region and a transmissive region The improvement is that the driving method is to add a multiplexer to each pixel of the lower board, and the multiplexer is respectively connected to the storage capacitor of the reflective area and the storage capacitor of the penetration area, and the multiplexer is modulated by Scanning signals and different voltage data signals respectively write different voltage data signals into the reflection area storage capacitors and the penetration area storage capacitors of each pixel to adjust the VT curve and the VR curve of the penetration area and the reflection area. The method for driving a single-crystal hole-filled transflective liquid crystal display according to claim 1, wherein each multiplexer comprises: a penetrating region thin film transistor formed in the penetrating region and associated with The pixel scanning line, the data line and the transmission area storage capacitor connection are driven and turned on by the modulation scanning signal of the pixel scanning line, and the voltage data of the current pixel data line is turned into the penetration area for storage. The first thin film transistor in the reflective region is formed in the reflective region and connected to the scanning line and the data line of the picture, and is driven and turned on by the modulated scanning signal of the pixel scanning line; and a reflective area a thin film transistor formed in the reflective region and connected in series with the first thin film transistor of the reflective region, and connected to the next pixel scan line of the pixel and the storage capacitor of the reflective region; When the modulation scan signal of the pixel scan line is driven to be turned on and off, and is simultaneously turned on with the first thin film transistor in the reflective region, The first thin film transistor in the over-reflection region writes the voltage data of the pixel data line into the storage capacitor of the penetration region. The driving method of the single crystal hole gap type transflective liquid crystal display according to claim 1, wherein the lower plate is further formed with a plurality of scanning lines and a plurality of sub scanning lines arranged in a staggered horizontal arrangement to form a plurality of data lines. The horizontal and vertical intersections have a scanning line and a sub-scanning line corresponding to each pixel; wherein each multiplexer comprises: a penetrating region thin film transistor formed in the penetrating region and scanned with the pixel The data line and the transmission area storage capacitor connection are driven and turned on by the modulation scan signal of the picture scanning line, and the voltage data of the current pixel data line is turned into the transmission area storage capacitor; The reflective region thin film transistor is formed in the reflective region and is connected to the pixel scanning line, the data line and the transmission area storage capacitor of the picture, and is driven and turned on by the modulation scan signal of the picture scanning line, and will be turned on and off. The voltage data of the pixel data line is written into the storage capacitor of the penetration area. The method for driving a single-crystal-hole gap type transflective liquid crystal display according to the second aspect of the invention, wherein the plurality of scanning lines of the lower plate sequentially receive a modulated scanning signal in sequence, and each modulated scanning signal is The driving signal of 2H includes a 0.5H first high potential signal, a 0.5H low potential signal and a 1H second high potential signal, and the time difference between the modulated scanning signals of the front and rear scanning lines is 1H. The method for driving a single-crystal hole gap type transflective liquid crystal display according to claim 4, wherein the method of generating the modulated scan signal first obtains two sets of timing signals with a phase difference of 1H and a pulse time of 0.5H. Then, the odd and even scan signals including the 2H high potential signal are respectively subtracted from the two sets of timing signals. The method for driving a single-crystal-hole gap type transflective liquid crystal display according to claim 3, wherein the plurality of sub-scanning lines and the scanning lines sequentially receive a modulated scanning signal in sequence, the modulation The scanning signal is a driving signal of 0.5H, and the sub-scanning line corresponding to each pixel and the modulated scanning signal of the scanning line are separated by a time interval of 0.5H. The method for driving a single-crystal hole-type transflective liquid crystal display according to claim 3, wherein the lower sub-multiple scanning lines sequentially receive a first modulated scanning signal, and the plurality of scanning lines are sequentially received. The second modulation signal is periodically received, wherein the first modulation signal is a high-potential signal of 0.5H, and the second modulation signal is a high-potential signal of 1H, and the sub-scanning lines and scans corresponding to each pixel There is no time difference between the line modulation scan signals. The method for driving a single-crystal hole-filled transflective liquid crystal display according to claim 1, wherein the transflective liquid crystal display further comprises a data driving circuit and a gamma voltage connected to the data driving circuit a generator, wherein the data driving circuit provides a voltage data signal of each pixel data line, and the data driving circuit is not provided by directly adjusting the gamma voltage generator The gamma voltage of the gray scale value causes the data driving circuit to respectively output the corresponding voltage data signal to the reflection area and the penetration area. The invention relates to a single-cell gap type transflective liquid crystal display, which comprises a transflective liquid crystal panel, a timing controller, a scan driving circuit and a data driving circuit. The improvement is that the semi-transparent liquid crystal panel comprises an upper portion. a plate and a lower plate with a liquid crystal layer interposed therebetween, and the lower plate is formed with a common electrode and a plurality of scanning lines and data lines arranged in a horizontal and vertical staggered manner, wherein a intersection of the scanning line and the data line is defined as a pixel, wherein Each pixel includes a penetrating region, a reflecting region and a multiplexer, and the multiplexer is connected to the pixel scanning line and the data line; the scanning driving circuit is connected to the plurality of scanning lines to periodically The output output modulated scanning signal to the complex scanning line drives each pixel multiplexer to determine the opening and closing sequence and the opening time of the reflection area and the penetration area; the data driving circuit is connected to the plurality of data lines for the same gray The order value outputs two sets of different voltage data signals to the penetration area and the reflection area of each pixel opening; and the timing controller provides a fixed timing signal to the scan driving circuit and the data Moving circuit. A single crystal hole gap type transflective liquid crystal display according to claim 9, wherein each multiplexer comprises: a penetrating region thin film transistor formed in the penetrating region and associated with the pixel Scanning line, data line and transmission area storage capacitor connection, modulated by the scanning line of the pixel The signal is driven to open and close, and the voltage data of the current data line of the current pixel is written into the storage capacitor of the penetration area; the first thin film transistor of a reflection area is formed in the reflection area and is scanned with the screen and The data line is connected and driven to be turned on and off by the modulated scanning signal of the pixel scanning line; and a second thin film transistor in the reflective region is formed in the reflective region and connected in series with the first thin film transistor of the reflective region, and Connected to the next pixel scan line of the pixel and the storage capacitor of the reflective region; driven and turned on by the modulated scan signal of the next pixel scan line of the pixel, and simultaneously opened with the first thin film transistor of the reflective region The voltage data of the pixel data line is written into the transmissive area storage capacitor through the first thin film transistor in the reflective region. The single crystal hole gap type transflective liquid crystal display according to claim 9, wherein the lower plate further forms a plurality of sub-scanning lines horizontally interlaced with the plurality of scanning lines to cross the plurality of data lines horizontally and vertically The pixel corresponds to a scan line and a sub-scan line; wherein each multiplexer comprises: a penetrating region thin film transistor formed in the penetrating region and intersecting with the pixel scan line, the data line and the penetrating region The storage capacitor connection is driven and turned on by the modulation scan signal of the pixel scan line, and the voltage data of the current pixel data line is turned into the storage capacitor of the penetration area; and a reflective area film transistor is Formed in the reflective area and connected with the picture scanning line, the data line and the transmission area storage capacitor of the picture, and are adjusted by the scanning line of the picture The variable scan signal is driven to turn on and off, and the voltage data of the current pixel data line at the time is written into the storage capacitor of the penetration area. The single crystal hole gap type transflective liquid crystal display according to claim 10, wherein the scan driving circuit outputs a driving signal whose modulation scanning signal is 2H, which comprises a 0.5H first high potential signal, and a The low potential signal of 0.5H and the second high potential signal of 1H, and the time difference of the modulated scanning signal interval of 1H of the front and rear scanning lines. The single crystal hole gap type transflective liquid crystal display according to claim 12, wherein: the plurality of scan lines comprise odd-numbered scan lines and even-numbered scan lines formed on opposite sides of the lower plate; the timing controller, Providing a first timing signal and a second timing signal, wherein the first timing signal and the second timing signal have the same frequency, and the timing difference is 1H, wherein the pulse wave accounts for 0.5H; the scan driving circuit sequentially generates the There are odd and even scan signals of the 2H high potential signal, and the odd and even scan signals are respectively subtracted from the first and second timing signals, and the modulated scan signal is output. The single crystal hole-type transflective liquid crystal display according to claim 11, wherein the lower sub-scanning line and the scanning line sequentially receive a modulated scanning signal in sequence, the modulated scanning signal system. It is a driving signal of 0.5H, and the sub-scanning line corresponding to each pixel and the modulated scanning signal of the scanning line are separated by a time interval of 0.5H. The single crystal hole-type transflective liquid crystal display according to claim 11, wherein the lower sub-scanning line sequentially receives a first modulated scanning signal, and the plurality of scanning lines are sequentially The second modulation signal is periodically received, wherein the first modulation signal is a high-potential signal of 0.5H, and the second modulation signal is a high-potential signal of 1H, and the sub-scanning lines and the scanning lines corresponding to each pixel are adjusted. There is no time difference between the variable scanning signals. The single crystal hole gap type transflective liquid crystal display according to claim 9, which further comprises: a gamma voltage generator connected to the data driving circuit and provided to the data driving circuit different gray The gamma voltage of the order value causes the data driving circuit to respectively output the corresponding voltage data signal to the reflection area and the penetration area; and a common voltage generating circuit is connected to the common electrode to provide the same low voltage level of each pixel . The single crystal hole-type transflective liquid crystal display according to claim 11, wherein the lower transflective liquid crystal display lower plate corresponds to each sub-scanning line segment of the display area and each scanning line segment is first The metal process is formed, and each of the sub-scanning line segments and the respective scanning line segments outside the display area of the lower plate are alternately formed by a second metal process, wherein the first metal process and the second metal process are formed. The scanning line segments are electrically connected through the conductive holes. The single crystal hole-type transflective liquid crystal display according to claim 17, wherein each of the sub-scanning line segments outside the display area of the lower plate is The second metal process is used, and the scanning line segments outside the display area of the lower plate are formed by the first metal process, wherein the sub-scanning line segments in the lower panel display area are electrically connected through the conductive holes.