CN110767151B - Light emitting diode display panel - Google Patents
Light emitting diode display panel Download PDFInfo
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- CN110767151B CN110767151B CN201910995007.4A CN201910995007A CN110767151B CN 110767151 B CN110767151 B CN 110767151B CN 201910995007 A CN201910995007 A CN 201910995007A CN 110767151 B CN110767151 B CN 110767151B
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- 239000003990 capacitor Substances 0.000 claims description 54
- 230000008878 coupling Effects 0.000 claims description 21
- 238000010168 coupling process Methods 0.000 claims description 21
- 238000005859 coupling reaction Methods 0.000 claims description 21
- 238000010586 diagram Methods 0.000 description 7
- 238000003384 imaging method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
Abstract
The invention discloses a light-emitting diode display panel. The light emitting diode display panel includes a plurality of data lines, a plurality of gate lines, a plurality of pixels, and a second transistor. The plurality of pixels are disposed in an effective display area of the light emitting diode display panel. A first pixel of the plurality of pixels includes a light emitting diode and a first transistor. The light emitting diode is coupled to a ground voltage. The first transistor is coupled between a first data line of the plurality of data lines and the light emitting diode. The gate of the first transistor is coupled to a first gate line of the plurality of gate lines and is controlled by a driving signal provided by the first gate line. The second transistor is disposed outside the effective display area. The second transistor is coupled to the first data line and a gate of the second transistor is controlled by a switching signal.
Description
Technical Field
The present invention relates to a display, and more particularly, to a Light-Emitting Diode (LED) display panel.
Background
Referring to fig. 1 and 2, fig. 1 is a schematic diagram showing a pixel design of a conventional led display panel; fig. 2 is a timing chart illustrating the control signals of the second transistor in fig. 1.
As shown in fig. 1, the pixel 1 of the conventional led display panel adopts a "2T1C" architecture, i.e., each pixel includes a first transistor T1, a second transistor T2 and a storage capacitor CS. The first transistor T1 is disposed between the working voltage VDD and the light emitting diode LED, and the first transistor T1 is controlled by the gate voltage VG; the second transistor T2 is disposed between the gate of the first transistor T1 and the data signal VDAT, and the second transistor T2 is controlled by the driving signal S (N); one end of the storage capacitor CS is coupled between the gate of the second transistor T2 and the gate of the first transistor T1, and the other end of the storage capacitor CS is coupled between the first transistor T1 and the light emitting diode LED.
In general, existing "2T1C" architectures are better suited for pixels that employ voltage Holding-type (Holding-type) imaging. However, since the driving current (about mA level) of the Light Emitting Diode LED is much larger than the driving current (about uA level) of the Organic Light-Emitting Diode (OLED), the total current of the Light Emitting Diode display panel employing the voltage holding mode is excessively high to increase power consumption.
In addition, since the width of the first transistor T1 disposed between the operating voltage VDD and the light emitting diode LED in each pixel is larger, with the development trend of the high resolution display panel, the difficulty of the circuit layout of the pixel is greatly increased due to the limitation of the components and the wirings when the pixel density (PPI) is increased, which needs to be overcome.
Disclosure of Invention
Accordingly, the present invention is directed to a light emitting diode display panel, which solves the above-mentioned problems encountered in the prior art.
An embodiment according to the present invention is a light emitting diode display panel. In this embodiment, the light emitting diode display panel includes a plurality of data lines, a plurality of gate lines, a plurality of pixels, and a second transistor. The plurality of pixels are disposed in an effective display area of the light emitting diode display panel. A first pixel of the plurality of pixels includes a light emitting diode and a first transistor. The light emitting diode is coupled to a ground voltage. The first transistor is coupled between a first data line of the plurality of data lines and the light emitting diode. The gate of the first transistor is coupled to a first gate line of the plurality of gate lines and is controlled by a driving signal provided by the first gate line. The second transistor is disposed outside the effective display area. The second transistor is coupled to the first data line and a gate of the second transistor is controlled by a switching signal.
In one embodiment, a coupling capacitor is provided between the first data line and the first gate line for storing charges.
In an embodiment, the second pixel of the plurality of pixels includes another light emitting diode and another first transistor. The other LED is coupled to the ground voltage. The other first transistor is coupled between the first data line and the other light emitting diode, and a gate of the first transistor is coupled with a second gate line of the plurality of gate lines and is controlled by another driving signal provided by the second gate line. The first pixel and the second pixel share the second transistor through the first data line.
In one embodiment, the first pixel further includes a storage capacitor having one end coupled to the first data line and the other end coupled between the light emitting diode and the ground voltage for storing charges.
In an embodiment, the second transistor is further coupled to the driving circuit and receives a data signal provided by the driving circuit, and when the second transistor is controlled by the switching signal to be turned on, the second transistor outputs the data signal to the first data line.
In an embodiment, the light emitting diode display panel further includes a third transistor disposed outside the effective display area, the third transistor is coupled between the first data line and the driving circuit, and a gate of the third transistor is controlled by the reference signal.
In one embodiment, when the third transistor is turned on under the control of the reference signal, the third transistor detects the current of the first data line and outputs a feedback signal to the driving circuit as a reference for compensation.
In an embodiment, when the first transistor is turned on by the driving signal, the current passing through the first transistor drives the light emitting diode to emit light.
In an embodiment, the light emitting diode display panel further includes another second transistor disposed outside the effective display area, the another second transistor is coupled to a second data line of the plurality of data lines, and a gate of the another second transistor is controlled by another switching signal.
In an embodiment, a third pixel and a fourth pixel of the plurality of pixels are coupled to the second data line and share the other second transistor through the second data line.
Compared with the prior art, the pixel design of the light emitting diode display panel of the present invention adopts a "1T1C" architecture or a "1T" architecture, rather than the conventional "2T1C" architecture, that is, each pixel includes a first transistor and a storage capacitor or only includes a first transistor, and shares a second transistor outside the effective display area, so that the circuit layout is easier, and even if the pixel density is increased, the circuit layout difficulty is not easily limited by each element and the wiring and greatly increased, so that the light emitting diode display panel of the present invention is applicable to the panel design with high resolution.
In addition, since the led display panel of the present invention adopts the pulse driving mode (Impulse driving mode) to drive all pixels in a partitioned manner, the required current is lower than that of the conventional voltage Holding mode (Holding-type), so that the total power consumption of the led display panel can be effectively reduced, and the number of driving circuits can be reduced by providing a multiplexer between the driving circuit and the second transistor.
The advantages and spirit of the present invention will be further understood from the following detailed description of the invention and the accompanying drawings.
Drawings
Fig. 1 is a schematic diagram showing a pixel design of a conventional led display panel.
Fig. 2 is a timing chart showing control signals of the second transistor in fig. 1.
Fig. 3 is a schematic diagram illustrating a light emitting diode display panel according to an embodiment of the invention.
Fig. 4 is a timing diagram illustrating the switching signals, the data signals and the driving signals in fig. 3.
Fig. 5 is a schematic view illustrating a light emitting diode display panel according to another embodiment of the invention.
Fig. 6 is a timing diagram illustrating the switching signals, the data signals and the driving signals in fig. 5.
Fig. 7 is a schematic view illustrating a light emitting diode display panel according to another embodiment of the invention.
FIG. 8 is a timing diagram illustrating the switching signals, data signals, driving signals and reference voltages of FIG. 7.
Wherein, the reference numerals:
1: pixel arrangement
VDD: operating voltage
VD: drain voltage
VS: source voltage
VG: gate voltage
3. 5, 7: light emitting diode display panel
AA: effective display area
PX1 to PX4: pixel arrangement
DL (i-1) to DL (i): data line
GL (N-1) to GL (N): gate line
S (N-1) to S (N+1): drive signal
SW (i-1) to SW (i): switching signals
T1: first transistor
An LED: light emitting diode
CC: coupling capacitor
VSS: ground voltage
T2: second transistor
VDAT: data signal
CS: storage capacitor
I: electric current
VGH: high level
VGL: low level
LEP: light-emitting period
VREF: reference voltage
T3: third transistor
IC: driving circuit
Detailed Description
The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. As will be recognized by those skilled in the art, the described embodiments may be modified in various different ways without departing from the spirit or scope of the invention.
In the drawings, a partial region is exaggerated for clarity. Like numbers refer to like elements throughout. It will be understood that when an element such as a region or substrate is referred to as being "on" or "connected (or referred to as being" coupled ") or" electrically connected "to another element, it can be directly on or connected (or referred to as being coupled) or electrically connected to the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected (or referred to as coupled)" may refer to a physical and/or electrical connection.
An embodiment according to the present invention is a light emitting diode display panel. Referring to fig. 3, fig. 3 is a schematic diagram illustrating a light emitting diode display panel in this embodiment.
As shown in fig. 3, the light emitting diode display panel 3 includes a plurality of data lines DL (i-1) to DL (i), a plurality of gate lines GL (N-1) to GL (N), a plurality of pixels PX1 to PX4, and a plurality of second transistors T2, wherein i and N are positive integers. It should be noted that, in this embodiment, two data lines, two gate lines, four pixels and two second transistors are taken as examples, but the invention is not limited thereto.
The light emitting diode display panel 3 includes an effective display area AA. The plurality of pixels PX1 to PX4 are disposed in the effective display area AA of the light emitting diode display panel 3 and the plurality of second transistors T2 are disposed outside the effective display area AA of the light emitting diode display panel 3.
The first data line DL (i-1) of the plurality of data lines DL (i-1) -DL (i) is coupled to the first pixel PX1 and the second pixel PX2 of the plurality of pixels PX 1-PX 4 and a second transistor T2 of the plurality of second transistors T2; the second data line DL (i) of the plurality of data lines DL (i-1) to DL (i) is coupled to the third pixel PX3 and the fourth pixel PX4 of the plurality of pixels PX1 to PX4 and another second transistor T2 of the plurality of second transistors T2; a first gate line GL (N-1) of the plurality of gate lines GL (N-1) to GL (N) is coupled to a first pixel PX1 and a third pixel PX3 of the plurality of pixels PX1 to PX 4; the second gate line GL (N) of the plurality of gate lines GL (N-1) to GL (N) is coupled to the second pixel PX2 and the fourth pixel PX4 of the plurality of pixels PX1 to PX4.
That is, the first pixel PX1 of the plurality of pixels PX1 to PX4 is coupled to the first data line DL (i-1) of the plurality of data lines DL (i-1) to DL (i) and the first gate line GL (N-1) of the plurality of gate lines GL (N-1) to GL (N), respectively; the second pixel PX2 of the pixels PX 1-PX 4 is coupled to the first data line DL (i-1) of the data lines DL (i-1) -DL (i) and the second gate line GL (N) of the gate lines GL (N-1) -GL (N), respectively; the third pixel PX3 of the plurality of pixels PX1 to PX4 is coupled to the second data line DL (i) of the plurality of data lines DL (i-1) to DL (i) and the first gate line GL (N-1) of the plurality of gate lines GL (N-1) to GL (N), respectively; the fourth pixel PX4 of the plurality of pixels PX1 to PX4 is coupled to the second data line DL (i) of the plurality of data lines DL (i-1) to DL (i) and the second gate line GL (N) of the plurality of gate lines GL (N-1) to GL (N), respectively. The first pixel PX1 and the second pixel PX2 of the plurality of pixels PX1 to PX4 share the second transistor T2 coupled to the first data line DL (i-1); the third pixel PX3 and the fourth pixel PX4 of the plurality of pixels PX1 to PX4 share the second transistor T2 coupled to the second data line DL (i).
In this embodiment, the pixels PX1 to PX4 each adopt a pixel design of a "1T1C" architecture, that is, each of the pixels PX1 to PX4 includes a transistor and a capacitor.
Taking the first pixel PX1 as an example, the first pixel PX1 includes a light emitting diode LED, a first transistor T1, and a storage capacitor CS. The light emitting diode LED is coupled to the ground voltage VSS. The first transistor T1 is coupled between a first data line DL (i-1) of the plurality of data lines DL (i-1) to DL (i) and the light emitting diode LED. The gate of the first transistor T1 is coupled to a first gate line GL (N-1) among the gate lines GL (N-1) to GL (N) and is controlled by a driving signal S (N-1) provided by the first gate line GL (N-1). One end of the storage capacitor CS is coupled to the first data line DL (i-1) and the other end of the storage capacitor CS is coupled between the light emitting diode LED and the ground voltage VSS for storing charges.
Similarly, if the second pixel PX2 is taken as an example, the second pixel PX2 also includes a light emitting diode LED, a first transistor T1, and a storage capacitor CS. The light emitting diode LED is coupled to the ground voltage VSS. The first transistor T1 is coupled between a first data line DL (i-1) of the plurality of data lines DL (i-1) to DL (i) and the light emitting diode LED. The gate of the first transistor T1 is coupled to a second gate line GL (N) of the plurality of gate lines GL (N-1) to GL (N) and is controlled by a driving signal S (N) provided by the second gate line GL (N). One end of the storage capacitor CS is coupled to the first data line DL (i-1) and the other end of the storage capacitor CS is coupled between the light emitting diode LED and the ground voltage VSS for storing charges.
Similarly, if the third pixel PX3 is taken as an example, the third pixel PX3 also includes a light emitting diode LED, a first transistor T1, and a storage capacitor CS. The light emitting diode LED is coupled to the ground voltage VSS. The first transistor T1 is coupled between a second data line DL (i) of the plurality of data lines DL (i-1) -DL (i) and the light emitting diode LED. The gate of the first transistor T1 is coupled to a first gate line GL (N-1) among the gate lines GL (N-1) to GL (N) and is controlled by a driving signal S (N-1) provided by the first gate line GL (N-1). One end of the storage capacitor CS is coupled to the second data line DL (i), and the other end of the storage capacitor CS is coupled between the light emitting diode LED and the ground voltage VSS for storing charges.
Similarly, if the fourth pixel PX4 is taken as an example, the fourth pixel PX4 also includes a light emitting diode LED, a first transistor T1, and a storage capacitor CS. The light emitting diode LED is coupled to the ground voltage VSS. The first transistor T1 is coupled between a second data line DL (i) of the plurality of data lines DL (i-1) -DL (i) and the light emitting diode LED. The gate of the first transistor T1 is coupled to a second gate line GL (N) of the plurality of gate lines GL (N-1) to GL (N) and is controlled by a driving signal S (N) provided by the second gate line GL (N). One end of the storage capacitor CS is coupled to the second data line DL (i), and the other end of the storage capacitor CS is coupled between the light emitting diode LED and the ground voltage VSS for storing charges.
The second transistor T2 coupled to the first data line DL (i-1) is also coupled to the data signal VDAT, and the gate of the second transistor T2 is controlled by the switching signal SW (i-1); the second transistor T2 coupled to the second data line DL (i) is also coupled to the data signal VDAT, and the gate of the second transistor T2 is controlled by the switching signal SW (i).
In practical applications, the plurality of second transistors T2 may be coupled to the driving circuit and receive the data signal VDAT provided by the driving circuit through a multiplexer, and the multiplexer may be a one-to-two, a one-to-three or other designs, so as to reduce the number of driving circuits, but not limited thereto.
Please refer to fig. 1 and fig. 2 at the same time. Taking the first pixel PX1 as an example, when the switching signal SW (i-1) changes from the low level VGL to the high level VGH, the other switching signal SW (i) still maintains the low level VGL, and the second transistor T2 controlled by the switching signal SW (i-1) is turned on, so as to charge the storage capacitor CS in the first pixel PX1 and the second pixel PX2 respectively through the first data line DL (i-1). After the switching signal SW (i-1) is changed from the high level VGH to the low level VGL, when the other switching signal SW (i) is changed from the low level VGL to the high level VGH, the second transistor T2 controlled by the switching signal SW (i) is turned on, so as to charge the storage capacitor CS in the third pixel PX3 and the fourth pixel PX4 respectively through the second data line DL (i).
Then, when the driving signal S (N-1) that is always maintained at the low level VGL changes to the high level VGH, the first transistor T1 controlled by the driving signal S (N-1) in the first pixel PX1 is turned on, so that the charges stored in the storage capacitor CS in the first pixel PX1 and the second pixel PX2 flow to the first transistor T1 in the first pixel PX1 to form a current I passing through the first transistor T1, so as to drive the light emitting diode LED in the first pixel PX1 to emit light. Therefore, for the first pixel PX1, the period during which the driving signal S (N-1) is at the high level VGH may be referred to as "light emitting period LEP".
Similarly, for the third pixel PX3, when the driving signal S (N-1) is at the high level VGH, the first transistor T1 of the third pixel PX3 controlled by the driving signal S (N-1) is turned on, so that the charges stored in the storage capacitors CS of the third pixel PX3 and the fourth pixel PX4 flow to the first transistor T1 of the third pixel PX3 to form a current I passing through the first transistor T1, so as to drive the light emitting diode LED of the third pixel PX3 to emit light. Therefore, the period during which the driving signal S (N-1) is at the high level VGH for the third pixel PX3 may also be referred to as "light emitting period LEP".
Similarly, for the second pixel PX2, when the driving signal S (N) is at the high level VGH, the first transistor T1 controlled by the driving signal S (N) in the second pixel PX2 is turned on, so that the charges stored in the storage capacitor CS of the first pixel PX1 and the second pixel PX2 flow to the first transistor T1 in the second pixel PX2 to form a current I passing through the first transistor T1, so as to drive the light emitting diode LED in the second pixel PX2 to emit light. Therefore, the period during which the driving signal S (N) is at the high level VGH for the second pixel PX2 may also be referred to as "light emitting period LEP".
Similarly, when the driving signal S (N) is at the high level VGH, the first transistor T1 controlled by the driving signal S (N) in the fourth pixel PX4 is turned on, so that the charges stored in the storage capacitor CS in the third pixel PX3 and the fourth pixel PX4 flow to the first transistor T1 in the fourth pixel PX4 to form a current I passing through the first transistor T1, so as to drive the light emitting diode LED in the fourth pixel PX4 to emit light. Therefore, the period during which the driving signal S (N) is at the high level VGH for the fourth pixel PX4 may also be referred to as "light emitting period LEP".
In another embodiment, referring to fig. 5, the pixels PX1 to PX4 in the led display panel 5 are all configured as a pixel design with a "1T" structure, that is, each of the pixels PX1 to PX4 in the led display panel 5 includes the first transistor T1, but does not include the storage capacitor CS in the previous embodiment.
Please refer to fig. 5 and fig. 6 simultaneously. If the first pixel PX1 is taken as an example, when the switching signal SW (i-1) is changed from the low level VGL to the high level VGH, the other switching signal SW (i) still maintains the low level VGL, and the second transistor T2 controlled by the switching signal SW (i-1) is turned on, at this time, the charges transferred through the first data line DL (i-1) can be stored in the coupling capacitor CC, for example, the coupling capacitor CC between the first data line DL (i-1) and the first gate line GL (N-1) and the coupling capacitor CC between the first data line DL (i-1) and the second gate line GL (N), but not limited thereto. In practice, the coupling capacitor CC may be any other capacitor coupled to the first data line DL (i-1), but is not limited thereto.
After the switch signal SW (i-1) is changed from the high level VGH to the low level VGL, when the other switch signal SW (i) is changed from the low level VGL to the high level VGH, the second transistor T2 controlled by the switch signal SW (i) is turned on, and at this time, the charges transferred through the second data line DL (i) may be stored in the coupling capacitor CC, for example, but not limited to, the coupling capacitor CC between the second data line DL (i) and the first gate line GL (N-1) and the coupling capacitor CC between the second data line DL (i) and the second gate line GL (N). In practice, the coupling capacitor CC may be any other capacitor coupled to the second data line DL (i), but is not limited thereto.
Then, when the driving signal S (N-1) always maintained at the low level VGL becomes the high level VGH, the first transistor T1 controlled by the driving signal S (N-1) in the first pixel PX1 is turned on, so that the charge stored in the coupling capacitor CC between the first data line DL (I-1) and the first gate line GL (N-1) and the coupling capacitor CC between the first data line DL (I-1) and the second gate line GL (N) flows to the first transistor T1 in the first pixel PX1 to form a current I passing through the first transistor T1, thereby driving the light emitting diode LED in the first pixel PX1 to emit light. Therefore, for the first pixel PX1, the period during which the driving signal S (N-1) is at the high level VGH may be referred to as "light emitting period LEP".
Similarly, for the third pixel PX3, when the driving signal S (N-1) is at the high level VGH, the first transistor T1 controlled by the driving signal S (N-1) in the third pixel PX3 is turned on, so that the charges stored in the coupling capacitor CC between the second data line DL (I) and the first gate line GL (N-1) and the coupling capacitor CC between the second data line DL (I) and the second gate line GL (N) flow to the first transistor T1 in the third pixel PX3 to form a current I passing through the first transistor T1, so as to drive the light emitting diode LED in the third pixel PX3 to emit light. Therefore, the period during which the driving signal S (N-1) is at the high level VGH for the third pixel PX3 may also be referred to as "light emitting period LEP".
Similarly, for the second pixel PX2, when the driving signal S (N) is at the high level VGH, the first transistor T1 controlled by the driving signal S (N) in the second pixel PX2 is turned on, so that the charges stored in the coupling capacitor CC between the first data line DL (I-1) and the first gate line GL (N-1) and the coupling capacitor CC between the first data line DL (I-1) and the second gate line GL (N) flow to the first transistor T1 in the second pixel PX2 to form a current I passing through the first transistor T1, so as to drive the light emitting diode LED in the second pixel PX2 to emit light. Therefore, the period during which the driving signal S (N) is at the high level VGH for the second pixel PX2 may also be referred to as "light emitting period LEP".
Similarly, when the driving signal S (N) is at the high level VGH, the first transistor T1 controlled by the driving signal S (N) in the fourth pixel PX4 is turned on, so that the charges stored in the coupling capacitor CC between the second data line DL (I) and the first gate line GL (N-1) and the coupling capacitor CC between the second data line DL (I) and the second gate line GL (N) flow to the first transistor T1 in the fourth pixel PX4 to form a current I passing through the first transistor T1, so as to drive the light emitting diode LED in the fourth pixel PX4 to emit light. Therefore, the period during which the driving signal S (N) is at the high level VGH for the fourth pixel PX4 may also be referred to as "light emitting period LEP".
In another embodiment, referring to fig. 7, the pixels PX1 to PX4 in the led display panel 7 are configured as the pixels PX1 to PX4 in the led display panel 3 of fig. 3 by a pixel design of "1T1C", that is, each of the pixels PX1 to PX4 in the led display panel 7 includes a first transistor T1 and a storage capacitor CS.
Note that, the led display panel 7 of fig. 7 is different from the led display panel 3 of fig. 3 in that: the led display panel 7 of fig. 7 further includes a compensation circuit around the effective display area AA, for example, the led display panel 7 of fig. 7 further includes a plurality of third transistors T3 disposed outside the effective display area AA.
As shown in fig. 7, a third transistor T3 of the plurality of third transistors T3 included in the led display panel 7 is coupled between the first data line DL (i-1) and the driving circuit IC, and the gate of the third transistor T3 is controlled by the reference signal VREF; another third transistor T3 of the plurality of third transistors T3 is coupled between the second data line DL (i) and the driving circuit IC, and the gate of the third transistor T3 is also controlled by the reference signal VREF.
Please refer to fig. 7 and fig. 8. During the period when the switching signal SW (i-1) is at the high level VGH to charge the first data line DL (i-1), when the reference signal VREF is changed from the low level VGL to the high level VGH, the third transistor T3 coupled to the first data line DL (i-1) is controlled by the reference signal VREF to be conducted, thereby detecting the current of the first data line DL (i-1) and outputting the feedback signal to the driving circuit IC as a reference for compensation of the driving circuit IC.
Similarly, during the period when the switching signal SW (i) is at the high level VGH and charges the second data line DL (i), when the reference signal VREF is changed from the low level VGL to the high level VGH, the third transistor T3 coupled to the second data line DL (i) is controlled to be turned on by the reference signal VREF, so as to detect the current of the second data line DL (i) and output the feedback signal to the driving circuit IC as a reference for the compensation of the driving circuit IC.
Compared with the prior art, the pixel design of the light emitting diode display panel of the present invention adopts a "1T1C" architecture or a "1T" architecture, rather than the conventional "2T1C" architecture, that is, each pixel includes a first transistor and a storage capacitor or only includes a first transistor, and shares a second transistor outside the effective display area, so that the circuit layout is easier, and even if the pixel density is increased, the circuit layout difficulty is not easily limited by each element and the wiring and greatly increased, so that the light emitting diode display panel of the present invention is applicable to the panel design with high resolution.
In addition, since the led display panel of the present invention adopts the pulse driving mode (Impulse driving mode) to drive all pixels in a partitioned manner, the required current is lower than that of the conventional voltage Holding mode (Holding-type), so that the total power consumption of the led display panel can be effectively reduced, and the number of driving circuits can be reduced by providing a multiplexer between the driving circuit and the second transistor.
The foregoing detailed description of the preferred embodiments is intended to more clearly describe the features and spirit of the invention, but is not intended to limit the scope of the invention by way of the preferred embodiments disclosed above. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended claims.
Claims (1)
1. A light emitting diode display panel, comprising:
a plurality of data lines;
a plurality of gate lines;
a plurality of pixels arranged in an effective display area of the LED display panel;
the light emitting diode display panel further includes:
the second transistor is arranged outside the effective display area, is coupled with the first data line and has a grid electrode controlled by a switching signal; and
a third transistor disposed outside the effective display region, the third transistor being coupled between the first data line and a driving circuit and having a gate controlled by a reference signal;
each pixel consists of a light emitting diode, a first transistor and a storage capacitor, wherein one end of the light emitting diode is coupled to a ground voltage, the first transistor is coupled between a first data line of the plurality of data lines and the light emitting diode, a grid electrode of the first transistor is coupled with a first grid line of the plurality of grid lines and controlled by a driving signal provided by the first grid line, and one end of the storage capacitor is coupled with the first data line, and the other end of the storage capacitor is coupled between the light emitting diode and the ground voltage for storing charges; or (b)
Each pixel consists of a light emitting diode, a first transistor and a coupling capacitor, wherein the coupling capacitor is a coupling capacitor between the first data line and the second gate line, one end of the light emitting diode is coupled to a grounding voltage, the first transistor is coupled between the first data line of the plurality of data lines and the light emitting diode, and the gate of the first transistor is coupled with the first gate line of the plurality of gate lines and controlled by a driving signal provided by the first gate line;
the second transistor is coupled to the driving circuit through the multiplexer and receives the data signal provided by the driving circuit;
during the period that the switching signal is at a high level and charges the first data line, the third transistor is controlled by the reference signal to be turned on, and the third transistor detects a current of the first data line and outputs a feedback signal to the driving circuit to serve as a reference for compensation.
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| TW108109870A TWI736862B (en) | 2019-03-21 | 2019-03-21 | Light-emitting diode display panel |
| TW108109870 | 2019-03-21 |
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| CN113077754B (en) * | 2020-06-10 | 2022-09-13 | 友达光电股份有限公司 | Pixel driving circuit |
| TWI772888B (en) * | 2020-09-11 | 2022-08-01 | 友達光電股份有限公司 | Display panel and spliced panel |
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| CN110767151A (en) | 2020-02-07 |
| TW202036519A (en) | 2020-10-01 |
| TWI736862B (en) | 2021-08-21 |
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