TW202036519A - Light-emitting diode display panel - Google Patents

Abstract

A light-emitting diode (LED) display panel is disclosed. The LED display panel includes a plurality of data lines, a plurality of gate lines, a plurality of pixels and a second transistor. The plurality of pixels is disposed in an active area of the LED display panel. A first pixel of the pixels includes a LED and a first transistor. The LED is coupled to a ground voltage. The first transistor is coupled between a first data line of the data lines and the LED. A gate of the first transistor is coupled to a first gate line of the gate lines and controlled by a driving signal provided by the first gate line. The second transistor is disposed out of the active area. The second transistor is coupled to the first data line and a gate of the second transistor is controlled by a switching signal.

Description

LED display panel

The present invention is related to displays, and particularly to a light-emitting diode (LED) display panel.

Please refer to FIGS. 1 and 2. FIG. 1 is a schematic diagram of the pixel design of a conventional light emitting diode display panel; FIG. 2 is a timing diagram of the control signal of the second transistor in FIG.

As shown in FIG. 1, the pixel 1 of the current common light-emitting diode display panel adopts the "2T1C" architecture, that is, each pixel includes a first transistor T1, a second transistor T2, and a storage capacitor CS. Wherein, the first transistor T1 is arranged between the working voltage VDD and the light emitting diode LED, and the first transistor T1 is controlled by the gate voltage VG; the second transistor T2 is arranged on the gate of the first transistor T1 Between the second transistor T2 and the data signal VDAT, and the second transistor T2 is controlled by the drive signal S(N); one end of the storage capacitor CS is coupled between the second transistor T2 and the gate of the first transistor T1 and the storage capacitor The other end of CS is coupled between the first transistor T1 and the light-emitting diode LED.

Generally speaking, the conventional "2T1C" architecture is more suitable for pixels that adopt the voltage holding mode (Holding-type) imaging. However, since the driving current of the light-emitting diode LED (approximately mA level) is much greater than the driving current of the organic light-emitting diode (Organic Light-Emitting Diode, OLED) (approximately uA level), the voltage holding mode is adopted for light emission The total current of the diode display panel is too high and power consumption is increased.

In addition, since the width of the first transistor T1 provided between the working voltage VDD and the light-emitting diode LED in each pixel is relatively large, with the development trend of high-resolution display panels, when the pixel density ( When the PPI is increased, the circuit layout difficulty of the pixel will be greatly increased due to the limitation of various components and wiring, which needs to be overcome urgently.

Therefore, the present invention proposes a light emitting diode display panel to solve the above-mentioned problems encountered in the prior art.

A specific embodiment according to the present invention is a light emitting diode display panel. In this embodiment, the light emitting diode display panel includes a plurality of data lines, a plurality of gate lines, a plurality of pixels, and a second transistor. The plurality of pixels are arranged in the effective display area of the light emitting diode display panel. The first pixel of the plurality of pixels includes a light emitting diode and a first transistor. The light emitting diode is coupled to the ground voltage. The first transistor is coupled between the first data line of the plurality of data lines and the light emitting diode. The gate of the first transistor is coupled to the first gate line of the plurality of gate lines and is controlled by the driving signal provided by the first gate line. The second transistor is arranged outside the effective display area. The second transistor is coupled to the first data line and the gate of the second transistor is controlled by the switching signal.

In one embodiment, there is a coupling capacitor between the first data line and the first gate line for storing charge.

In one embodiment, the second pixel of the plurality of pixels includes another light emitting diode and another first transistor. The other light emitting diode is coupled to the ground voltage. The other first transistor is coupled between the first data line and the other light emitting diode, and the gate of the first transistor is coupled to the second gate line of the plurality of gate lines and controlled Another driving signal provided by the second gate line. The first pixel and the second pixel share the second transistor through the first data line.

In one embodiment, the first pixel further includes a storage capacitor, one end of which is coupled to the first data line and the other end of which is coupled between the light emitting diode and the ground voltage for storing charges.

In one embodiment, the second transistor is also coupled to the drive circuit and receives the data signal provided by the drive circuit. When the second transistor is turned on under the control of the switching signal, the second transistor outputs the data signal to the first data line.

In one embodiment, the light emitting diode display panel further includes a third transistor disposed outside the effective display area, the third transistor is coupled between the first data line and the driving circuit and the gate of the third transistor Extremely controlled by the reference signal.

In one embodiment, when the third transistor is controlled by the reference signal and is turned on, the third transistor detects the current of the first data line and outputs the feedback signal to the driving circuit as a reference for compensation.

In one embodiment, when the first transistor is controlled by the driving signal and turned on, the current through the first transistor drives the light-emitting diode to emit light.

In one embodiment, the light-emitting diode display panel further includes another second transistor, which is disposed outside the effective display area, and the other second transistor is coupled to the second data line among the plurality of data lines. The gate of the other second transistor is controlled by another switching signal.

In one embodiment, the third pixel and the fourth pixel of the plurality of pixels are coupled to the second data line and share the other second transistor through the second data line.

Compared with the prior art, the pixel design of the LED display panel of the present invention adopts the "1T1C" architecture or the "1T" architecture, instead of the traditional "2T1C" architecture, that is, each pixel includes the first electrical The crystal and storage capacitor may only include the first transistor, and share the second transistor outside the effective display area. Therefore, the circuit layout is easier. Even when the pixel density is increased, the circuit layout difficulty is not easily limited by The number of components and traces has been greatly increased, so it is suitable for high-resolution panel design.

In addition, since the light-emitting diode display panel of the present invention adopts the impulse driving mode (Impulse driving mode) to drive all the pixel partitions, the required current is lower than that of the traditional holding-type mode (Holding-type), so it is effective The total power consumption of the light-emitting diode display panel is reduced, and a multiplexer can be arranged between the driving circuit and the second transistor to reduce the number of required driving circuits.

The advantages and spirit of the present invention can be further understood from the following detailed description of the invention and the accompanying drawings.

Hereinafter, the present invention will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the present invention are shown. As those skilled in the art would realize, the described embodiments may be modified in various different ways without departing from the spirit or scope of the present invention.

In the drawings, some areas are enlarged for clarity. Throughout the specification, the same reference numerals denote the same elements. It should be understood that when an element such as a region or a substrate is referred to as being "on" or "connected (or referred to as coupled)" or "electrically connected" to another element, it may be directly connected to another element. It is connected to another element (or referred to as being coupled) or electrically connected, or an intermediate element may also exist. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. As used herein, "connected (or referred to as coupled)" can refer to physical and/or electrical connections.

A specific embodiment according to the present invention is a light emitting diode display panel. Please refer to FIG. 3. FIG. 3 is a schematic diagram of the light emitting diode display panel in this embodiment.

As shown in FIG. 3, the light-emitting diode display panel 3 includes a plurality of data lines DL(i-1)~DL(i), a plurality of gate lines GL(N-1)~GL(N), and a plurality of pictures. PX1~PX4 and a plurality of second transistors T2, where i and N are both positive integers. It should be noted that, although two data lines, two gate lines, four pixels, and two second transistors are taken as examples for description in this embodiment, the present invention is not limited thereto.

The light emitting diode display panel 3 includes an effective display area AA. The plurality of pixels PX1~PX4 are arranged in the effective display area AA of the light emitting diode display panel 3 and the plurality of second transistors T2 are arranged outside the effective display area AA of the light emitting diode display panel 3 .

The first data line DL(i-1) of the plurality of data lines DL(i-1)~DL(i) is coupled to the first pixel PX1 and the second pixel of the plurality of pixels PX1~PX4 PX2 and a second transistor T2 of the plurality of second transistors T2; the second data line DL(i) of the plurality of data lines DL(i-1)~DL(i) is coupled to the plurality of data lines DL(i-1)~DL(i) The third pixel PX3 and the fourth pixel PX4 among the pixels PX1~PX4 and the other second transistor T2 among the plurality of second transistors T2; the plurality of gate lines GL(N-1)~ The first gate line GL(N-1) in GL(N) is coupled to the first pixel PX1 and the third pixel PX3 in the plurality of pixels PX1~PX4; the plurality of gate lines GL(N -1) The second gate line GL(N) in ~GL(N) is coupled to the second pixel PX2 and the fourth pixel PX4 of the plurality of pixels PX1~PX4.

That is, the first pixel PX1 of the plurality of pixels PX1~PX4 is respectively coupled to the first data line DL(i-1) of the plurality of data lines DL(i-1)~DL(i) And the first gate line GL(N-1) of the plurality of gate lines GL(N-1)~GL(N); the second pixel PX2 of the plurality of pixels PX1~PX4 is respectively coupled The first data line DL(i-1) among the plurality of data lines DL(i-1)~DL(i) and the second among the plurality of gate lines GL(N-1)~GL(N) Gate line GL(N); the third pixel PX3 of the plurality of pixels PX1~PX4 is respectively coupled to the second data line DL( of the plurality of data lines DL(i-1)~DL(i) i) and the first gate line GL(N-1) among the plurality of gate lines GL(N-1)~GL(N); the fourth pixel PX4 among the plurality of pixels PX1~PX4 respectively Coupled to the second data line DL(i) of the plurality of data lines DL(i-1)~DL(i) and the second of the plurality of gate lines GL(N-1)~GL(N) Gate line GL(N). The first pixel PX1 and the second pixel PX2 of the plurality of pixels PX1~PX4 share the second transistor T2 coupled to the first data line DL(i-1); among the plurality of pixels PX1~PX4 The third pixel PX3 and the fourth pixel PX4 share the second transistor T2 coupled to the second data line DL(i).

In this embodiment, the plurality of pixels PX1~PX4 all adopt the pixel design of the “1T1C” architecture, that is, each pixel PX1~PX4 includes a transistor and a capacitor.

Taking the first pixel PX1 as an example, the first pixel PX1 includes a light emitting diode LED, a first transistor T1 and a storage capacitor CS. The light emitting diode LED is coupled to the ground voltage VSS. The first transistor T1 is coupled between the first data line DL(i-1) among the plurality of data lines DL(i-1)~DL(i) and the light emitting diode LED. The gate of the first transistor T1 is coupled to the first gate line GL(N-1) among the plurality of gate lines GL(N-1)~GL(N) and controlled by the first gate line GL (N-1) The drive signal S(N-1) provided. One end of the storage capacitor CS is coupled to the first data line DL(i-1) and the other end of the storage capacitor CS is coupled between the light emitting diode LED and the ground voltage VSS for storing charges.

Similarly, if the second pixel PX2 is taken as an example, the second pixel PX2 also includes a light emitting diode LED, a first transistor T1 and a storage capacitor CS. The light emitting diode LED is coupled to the ground voltage VSS. The first transistor T1 is coupled between the first data line DL(i-1) among the plurality of data lines DL(i-1)~DL(i) and the light emitting diode LED. The gate of the first transistor T1 is coupled to the second gate line GL(N) among the plurality of gate lines GL(N-1)~GL(N) and is controlled by the second gate line GL(N) ) The drive signal S(N) provided. One end of the storage capacitor CS is coupled to the first data line DL(i-1) and the other end of the storage capacitor CS is coupled between the light emitting diode LED and the ground voltage VSS for storing charges.

Similarly, if the third pixel PX3 is taken as an example, the third pixel PX3 also includes a light emitting diode LED, a first transistor T1 and a storage capacitor CS. The light emitting diode LED is coupled to the ground voltage VSS. The first transistor T1 is coupled between the second data line DL(i) among the plurality of data lines DL(i-1)~DL(i) and the light emitting diode LED. The gate of the first transistor T1 is coupled to the first gate line GL(N-1) among the plurality of gate lines GL(N-1)~GL(N) and controlled by the first gate line GL (N-1) The drive signal S(N-1) provided. One end of the storage capacitor CS is coupled to the second data line DL(i) and the other end of the storage capacitor CS is coupled between the light emitting diode LED and the ground voltage VSS for storing charges.

Similarly, if the fourth pixel PX4 is taken as an example, the fourth pixel PX4 also includes a light-emitting diode LED, a first transistor T1 and a storage capacitor CS. The light emitting diode LED is coupled to the ground voltage VSS. The first transistor T1 is coupled between the second data line DL(i) among the plurality of data lines DL(i-1)~DL(i) and the light emitting diode LED. The gate of the first transistor T1 is coupled to the second gate line GL(N) among the plurality of gate lines GL(N-1)~GL(N) and is controlled by the second gate line GL(N) ) The drive signal S(N) provided. One end of the storage capacitor CS is coupled to the second data line DL(i) and the other end of the storage capacitor CS is coupled between the light emitting diode LED and the ground voltage VSS for storing charges.

The second transistor T2 coupled to the first data line DL(i-1) is also coupled to the data signal VDAT and the gate of this second transistor T2 is controlled by the switching signal SW(i-1); coupled to the second The second transistor T2 of the data line DL(i) is also coupled to the data signal VDAT and the gate of this second transistor T2 is controlled by the switching signal SW(i).

In practical applications, the plurality of second transistors T2 can be coupled to the drive circuit through a multiplexer and receive the data signal VDAT provided by the drive circuit, and the multiplexer can be one-to-two, one-to-three or other designs. In order to reduce the number of driving circuits, but not limited to this.

Please refer to Figure 1 and Figure 2 at the same time. Taking the first pixel PX1 as an example, when the switching signal SW(i-1) changes from the low level VGL to the high level VGH, the other switching signal SW(i) still maintains the low level VGL and is controlled by the switching signal SW The second transistor T2 of (i-1) is turned on to charge the storage capacitor CS in the first pixel PX1 and the second pixel PX2 through the first data line DL(i-1). After the switching signal SW(i-1) changes from the high level VGH to the low level VGL, when another switching signal SW(i) changes from the low level VGL to the high level VGH, it is controlled by the switching signal SW(i) The second transistor T2 is turned on, so as to charge the storage capacitor CS in the third pixel PX3 and the fourth pixel PX4 through the second data line DL(i).

Then, when the driving signal S(N-1) that was originally maintained at the low level VGL changes to the high level VGH, the first transistor T1 in the first pixel PX1 controlled by the driving signal S(N-1) Will be turned on, so that the charge stored in the storage capacitor CS in the first pixel PX1 and the second pixel PX2 flows to the first transistor T1 in the first pixel PX1 to form a current I through the first transistor T1, Drive the light-emitting diode LED in the first pixel PX1 to emit light. Therefore, for the first pixel PX1, the period during which the driving signal S(N-1) is at the high level VGH can be referred to as the "light emitting period LEP".

Similarly, for the third pixel PX3, when the driving signal S(N-1) is at the high level VGH, the first transistor in the third pixel PX3 is controlled by the driving signal S(N-1) T1 will also be turned on, so that the charge stored in the storage capacitor CS in the third pixel PX3 and the fourth pixel PX4 flows to the first transistor T1 in the third pixel PX3 to form a current I through the first transistor T1 , To drive the light emitting diode LED in the third pixel PX3 to emit light. Therefore, for the third pixel PX3, the period during which the driving signal S(N-1) is at the high level VGH can also be referred to as the "light emitting period LEP".

Similarly, for the second pixel PX2, when the driving signal S(N) is at a high level VGH, the first transistor T1 in the second pixel PX2 controlled by the driving signal S(N) will also be turned on , So that the charge stored in the storage capacitor CS in the first pixel PX1 and the second pixel PX2 flows to the first transistor T1 in the second pixel PX2 to form a current I through the first transistor T1 to drive the The light-emitting diode LED in the two-pixel PX2 emits light. Therefore, for the second pixel PX2, the period during which the driving signal S(N) is at the high level VGH can also be referred to as the "light emitting period LEP".

Similarly, for the fourth pixel PX4, when the driving signal S(N) is at the high level VGH, the first transistor T1 in the fourth pixel PX4 controlled by the driving signal S(N) will also be turned on , So that the charge stored in the storage capacitor CS in the third pixel PX3 and the fourth pixel PX4 flows to the first transistor T1 in the fourth pixel PX4 to form a current I passing through the first transistor T1 to drive the first transistor T1 The light-emitting diode LED in the four-pixel PX4 emits light. Therefore, for the fourth pixel PX4, the period during which the driving signal S(N) is at the high level VGH can also be referred to as the "light emitting period LEP".

In another specific embodiment, please refer to FIG. 5, the plurality of pixels PX1~PX4 in the LED display panel 5 adopt the pixel design of the "1T" architecture, that is, the LED display panel 5 Each of the pixels PX1 to PX4 includes the first transistor T1, but does not include the storage capacitor CS in the previous embodiment.

Please refer to Figure 5 and Figure 6 at the same time. Taking the first pixel PX1 as an example, when the switching signal SW(i-1) changes from the low level VGL to the high level VGH, the other switching signal SW(i) still maintains the low level VGL and is controlled by the switching signal SW The second transistor T2 of (i-1) will be turned on. At this time, the charge transferred through the first data line DL(i-1) can be stored in the coupling capacitor CC, such as the first data line DL(i-1) The coupling capacitor CC between the first gate line GL(N-1) and the coupling capacitor CC between the first data line DL(i-1) and the second gate line GL(N), but not Is limited. In fact, the coupling capacitor CC can also be other capacitors coupled to the first data line DL(i-1), but is not limited to this.

After the switching signal SW(i-1) changes from the high level VGH to the low level VGL, when another switching signal SW(i) changes from the low level VGL to the high level VGH, it is controlled by the switching signal SW(i) The second transistor T2 will be turned on. At this time, the charge transferred through the second data line DL(i) can be stored in the coupling capacitor CC, such as the second data line DL(i) and the first gate line GL(N- 1) The coupling capacitor CC between the second data line DL(i) and the second gate line GL(N), but not limited to this. In fact, the coupling capacitor CC can also be other capacitors coupled to the second data line DL(i), but it is not limited to this.

Then, when the driving signal S(N-1) that was originally maintained at the low level VGL changes to the high level VGH, the first transistor T1 in the first pixel PX1 controlled by the driving signal S(N-1) Will be turned on, so that the coupling capacitor CC stored between the first data line DL(i-1) and the first gate line GL(N-1) and the first data line DL(i-1) and the second gate The charge of the coupling capacitor CC between the lines GL(N) flows to the first transistor T1 in the first pixel PX1 to form a current I through the first transistor T1 to drive the light emitting diode in the first pixel PX1 Body LED glows. Therefore, for the first pixel PX1, the period during which the driving signal S(N-1) is at the high level VGH can be referred to as the "light emitting period LEP".

Similarly, for the third pixel PX3, when the driving signal S(N-1) is at the high level VGH, the first transistor in the third pixel PX3 is controlled by the driving signal S(N-1) T1 will also be turned on, so that the coupling capacitor CC stored between the second data line DL(i) and the first gate line GL(N-1) and the second data line DL(i) and the second gate line GL The charge of the coupling capacitor CC between (N) flows to the first transistor T1 in the third pixel PX3 to form a current I through the first transistor T1 to drive the light-emitting diode LED in the third pixel PX3 Glow. Therefore, for the third pixel PX3, the period during which the driving signal S(N-1) is at the high level VGH can also be referred to as the "light emitting period LEP".

Similarly, for the second pixel PX2, when the driving signal S(N) is at a high level VGH, the first transistor T1 in the second pixel PX2 controlled by the driving signal S(N) will also be turned on , So that the coupling capacitor CC stored between the first data line DL(i-1) and the first gate line GL(N-1) and the first data line DL(i-1) and the second gate line GL The charge of the coupling capacitor CC between (N) flows to the first transistor T1 in the second pixel PX2 to form a current I through the first transistor T1 to drive the light-emitting diode LED in the second pixel PX2 Glow. Therefore, for the second pixel PX2, the period during which the driving signal S(N) is at the high level VGH can also be referred to as the "light emitting period LEP".

Similarly, for the fourth pixel PX4, when the driving signal S(N) is at the high level VGH, the first transistor T1 in the fourth pixel PX4 controlled by the driving signal S(N) will also be turned on , So that the coupling capacitor CC stored between the second data line DL(i) and the first gate line GL(N-1) and the second data line DL(i) and the second gate line GL(N) The charge of the coupling capacitor CC flows to the first transistor T1 in the fourth pixel PX4 to form a current I through the first transistor T1 to drive the light emitting diode LED in the fourth pixel PX4 to emit light. Therefore, for the fourth pixel PX4, the period during which the driving signal S(N) is at the high level VGH can also be referred to as the "light emitting period LEP".

In another specific embodiment, referring to FIG. 7, the plurality of pixels PX1~PX4 in the light emitting diode display panel 7 and the plurality of pixels PX1~ in the light emitting diode display panel 3 of FIG. The PX4 also adopts the pixel design of the "1T1C" architecture, that is, each pixel PX1~PX4 in the light emitting diode display panel 7 includes the first transistor T1 and the storage capacitor CS.

It should be noted that the LED display panel 7 of FIG. 7 is different from the LED display panel 3 of FIG. 3 in that: the LED display panel 7 of FIG. 7 is also designed to compensate around the effective display area AA The circuit, for example, the light emitting diode display panel 7 of FIG. 7 further includes a plurality of third transistors T3 arranged outside the effective display area AA.

As shown in FIG. 7, one of the plurality of third transistors T3 included in the light emitting diode display panel 7 is coupled to the first data line DL(i-1) and the driving circuit IC. Between and the gate of the third transistor T3 is controlled by the reference signal VREF; the other third transistor T3 of the plurality of third transistors T3 is coupled to the second data line DL(i) and drives The gate of the third transistor T3 between the circuits IC is also controlled by the reference signal VREF.

Please also refer to Figure 7 and Figure 8 at the same time. When the switching signal SW(i-1) is at the high level VGH and the first data line DL(i-1) is charged, when the reference signal VREF changes from the low level VGL to the high level VGH, the first data line is coupled The third transistor T3 of DL(i-1) is controlled by the reference signal VREF and turned on, so as to detect the current of the first data line DL(i-1) and output the feedback signal to the driving circuit IC to perform as the driving circuit IC Reference for compensation.

Similarly, when the switching signal SW(i) is at the high level VGH and the second data line DL(i) is charged, when the reference signal VREF changes from the low level VGL to the high level VGH, the second data line DL is coupled The third transistor T3 of (i) is controlled by the reference signal VREF and turned on, so as to detect the current of the second data line DL(i) and output a feedback signal to the driving circuit IC as a reference for the compensation of the driving circuit IC.

Compared with the prior art, the pixel design of the LED display panel of the present invention adopts the "1T1C" architecture or the "1T" architecture, instead of the traditional "2T1C" architecture, that is, each pixel includes the first electrical The crystal and storage capacitor may only include the first transistor, and share the second transistor outside the effective display area. Therefore, the circuit layout is easier. Even when the pixel density is increased, the circuit layout difficulty is not easily limited by The number of components and traces has been greatly increased, so it is suitable for high-resolution panel design.

In addition, since the light-emitting diode display panel of the present invention adopts the impulse driving mode (Impulse driving mode) to drive all the pixel partitions, the required current is lower than that of the traditional holding-type mode (Holding-type), so it is effective The total power consumption of the light-emitting diode display panel is reduced, and a multiplexer can be arranged between the driving circuit and the second transistor to reduce the number of required driving circuits.

Through the detailed description of the preferred embodiments above, it is hoped that the characteristics and spirit of the present invention can be described more clearly, and the scope of the present invention is not limited by the preferred embodiments disclosed above. On the contrary, its purpose is to cover various changes and equivalent arrangements within the scope of the patent application for the present invention.

1: Pixel VDD: working voltage VD: Drain voltage VS: source voltage VG: Gate voltage 3, 5, 7: LED display panel AA: effective display area PX1~PX4: pixel DL(i-1)~DL(i): data line GL(N-1)~GL(N): gate line S(N-1)~S(N+1): drive signal SW(i-1)~SW(i): switch signal T1: first transistor LED: light emitting diode CC: Coupling capacitor VSS: Ground voltage T2: second transistor VDAT: Data signal CS: storage capacitor I: current VGH: High level VGL: Low level LEP: During light emission VREF: Reference voltage T3: third transistor IC: drive circuit

FIG. 1 is a schematic diagram showing the pixel design of a common LED display panel.

FIG. 2 is a timing diagram of the control signal of the second transistor in FIG. 1.

FIG. 3 is a schematic diagram of a light emitting diode display panel according to a specific embodiment of the invention.

FIG. 4 is a timing diagram of the switching signal, the data signal and the driving signal in FIG. 3.

FIG. 5 is a schematic diagram of a light emitting diode display panel according to another embodiment of the invention.

FIG. 6 is a timing diagram of the switching signal, the data signal and the driving signal in FIG. 5.

FIG. 7 is a schematic diagram of a light emitting diode display panel according to another embodiment of the present invention.

FIG. 8 is a timing diagram of the switching signal, the data signal, the driving signal and the reference voltage in FIG. 7.

5: LED display panel

AA: effective display area

PX1~PX4: pixel

DL(i-1)~DL(i): data line

GL(N-1)~GL(N): gate line

S(N-1)~S(N): drive signal

SW(i-1)~SW(i): switch signal

T1: first transistor

LED: light emitting diode

CC: Coupling capacitor

VSS: Ground voltage

T2: second transistor

VDAT: Data signal

Claims (10)

A light-emitting diode display panel, comprising: a plurality of data lines; a plurality of gate lines; a plurality of pixels, arranged in an effective display area of the light-emitting diode display panel, one of the plurality of pixels The first pixel includes: a light emitting diode coupled to a ground voltage; and a first transistor coupled between a first data line of the plurality of data lines and the light emitting diode, the The gate of the first transistor is coupled to a first gate line of the plurality of gate lines and is controlled by a driving signal provided by the first gate line; and a second transistor is disposed on the Outside the effective display area, the second transistor is coupled to the first data line and the gate of the second transistor is controlled by a switching signal. According to the light emitting diode display panel described in claim 1, wherein a coupling capacitor is provided between the first data line and the first gate line for storing electric charges. According to the light-emitting diode display panel described in claim 1, wherein one of the second pixels of the plurality of pixels includes: another light-emitting diode coupled to the ground voltage; and another first A transistor is coupled between the first data line and the other light emitting diode, and the gate of the first transistor is coupled to a second gate line of the plurality of gate lines and controlled by Another driving signal provided by the second gate line; wherein, the first pixel and the second pixel share the second transistor through the first data line. The light-emitting diode display panel described in claim 1, wherein the first pixel further includes: a storage capacitor, one end of which is coupled to the first data line and the other end of which is coupled to the light-emitting diode Between the body and the ground voltage, it is used to store charges. The light-emitting diode display panel described in claim 1, wherein the second transistor is also coupled to a driving circuit and receives a data signal provided by the driving circuit. When the second transistor is controlled by When the switching signal is turned on, the second transistor outputs the data signal to the first data line. The light-emitting diode display panel described in item 1 of the scope of patent application further includes: a third transistor disposed outside the effective display area, and the third transistor is coupled to the first data line and a Between the driving circuits and the gate of the third transistor is controlled by a reference signal. According to the light-emitting diode display panel described in claim 6, wherein when the third transistor is controlled by the reference signal and is turned on, the third transistor detects a current of the first data line and outputs A feedback signal is sent to the driving circuit as a reference for compensation. The light-emitting diode display panel described in claim 1, wherein when the first transistor is turned on under the control of the driving signal, the light-emitting diode is driven to emit light by a current of the first transistor . The light-emitting diode display panel described in item 1 of the scope of patent application further includes: another second transistor disposed outside the effective display area, and the other second transistor is coupled to the plurality of data lines One of the second data lines and the gate of the other second transistor are controlled by another switching signal. The light-emitting diode display panel described in item 9 of the scope of patent application, wherein a third pixel and a fourth pixel of the plurality of pixels are both coupled to the second data line and pass through the second data The wires share the other second transistor.

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