TWI527012B - Pixel circuit of light-emitting diode and driving method thereof - Google Patents

Pixel circuit of light-emitting diode and driving method thereof Download PDF

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TWI527012B
TWI527012B TW103123028A TW103123028A TWI527012B TW I527012 B TWI527012 B TW I527012B TW 103123028 A TW103123028 A TW 103123028A TW 103123028 A TW103123028 A TW 103123028A TW I527012 B TWI527012 B TW I527012B
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transistor
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during
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TW103123028A
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TW201602989A (en
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李建亞
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友達光電股份有限公司
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Description

發光二極體畫素電路及其驅動方法 Light-emitting diode pixel circuit and driving method thereof

本發明是有關於一種畫素電路,尤其是有關於一種發光二極體畫素電路及其驅動方法。 The present invention relates to a pixel circuit, and more particularly to a light emitting diode pixel circuit and a driving method thereof.

在發光二極體畫素電路之中,可以用一個發光二極體搭配四個電晶體及兩個電容的元件配置方式來實現其畫素電路架構,也就是採用所謂的4T2C電路架構。在此4T2C電路架構當中,其中一個電晶體係用以作為驅動電晶體,且其中一個電容係電性耦接於此驅動電晶體的控制端與源極端之間。當此4T2C電路架構於資料寫入完畢而要使發光二極體發光時,是透過使驅動電晶體的控制端浮接(floating),並利用電性耦接於驅動電晶體的控制端與源極端之間的電容來將驅動電晶體之源極端的電壓變化耦合至驅動電晶體的控制端,藉以補償(或稱消除)發光二極體本身的跨壓及驅動電晶體的臨界電壓(Vt)對於發光亮度的影響。 In the light-emitting diode pixel circuit, a pixel configuration can be realized by using a light-emitting diode with four transistors and two capacitors, that is, using a so-called 4T2C circuit structure. In the 4T2C circuit architecture, one of the electro-optic systems is used as a driving transistor, and one of the capacitors is electrically coupled between the control terminal and the source terminal of the driving transistor. When the 4T2C circuit structure is used to enable the light emitting diode to emit light after the data is written, the control terminal of the driving transistor is floated and electrically coupled to the control terminal and the source of the driving transistor. Capacitance between the extremes to couple the voltage change of the source terminal of the driving transistor to the control terminal of the driving transistor, thereby compensating (or eliminating) the voltage across the LED itself and the threshold voltage (Vt) of the driving transistor The effect on the brightness of the light.

然而,由於每個電晶體本身即存在有寄生電容,因此在使發光二極體發光時,電性耦接於驅動電晶體的控制端與源極端之間的電容自驅動電晶體之源極端所耦合至控制端的電壓,就會被上述之寄生電容分壓(此可稱為寄生電容效 應),造成上述補償的效果不佳。為了解決上述的問題,就必須增加電性耦接於驅動電晶體的控制端與源極端之間的電容的電容值,例如加大驅動電晶體的控制端與源極端之間的電容的電容值至Ct,可是此舉卻會進一步衍生出發光二極體的發光電流減少,以及使補償速度變慢等問題。 However, since each transistor itself has a parasitic capacitance, when the light emitting diode is illuminated, the capacitor is electrically coupled between the control terminal and the source terminal of the driving transistor from the source terminal of the driving transistor. The voltage coupled to the control terminal is divided by the parasitic capacitance described above (this can be called parasitic capacitance effect). Yes), the effect of the above compensation is not good. In order to solve the above problem, it is necessary to increase the capacitance value of the capacitance electrically coupled between the control terminal and the source terminal of the driving transistor, for example, increase the capacitance value of the capacitance between the control terminal and the source terminal of the driving transistor. To Ct, this will further lead to the reduction of the illuminating current of the illuminating diode and the slowing of the compensation speed.

本發明提供一種發光二極體畫素電路,其可避免發生發光二極體的發光電流減少,以及補償速度變慢等問題。 The invention provides a light-emitting diode pixel circuit, which can avoid the problem that the light-emitting current of the light-emitting diode is reduced and the compensation speed is slow.

本發明另提供一種適用於上述發光二極體畫素電路的驅動方法。 The present invention further provides a driving method suitable for the above-described light emitting diode pixel circuit.

本發明提出一種發光二極體畫素電路,其包括第一電晶體、第二電晶體、第三電晶體、第四電晶體(用以作為驅動電晶體)、第一電容、第二電容、以及發光二極體。第一電晶體具有控制端、第一端以及第二端,且第一電晶體的控制端係電性耦接於第一控制訊號,而第一電晶體的第一端係用以接收資料電位或是參考電位。第二電晶體具有控制端、第一端、以及第二端,且第二電晶體的控制端係電性耦接於第二控制訊號,而第二電晶體的第一端係電性耦接於第一操作電源。第三電晶體具有控制端、第一端、以及第二端,且第三電晶體的控制端係電性耦接於第三控制訊號。第四電晶體具有控制端、第一端、以及第二端,且第四電晶體的第一端係電性耦接於第二電晶體的第二端,第四電晶體的第二端係電性耦接於第三電晶體的第二端,而第四電晶體的控制端係電性耦接於第一電晶體的第二端。第一電容具有第一端及第二端,第一電容的第一端係電性耦接於第四電晶體的控制端,且第一電容的第二端、第四電晶體的第二端以及第三電 晶體的第二端係共同電性耦接。第二電容具有第一端以及第二端,且第二電容的第一端、第一電晶體的第二端以及第一電容的第一端係共同電性耦接,而第二電容的第二端係電性耦接於第三電晶體的第一端。此外,第二電容的電容值大於第一電容的電容值。發光二極體具有第一端以及第二端,且發光二極體的第一端係電性耦接於第四電晶體的第二端,而發光二極體的第二端係電性耦接於第二操作電源。 The present invention provides a light emitting diode pixel circuit including a first transistor, a second transistor, a third transistor, a fourth transistor (used as a driving transistor), a first capacitor, a second capacitor, And a light-emitting diode. The first transistor has a control end, a first end, and a second end, and the control end of the first transistor is electrically coupled to the first control signal, and the first end of the first transistor is configured to receive the data potential Or reference potential. The second transistor has a control end, a first end, and a second end, and the control end of the second transistor is electrically coupled to the second control signal, and the first end of the second transistor is electrically coupled The first operating power supply. The third transistor has a control end, a first end, and a second end, and the control end of the third transistor is electrically coupled to the third control signal. The fourth transistor has a control end, a first end, and a second end, and the first end of the fourth transistor is electrically coupled to the second end of the second transistor, and the second end of the fourth transistor The second end of the third transistor is electrically coupled to the second end of the first transistor. The first capacitor has a first end and a second end. The first end of the first capacitor is electrically coupled to the control end of the fourth transistor, and the second end of the first capacitor and the second end of the fourth transistor And the third electricity The second ends of the crystals are electrically coupled together. The second capacitor has a first end and a second end, and the first end of the second capacitor, the second end of the first transistor, and the first end of the first capacitor are electrically coupled together, and the second capacitor The two ends are electrically coupled to the first end of the third transistor. In addition, the capacitance value of the second capacitor is greater than the capacitance value of the first capacitor. The light emitting diode has a first end and a second end, and the first end of the light emitting diode is electrically coupled to the second end of the fourth transistor, and the second end of the light emitting diode is electrically coupled Connected to the second operating power supply.

本發明又提出一種發光二極體畫素電路,其除了包括有上述之第一電晶體、第二電晶體、第三電晶體、第四電晶體、第一電容、第二電容、以及發光二極體,並具有相同的電性耦接關係之外,更包括一第五電晶體。此第五電晶體具有控制端、第一端及第二端,且第五電晶體的控制端接收第四控制訊號,第五電晶體的第一端電性耦接預設電位,而第五電晶體的第二端電性耦接於第三電晶體的第一端。 The invention further provides a light emitting diode pixel circuit, which comprises the above first transistor, second transistor, third transistor, fourth transistor, first capacitor, second capacitor, and light emitting diode In addition to the same electrical coupling relationship, the polar body further includes a fifth transistor. The fifth transistor has a control end, a first end and a second end, and the control end of the fifth transistor receives the fourth control signal, the first end of the fifth transistor is electrically coupled to the preset potential, and the fifth The second end of the transistor is electrically coupled to the first end of the third transistor.

本發明又另提出一種發光二極體畫素電路,其包括:第一電晶體、第二電晶體、第三電晶體(用以作為驅動電晶體)、發光二極體以及電容模組。第一電晶體具有控制端、第一端以及第二端,且第一電晶體的控制端係電性耦接於第一控制訊號,而第一電晶體的第一端係用以接收資料電位或是參考電位。第二電晶體具有控制端、第一端以及第二端,且第二電晶體的控制端係電性耦接於第二控制訊號,而第二電晶體的第一端係電性耦接於第一操作電源。第三電晶體具有控制端、第一端以及第二端,且第三電晶體的第一端係電性耦接於第二電晶體的第二端,而第三電晶體的控制端係電性耦接於第一電晶體的第二端。發光二極體具有第一端以及第二端,且發光二極體的第一端係電性耦接於第三電晶體的第二端,而發光二極體的第二端係電性耦接於第二操作電源。電容模組係電性耦接於第三電晶體的控制端與第二端之 間,且電容模組用以提供給第三電晶體的控制端與第二端之間一個等效電容,而電容模組在二極體畫素電路處於重置期間與發光期間時所提供之等效電容的值大於二極體畫素電路處於補償期間與資料寫入期間時所提供之等效電容的值。 The invention further provides a light emitting diode pixel circuit, comprising: a first transistor, a second transistor, a third transistor (used as a driving transistor), a light emitting diode and a capacitor module. The first transistor has a control end, a first end, and a second end, and the control end of the first transistor is electrically coupled to the first control signal, and the first end of the first transistor is configured to receive the data potential Or reference potential. The second transistor has a control end, a first end, and a second end, and the control end of the second transistor is electrically coupled to the second control signal, and the first end of the second transistor is electrically coupled to the second transistor The first operating power supply. The third transistor has a control end, a first end and a second end, and the first end of the third transistor is electrically coupled to the second end of the second transistor, and the control end of the third transistor is electrically The second end of the first transistor is coupled to the first transistor. The light emitting diode has a first end and a second end, and the first end of the light emitting diode is electrically coupled to the second end of the third transistor, and the second end of the light emitting diode is electrically coupled Connected to the second operating power supply. The capacitor module is electrically coupled to the control end and the second end of the third transistor And the capacitor module is configured to provide an equivalent capacitance between the control end and the second end of the third transistor, and the capacitor module is provided during the reset period and the illumination period of the diode pixel circuit The value of the equivalent capacitance is greater than the value of the equivalent capacitance provided by the diode pixel circuit during the compensation period and during the data write period.

本發明再提出一種發光二極體畫素電路的驅動方法,用以驅動上述之具有第一至第四電晶體的發光二極體畫素電路。此驅動方法包括:於重置期間中,使第一操作電源提供第一電位,並導通第一電晶體、第二電晶體與第三電晶體,且同時提供參考電位至第一電晶體的第一端;於補償期間中,使第一操作電源提供第二電位,此第二電位大於前述之第一電位,並導通第一電晶體與第二電晶體,且同時關閉第三電晶體,並提供參考電位至第一電晶體的第一端;於資料寫入期間中,使第一操作電源提供第二電位,並導通第一電晶體與第三電晶體,以及關閉第二電晶體,其中第一電晶體與第三電晶體並不同時導通,且第一電晶體之導通時間先於第三電晶體之導通時間,並在第一電晶體導通時提供資料電位至第一電晶體的第一端;以及,於發光期間中,使第一操作電源提供第二電位,並關閉第一電晶體,以及導通第二電晶體與第三電晶體,並提供參考電位至第一電晶體的第一端。其中,重置期間先於補償期間,補償期間先於資料寫入期間,資料寫入期間先於發光期間。 The invention further provides a driving method of a light emitting diode pixel circuit for driving the above-mentioned light emitting diode pixel circuit having first to fourth transistors. The driving method includes: providing a first operating power source with a first potential during a reset period, and turning on the first transistor, the second transistor, and the third transistor, and simultaneously providing a reference potential to the first transistor One end; during the compensation period, causing the first operating power source to provide a second potential, the second potential being greater than the first potential, and turning on the first transistor and the second transistor, and simultaneously turning off the third transistor, and Providing a reference potential to the first end of the first transistor; during the data writing period, causing the first operating power source to provide the second potential, and turning on the first transistor and the third transistor, and turning off the second transistor, wherein The first transistor and the third transistor are not simultaneously turned on, and the on-time of the first transistor is prior to the on-time of the third transistor, and the data potential is supplied to the first transistor when the first transistor is turned on And one end; and, during the illuminating period, causing the first operating power source to provide the second potential, and turning off the first transistor, and turning on the second transistor and the third transistor, and providing the reference potential to the first transistor End. Wherein, the reset period precedes the compensation period, the compensation period precedes the data writing period, and the data writing period precedes the lighting period.

本發明又再提出一種發光二極體畫素電路的驅動方法,用以驅動上述之具有第一至第五電晶體的發光二極體畫素電路,此驅動方法包括:於重置期間中,導通第一電晶體、第三電晶體與第五電晶體,同時提供參考電位至第一電晶體的第一端;於補償期間中,導通第一電晶體與第二電晶體,同時關閉第三電晶體與第五電晶體,並提供參考電位至第一電晶體的第一端;於資料寫入期間中,導通第一電晶 體與第三電晶體,以及關閉第二電晶體與第五電晶體,其中第一電晶體與第三電晶體並不同時導通,且第一電晶體之導通時間先於第三電晶體之導通時間,並在第一電晶體導通時提供資料電位至第一電晶體的第一端;以及,於發光期間中,關閉第一電晶體與第五電晶體,並導通第二電晶體與第三電晶體,以及提供參考電位至第一電晶體的第一端。其中,重置期間先於補償期間,補償期間先於資料寫入期間,資料寫入期間先於發光期間。 The present invention further provides a driving method for a light emitting diode pixel circuit for driving the above-described light emitting diode pixel circuit having first to fifth transistors, and the driving method includes: during the reset period, Turning on the first transistor, the third transistor and the fifth transistor while providing a reference potential to the first end of the first transistor; during the compensation period, turning on the first transistor and the second transistor while turning off the third a transistor and a fifth transistor, and providing a reference potential to the first end of the first transistor; during the data writing period, turning on the first transistor And a third transistor, and closing the second transistor and the fifth transistor, wherein the first transistor and the third transistor are not simultaneously turned on, and the on time of the first transistor is prior to the conduction of the third transistor Time, and providing a data potential to the first end of the first transistor when the first transistor is turned on; and, during the illuminating period, turning off the first transistor and the fifth transistor, and turning on the second transistor and the third a transistor, and providing a reference potential to the first end of the first transistor. Wherein, the reset period precedes the compensation period, the compensation period precedes the data writing period, and the data writing period precedes the lighting period.

在本發明之發光二極體畫素電路的電路架構中,係採用例如是由二個電容與一個電晶體所構成的電容模組來電性耦接於驅動電晶體的控制端與源極端之間,並利用此電晶體來決定是否讓上述二個電容皆電性耦接於驅動電晶體的控制端與源極端之間,或是僅讓其中一個電容電性耦接於驅動電晶體的控制端與源極端之間,藉以在發光二極體畫素電路的不同操作期間中改變電性耦接於驅動電晶體的控制端與源極端之間的等效電容的容值大小。據此,只要在重置期間與發光期間中導通此電晶體而使得上述二個電容並聯,並在其餘二個期間中關閉此電晶體,那麼本發明之發光二極體畫素電路便可避免發生習知技術中之發光二極體的發光電流減少,以及補償速度變慢等問題。 In the circuit architecture of the illuminating diode pixel circuit of the present invention, a capacitor module composed of, for example, two capacitors and one transistor is electrically coupled between the control terminal and the source terminal of the driving transistor. And using the transistor to determine whether the two capacitors are electrically coupled between the control terminal and the source terminal of the driving transistor, or only one of the capacitors is electrically coupled to the control terminal of the driving transistor. Between the source terminal and the source terminal, the capacitance value of the equivalent capacitance electrically coupled between the control terminal and the source terminal of the driving transistor is changed during different operation periods of the light emitting diode pixel circuit. Accordingly, the light-emitting diode pixel circuit of the present invention can be avoided as long as the two capacitors are connected in parallel during the reset period and during the light-emitting period, and the two capacitors are turned off in parallel during the remaining two periods. There is a problem that the luminous current of the light-emitting diode in the conventional technique is reduced, and the compensation speed is slow.

100、200‧‧‧發光二極體畫素驅動電路 100,200‧‧‧Light emitting diode driving circuit

11、12、13、14、15‧‧‧電晶體 11, 12, 13, 14, 15‧‧‧ transistors

C1、C2、C3‧‧‧電容 C1, C2, C3‧‧‧ capacitors

20‧‧‧發光二極體 20‧‧‧Lighting diode

110、120、130、140、150‧‧‧控制端 110, 120, 130, 140, 150‧‧‧ control terminals

111、121、131、141、151、C11、C21、C31、201‧‧‧第一端 111, 121, 131, 141, 151, C11, C21, C31, 201‧‧‧ first end

112、122、132、142、152、C12、C22、C32、202‧‧‧第二端 112, 122, 132, 142, 152, C12, C22, C32, 202‧‧‧ second end

Scan、EM、Reset1、Reset2‧‧‧控制訊號 Scan, EM, Reset1, Reset2‧‧‧ control signals

Data‧‧‧資料訊號 Data‧‧‧Information Signal

Vdata‧‧‧資料電位 Vdata‧‧‧ data potential

Vref‧‧‧參考電位 Vref‧‧‧ reference potential

Vsus‧‧‧預設電位 Vsus‧‧‧Preset potential

OVDD、OVSS‧‧‧操作電源 OVDD, OVSS‧‧‧ operating power supply

OVDDH、OVDDL、H、L‧‧‧電位 OVDDH, OVDDL, H, L‧‧‧ potential

G、S‧‧‧節點 G, S‧‧‧ nodes

t‧‧‧預設時間 t‧‧‧Preset time

501、502、503、504、601、602、603、604‧‧‧步驟 501, 502, 503, 504, 601, 602, 603, 604‧ ‧ steps

圖1所繪示為本發明一實施例之發光二極體畫素電路的電路架構圖;圖2所繪示為圖1所示之發光二極體畫素電路的其中一種訊號時序圖; 圖3所繪示為本發明另一實施例之發光二極體畫素電路的電路架構圖;圖4所繪示為圖3所示之發光二極體畫素電路的其中一種訊號時序圖;圖5為本發明之其中一個發光二極體畫素電路的其中一個操作流程;圖6為本發明之另一個發光二極體畫素電路的其中一個操作流程。 FIG. 1 is a circuit diagram of a light-emitting diode pixel circuit according to an embodiment of the present invention; FIG. 2 is a timing diagram of one of the light-emitting diode pixel circuits shown in FIG. 1; FIG. 3 is a circuit diagram of a light-emitting diode pixel circuit according to another embodiment of the present invention; FIG. 4 is a timing diagram of one of the light-emitting diode pixel circuits shown in FIG. 3; FIG. 5 is one of the operational flows of one of the light-emitting diode pixel circuits of the present invention; FIG. 6 is one of the operational flows of another light-emitting diode pixel circuit of the present invention.

圖1所繪示為本發明一實施例之發光二極體畫素電路的電路架構圖。如圖1所示,發光二極體畫素電路100包括電晶體11、電晶體12、電晶體13、電晶體14(用以作為驅動電晶體)、電容C1、電容C2,以及發光二極體20。此外,在此例中,係以C3來表示發光二極體20本身固有之等效電容。另外,在此例中,電容C2的電容值係大於電容C1的電容值,且電容C1與C2二個加起來的電容值等於前述習知技術中,電性耦接於驅動電晶體的控制端與源極端之間的等效電容於容值增加後的電容值Ct。電晶體11具有控制端110、第一端111以及第二端112。電晶體11的控制端110係電性耦接於控制訊號Scan,以藉由控制訊號Scan導通或是關閉電晶體11。電晶體11的第一端111用以接收資料訊號Data,此資料訊號Data可以提供資料電位Vdata或是參考電位Vref至電晶體11的第一端111。 FIG. 1 is a circuit diagram of a light emitting diode pixel circuit according to an embodiment of the invention. As shown in FIG. 1, the LED pixel circuit 100 includes a transistor 11, a transistor 12, a transistor 13, a transistor 14 (used as a driving transistor), a capacitor C1, a capacitor C2, and a light-emitting diode. 20. Further, in this example, the equivalent capacitance inherent to the light-emitting diode 20 itself is represented by C3. In addition, in this example, the capacitance value of the capacitor C2 is greater than the capacitance value of the capacitor C1, and the capacitance values of the two capacitors C1 and C2 are equal to those in the prior art, and are electrically coupled to the control end of the driving transistor. The equivalent capacitance between the source and the source is the capacitance value Ct after the capacitance is increased. The transistor 11 has a control end 110, a first end 111, and a second end 112. The control terminal 110 of the transistor 11 is electrically coupled to the control signal Scan to turn on or off the transistor 11 by the control signal Scan. The first end 111 of the transistor 11 is configured to receive the data signal Data, and the data signal Data can provide the data potential Vdata or the reference potential Vref to the first end 111 of the transistor 11.

電晶體12具有控制端120、第一端121、以及第二端122。電晶體12的控制端120係電性耦接於控制訊號EM,以藉由控制訊號EM導通或是關閉電晶體12。電晶體12的第一端121係電性耦接於操作電源OVDD。電晶體13具有控制端130、 第一端131、以及第二端132。電晶體13的控制端130係電性耦接於控制訊號Reset1,以藉由控制訊號Reset1導通或是關閉電晶體13。電晶體14具有控制端140、第一端141、以及第二端142。電晶體14的第一端141係電性耦接於電晶體12的第二端122,且電晶體14的第二端142係電性耦接於電晶體13的第二端132,而電晶體14的控制端140係電性耦接於電晶體11的第二端112。 The transistor 12 has a control end 120, a first end 121, and a second end 122. The control terminal 120 of the transistor 12 is electrically coupled to the control signal EM to turn on or off the transistor 12 by the control signal EM. The first end 121 of the transistor 12 is electrically coupled to the operating power source OVDD. The transistor 13 has a control terminal 130, The first end 131 and the second end 132. The control terminal 130 of the transistor 13 is electrically coupled to the control signal Reset1 to turn on or off the transistor 13 by the control signal Reset1. The transistor 14 has a control end 140, a first end 141, and a second end 142. The first end 141 of the transistor 14 is electrically coupled to the second end 122 of the transistor 12, and the second end 142 of the transistor 14 is electrically coupled to the second end 132 of the transistor 13, and the transistor The control terminal 140 of the 14 is electrically coupled to the second end 112 of the transistor 11 .

電容C1具有第一端C11及第二端C12。電容C1的第一端C11係電性耦接於電晶體14的控制端140,且電容C1的第二端C12與電晶體14的第二端142以及電晶體13的第二端132共同電性耦接。電容C2具有第一端C21及第二端C22。電容C2的第一端C21與電晶體11的第二端112以及電容C1的第一端C11共同電性耦接,且電容C2的第二端C22係電性耦接於電晶體13的第一端131。發光二極體20具有第一端201以及第二端202。發光二極體20的第一端201係電性耦接於電晶體14的第二端142,且發光二極體20的第二端202係電性耦接於操作電源OVSS。 The capacitor C1 has a first end C11 and a second end C12. The first end C11 of the capacitor C1 is electrically coupled to the control end 140 of the transistor 14, and the second end C12 of the capacitor C1 is electrically connected to the second end 142 of the transistor 14 and the second end 132 of the transistor 13. Coupling. The capacitor C2 has a first end C21 and a second end C22. The first end C21 of the capacitor C2 is electrically coupled to the second end 112 of the capacitor 11 and the first end C11 of the capacitor C1, and the second end C22 of the capacitor C2 is electrically coupled to the first of the transistor 13. End 131. The light emitting diode 20 has a first end 201 and a second end 202. The first end 201 of the LED 20 is electrically coupled to the second end 142 of the transistor 14 , and the second end 202 of the LED 20 is electrically coupled to the operating power source OVSS .

圖2所繪示為圖1所示之發光二極體畫素電路的其中一種訊號時序圖。如圖2所示,圖1之發光二極體畫素電路100係可依序運作於重置期間、補償期間、資料寫入期間、以及發光期間,其中各訊號可以具有高準位H及低準位L兩種狀態,高準位H施加於N型電晶體的閘極時,可以使得N型電晶體導通,但高準位H施加於P型電晶體的閘極時,則會使得P型電晶體關閉;反之,低準位L施加於N型電晶體的閘極時,會使得N型電晶體關閉,而低準位L施加於P型電晶體的閘極時,則可以使得P型電晶體導通。高準位H可以例如等於電位 OVDDH,而低準位L可以例如等於電位OVDDL。請共同參照圖1及圖2,發光二極體畫素電路100之電晶體11用以於重置期間、補償期間以及資料寫入期間時導通,且電晶體11的第一端111於資料寫入期間時接收資料訊號Data所提供的資料電位Vdata,並於重置期間、補償期間以及發光期間時接收資料訊號Data所提供的參考電位Vref。電晶體12用以於重置期間、補償期間以及發光期間時導通,且電晶體12的第一端121於重置期間時接收操作電源OVDD所提供的電位OVDDL,而電晶體12的第一端121於補償期間、資料寫入期間及發光期間時接收操作電源OVDD所提供的電位OVDDH,且電位OVDDL係小於電位OVDDH。電晶體13用以於重置期間、資料寫入期間以及發光期間時導通。特別一提的是,於資料寫入期間中,電晶體13及電晶體11的導通時間可為部分重疊或不重疊(在圖2中係不重疊),且電晶體13的導通時間晚於電晶體11的導通時間。此外,由於操作電源OVDD在重置期間當中提供電位OVDDL,因此使得節點S上的電位會為OVDDL,此時電容C1以及C2會透過節點S進行放電以重置發光二極體畫素電路100。 FIG. 2 is a timing diagram of one of the signals of the LED pixel circuit shown in FIG. 1. As shown in FIG. 2, the LED pixel circuit 100 of FIG. 1 can be sequentially operated during a reset period, a compensation period, a data writing period, and a light-emitting period, wherein each signal can have a high level H and a low level. In the two states of the level L, when the high level H is applied to the gate of the N-type transistor, the N-type transistor can be turned on, but when the high level H is applied to the gate of the P-type transistor, the P is made. The transistor is turned off; conversely, when the low level L is applied to the gate of the N-type transistor, the N-type transistor is turned off, and when the low level L is applied to the gate of the P-type transistor, the P can be made. The type of transistor is turned on. The high level H can be, for example, equal to the potential OVDDH, and the low level L can be, for example, equal to the potential OVDDL. Referring to FIG. 1 and FIG. 2 together, the transistor 11 of the LED device 100 is turned on during the reset period, the compensation period, and the data writing period, and the first end 111 of the transistor 11 is written in the data. The data potential Vdata provided by the data signal Data is received during the input period, and the reference potential Vref provided by the data signal Data is received during the reset period, the compensation period, and the light-emitting period. The transistor 12 is used to be turned on during the reset period, the compensation period, and the light-emitting period, and the first end 121 of the transistor 12 receives the potential OVDDL provided by the operating power source OVDD during the reset period, and the first end of the transistor 12 The potential OVDDH supplied from the operation power source OVDD is received during the compensation period, the data writing period, and the light-emitting period, and the potential OVDDL is smaller than the potential OVDDH. The transistor 13 is used to conduct during reset, during data writing, and during illumination. In particular, during the data writing period, the on-times of the transistor 13 and the transistor 11 may be partially overlapped or not overlapped (not overlapping in FIG. 2), and the on-time of the transistor 13 is later than the electricity. The conduction time of the crystal 11. In addition, since the operating power source OVDD provides the potential OVDDL during the reset period, the potential on the node S will be OVDDL, and at this time, the capacitors C1 and C2 will discharge through the node S to reset the light-emitting diode pixel circuit 100.

以圖2所示為例,詳細而言,當發光二極體畫素電路100運作於重置期間時,電晶體11、電晶體12以及電晶體13會分別被控制訊號Scan、控制訊號EM以及控制訊號Reset1所導通,且此時電晶體11的第一端111接收資料訊號Data所提供的參考電位Vref,電晶體12的第一端121接收操作電源OVDD所提供的電位OVDDL,所以此時節點G的電位Vg在理想情況下會等於Vref,而節點S的電位Vs在理想情況下會等於OVDDL。接著,當發光二極體畫素電路100運作於補償期間 時,電晶體11仍然維持導通狀態,且電晶體11的第一端111持續接收資料訊號Data所提供的參考電位Vref,而電晶體12亦仍然維持導通狀態,但是電晶體12的第一端此時接收的是操作電源OVDD所提供的電位OVDDH,至於電晶體13於此期間則是被關閉,所以此時節點G的電位Vg仍然是Vref,而節點S的電位Vs則會由電位OVDDL的準位持續上升至等於或者實質上等於Vref-Vth,其中Vth為電晶體14的臨界電壓值(Threshold Voltage)。由於電容C1與C2二個加起來的電容值等於前述習知技術中,電性耦接於驅動電晶體的控制端與源極端之間的等效電容於容值增加後的電容值Ct,且在此時,整個發光二極體畫素電路100僅需對電容C1與C3進行充電,而不需對電容C2進行充電,因此可加速補償的速度。 As shown in FIG. 2, in detail, when the LED device 100 operates during the reset period, the transistor 11, the transistor 12, and the transistor 13 are respectively controlled by the signal Scan, the control signal EM, and The control signal Reset1 is turned on, and at this time, the first end 111 of the transistor 11 receives the reference potential Vref provided by the data signal Data, and the first end 121 of the transistor 12 receives the potential OVDDL provided by the operating power supply OVDD, so the node at this time The potential Vg of G will ideally be equal to Vref, and the potential Vs of node S will ideally be equal to OVDDL. Then, when the light emitting diode pixel circuit 100 operates during the compensation period When the transistor 11 is still in the on state, the first end 111 of the transistor 11 continues to receive the reference potential Vref provided by the data signal Data, and the transistor 12 remains in the on state, but the first end of the transistor 12 At the time of receiving the potential OVDDH provided by the operating power supply OVDD, the transistor 13 is turned off during this period, so the potential Vg of the node G is still Vref, and the potential Vs of the node S is determined by the potential OVDDL. The bit continues to rise to be equal to or substantially equal to Vref-Vth, where Vth is the threshold voltage of the transistor 14. Since the capacitance values of the two capacitors C1 and C2 are equal to those in the prior art, the equivalent capacitance between the control terminal and the source terminal of the driving transistor is increased by the capacitance value Ct after the capacitance is increased, and At this time, the entire LED pixel circuit 100 only needs to charge the capacitors C1 and C3 without charging the capacitor C2, thereby accelerating the speed of compensation.

再接著,當發光二極體畫素電路100運作於資料寫入期間時,電晶體11會在一段預設時間t1之後被關閉,而在電晶體11被關閉之前,電晶體11的第一端111會接收資料訊號Data所提供的資料電位Vdata。此外,在資料寫入期間時,電晶體12會被關閉,而電晶體13會在上述的預設時間t1之後被導通(例如在進入資料寫入期間t2後導通,即電晶體13及電晶體11的導通時間為不重疊),所以此時節點G的電位Vg在理想情況下會等於Vdata,而節點S的電位透過電容耦合則會變成Vref-Vth+a(Vdata-Vref),因為節點G由Vref電壓準位轉變為Vdata電壓準位時,電晶體13為關閉狀態,所以a為C1/(C1+C3)。 Then, when the light-emitting diode pixel circuit 100 operates during data writing, the transistor 11 is turned off after a predetermined time t1, and before the transistor 11 is turned off, the first end of the transistor 11 111 will receive the data potential Vdata provided by the data signal Data. In addition, during the data writing period, the transistor 12 is turned off, and the transistor 13 is turned on after the preset time t1 (for example, after the data writing period t2 is turned on, that is, the transistor 13 and the transistor). The on-time of 11 is not overlapping), so the potential Vg of the node G is ideally equal to Vdata, and the potential of the node S is capacitively coupled to Vref-Vth+a(Vdata-Vref) because the node G When the Vref voltage level is changed to the Vdata voltage level, the transistor 13 is turned off, so a is C1/(C1+C3).

由上述可知,由於電容C1的電容值小於習知技術中原本電性耦接於驅動電晶體的控制端與源極端之間的等效電容於容值增加後的電容值Ct,因此在發光二極體畫素電路 100自補償期間進入資料寫入期間時,由節點G耦合至節點S的電壓會變小,這樣便拉大了節點G與節點S之間的壓差。如此一來,通過電晶體14的電流量便會增加,進而可以提高流過發光二極體20的發光電流。 It can be seen from the above that since the capacitance value of the capacitor C1 is smaller than the capacitance value Ct of the equivalent capacitance between the control terminal and the source terminal of the prior art electrically coupled to the driving transistor, the capacitance value Ct is increased. Polar body pixel circuit When the data self-compensation period enters the data writing period, the voltage coupled to the node S by the node G becomes smaller, thus widening the voltage difference between the node G and the node S. As a result, the amount of current passing through the transistor 14 is increased, and the light-emitting current flowing through the light-emitting diode 20 can be increased.

最後,當發光二極體畫素電路100運作於發光期間時,電晶體11維持關閉,電晶體12以及電晶體13則維持導通,且電晶體12持續接收操作電源OVDD所提供的電位OVDDH。此時,節點S的電位變化量會耦合至節點G,而其耦合量可用(C1+C2)/(C1+C2+Cp)式來計算,其中Cp(圖未示)為與節點G相關的的寄生電容值。由上式可知,由於電容C1與C2的電容值加起來等於前述習知技術中,電性耦接於驅動電晶體的控制端與源極端之間的等效電容於容值增加後的電容值Ct,因此,這樣的做法同樣可以降低寄生電容效應。 Finally, when the light-emitting diode pixel circuit 100 operates during the light-emitting period, the transistor 11 remains turned off, the transistor 12 and the transistor 13 remain turned on, and the transistor 12 continues to receive the potential OVDDH provided by the operating power source OVDD. At this time, the potential variation of the node S is coupled to the node G, and the coupling amount thereof can be calculated by the equation (C1+C2)/(C1+C2+Cp), where Cp (not shown) is related to the node G. The parasitic capacitance value. As shown in the above formula, since the capacitance values of the capacitors C1 and C2 add up to the above-mentioned conventional techniques, the equivalent capacitance between the control terminal and the source terminal of the driving transistor is increased after the capacitance value is increased. Ct, therefore, this approach can also reduce the parasitic capacitance effect.

在另一個例子的資料寫入期間中,控制訊號Scan由高準位(high)轉態至低準位(low)的時間可以是晚於控制訊號Reset1由低準位轉態至高準位的時間,以使得電晶體13及電晶體11的導通時間為部分重疊,進而避免節點G在這二個控制訊號的轉態過程中因呈現浮接狀態而受到電容C1與C2所耦合之電壓的影響而改變其準位。 In the data writing period of another example, the time when the control signal Scan is shifted from the high level to the low level (low) may be later than the time when the control signal Reset1 is shifted from the low level to the high level. Therefore, the on-times of the transistor 13 and the transistor 11 are partially overlapped, thereby preventing the node G from being affected by the voltage coupled by the capacitors C1 and C2 due to the floating state during the transition state of the two control signals. Change its level.

當然,儘管在圖1所示之實施例中,電容C3係表示發光二極體20本身固有之等效電容,然而在發光二極體20本身固有之等效電容的電容值不足的情況下,設計者自可在發光二極體20旁並聯一個實體電容,使得發光二極體20之第一端201與第二端202之間的等效電容值可為發光二極體20本身固有之等效電容與並聯之電容的電容值總合。 Of course, in the embodiment shown in FIG. 1, the capacitor C3 represents the equivalent capacitance inherent to the LED 20 itself, but in the case where the capacitance of the equivalent capacitance inherent to the LED 20 is insufficient. The designer can connect a solid capacitor in parallel with the LED 20 so that the equivalent capacitance between the first end 201 and the second end 202 of the LED 20 can be inherent to the LED 20 itself. The effective capacitance is the sum of the capacitance values of the parallel capacitors.

圖3所繪示為本發明另一實施例之發光二極體畫 素電路的電路架構圖。在圖3中,與圖1中的標號相同者係代表相同的元件或訊號。如圖3所示,發光二極體畫素電路200與圖1中的發光二極體畫素電路100的電路架構大致相同,差異僅在於發光二極體畫素電路200更包括一個電晶體15。電晶體15具有控制端150、第一端151以及第二端152,且電晶體15的控制端150係接收控制訊號Reset2,電晶體15的第一端151係電性耦接於一個預設電位Vsus(其電位大小與電位OVDDL相同或約略相等),而電晶體15的第二端152係電性耦接於電晶體13的第一端131。 FIG. 3 illustrates a light-emitting diode painting according to another embodiment of the present invention. The circuit architecture diagram of the prime circuit. In FIG. 3, the same reference numerals as in FIG. 1 denote the same elements or signals. As shown in FIG. 3, the LED structure of the LED pixel circuit 200 is substantially the same as that of the LED pixel circuit 100 of FIG. 1, except that the LED circuit 200 further includes a transistor 15. . The transistor 15 has a control terminal 150, a first end 151 and a second end 152, and the control terminal 150 of the transistor 15 receives the control signal Reset2, and the first end 151 of the transistor 15 is electrically coupled to a predetermined potential. The second end 152 of the transistor 15 is electrically coupled to the first end 131 of the transistor 13 . The second end 152 of the transistor 15 is electrically coupled to the first end 131 of the transistor 13 .

圖4所繪示為圖3所示之發光二極體畫素電路的其中一種訊號時序圖。如圖4所示,發光二極體畫素電路200亦是依序運作於重置期間、補償期間、資料寫入期間以及發光期間。發光二極體畫素電路200之中的電晶體11用以於重置期間、補償期間及資料寫入期間時導通,且電晶體11的第一端111於資料寫入期間時接收資料訊號Data所提供的資料電位Vdata,並於重置期間、補償期間以及發光期間時接收資料訊號Data所提供的參考電位Vref。發光二極體畫素電路200之中的電晶體12係用以於補償期間及發光期間時導通。發光二極體畫素電路200之中的電晶體13用以於重置期間、資料寫入期間以及發光期間時導通。其中,於資料寫入期間中,發光二極體畫素電路200之中的電晶體13以及電晶體11的導通時間亦可為部分重疊或不重疊(在圖4中係不重疊,可設計為重疊的原因亦如先前所述),且電晶體13的導通時間晚於電晶體11的導通時間。而發光二極體畫素電路200之中的電晶體15係用以於重置期間時導通,且電晶體15的第一端151係於重置期間時接收預設電位Vsus,預設電位Vsus可以例如具有電位 OVDDL。此外,由於在重置期間提供預設電位Vsus至電容C1的其中一端以及電容C2的其中一端,因此此時電容C1以及C2會進行放電以重置發光二極體畫素電路200。 FIG. 4 is a timing diagram of one of the signals of the LED pixel circuit shown in FIG. 3. As shown in FIG. 4, the LED circuit 200 is also sequentially operated during the reset period, the compensation period, the data writing period, and the light-emitting period. The transistor 11 in the LED pixel circuit 200 is used to be turned on during the reset period, the compensation period, and the data writing period, and the first end 111 of the transistor 11 receives the data signal during the data writing period. The data potential Vdata is provided, and the reference potential Vref provided by the data signal Data is received during the reset period, the compensation period, and the light-emitting period. The transistor 12 in the light-emitting diode pixel circuit 200 is used to be turned on during the compensation period and during the light-emitting period. The transistor 13 in the light-emitting diode pixel circuit 200 is used to be turned on during the reset period, during the data writing period, and during the light-emitting period. In the data writing period, the on-times of the transistor 13 and the transistor 11 in the LED pixel circuit 200 may be partially overlapped or not overlapped (not overlapping in FIG. 4, and may be designed as The reason for the overlap is also as described previously, and the on-time of the transistor 13 is later than the on-time of the transistor 11. The transistor 15 in the LED pixel circuit 200 is used to be turned on during the reset period, and the first end 151 of the transistor 15 receives the preset potential Vsus during the reset period, and the preset potential Vsus Can have, for example, a potential OVDDL. Further, since the preset potential Vsus is supplied to one end of the capacitor C1 and one end of the capacitor C2 during the reset, the capacitors C1 and C2 are discharged at this time to reset the light-emitting diode pixel circuit 200.

雖然在先前的敘述當中,電容C1、電容C2以及電晶體13均為各自獨立的元件,但是也可以將此三者視為一個電容模組。此電容模組係用以在電晶體14的控制端140與電晶體14的第二端142之間提供一個等效電容,且此電容模組在發光二極體畫素電路處於重置期間以及發光期間時所提供之等效電容的容值大於發光二極體畫素電路處於補償期間以及資料寫入期間時所提供之等效電容的容值。當然,上述之電容模組的實現方式僅是用以舉例,並非用以限制本發明。 Although in the previous description, the capacitor C1, the capacitor C2, and the transistor 13 are independent components, the three can also be regarded as one capacitor module. The capacitor module is configured to provide an equivalent capacitance between the control terminal 140 of the transistor 14 and the second end 142 of the transistor 14, and the capacitor module is in a reset state during the LED circuit and The capacitance of the equivalent capacitance provided during the light-emitting period is greater than the capacitance of the equivalent capacitance provided by the light-emitting diode pixel circuit during the compensation period and during the data writing period. The implementation of the capacitor module described above is for example only and is not intended to limit the present invention.

圖5為本發明一實施例之發光二極體畫素電路的驅動方法流程圖。透過上述的敘述,可以將發光二極體畫素電路100的驅動方法歸納出如圖5所示的步驟501~504。 FIG. 5 is a flow chart of a driving method of a light emitting diode pixel circuit according to an embodiment of the present invention. Through the above description, the driving method of the light-emitting diode pixel circuit 100 can be summarized as steps 501 to 504 shown in FIG.

步驟501:於重置期間中,使操作電源OVDD提供電位OVDDL,並導通電晶體11、電晶體12以及電晶體13,同時提供參考電位Vref至電晶體11的第一端111。步驟502:於補償期間中,使操作電源OVDD提供電位OVDDH,電位OVDDH大於電位OVDDL,並導通電晶體11與電晶體12,同時關閉電晶體13,並提供參考電位Vref至電晶體11的第一端111。步驟503:於資料寫入期間中,使操作電源OVDD提供電位OVDDH,並導通電晶體11與電晶體13,以及關閉電晶體12,其中電晶體11與電晶體13的導通時間為部分重疊或不重疊,且電晶體11之導通時間先於與電晶體13之導通時間,並在電晶體11導通時提供資料電位Vdata至電晶體11的第一端111。步驟504:於發光期間中,使操作電源OVDD提供電位OVDDH, 並關閉電晶體11,以及導通電晶體12與電晶體13,並提供參考電位Vref至電晶體11的第一端111。在上述的步驟501~504之中,重置期間先於補償期間,補償期間先於資料寫入期間,資料寫入期間先於發光期間。 Step 501: During the reset period, the operating power source OVDD is supplied with the potential OVDDL, and the crystal 11, the transistor 12, and the transistor 13 are turned on, while the reference potential Vref is supplied to the first end 111 of the transistor 11. Step 502: During the compensation period, the operating power source OVDD is supplied with the potential OVDDH, the potential OVDDH is greater than the potential OVDDL, and the transistor 11 and the transistor 12 are turned on, and the transistor 13 is turned off, and the reference potential Vref is supplied to the first of the transistor 11. End 111. Step 503: During the data writing period, the operating power source OVDD is supplied with the potential OVDDH, and the transistor 11 and the transistor 13 are turned on, and the transistor 12 is turned off. The on-time of the transistor 11 and the transistor 13 is partially overlapped or not. Overlap, and the on-time of the transistor 11 precedes the on-time with the transistor 13, and provides the data potential Vdata to the first end 111 of the transistor 11 when the transistor 11 is turned on. Step 504: In the light emitting period, the operating power source OVDD is supplied with the potential OVDDH, The transistor 11 is turned off, and the conductive crystal 12 and the transistor 13 are electrically connected, and a reference potential Vref is supplied to the first end 111 of the transistor 11. In the above steps 501 to 504, the reset period precedes the compensation period, the compensation period precedes the data write period, and the data write period precedes the light emission period.

圖6為本發明一實施例之發光二極體畫素電路的驅動方法流程圖。透過上述的敘述,可以將發光二極體畫素電路200的驅動方法歸納出如圖6所示的步驟601~604。 FIG. 6 is a flow chart of a driving method of a light emitting diode pixel circuit according to an embodiment of the present invention. Through the above description, the driving method of the light-emitting diode pixel circuit 200 can be summarized as steps 601 to 604 shown in FIG. 6.

步驟601:於重置期間中,導通電晶體11、電晶體13與電晶體15,同時提供參考電位Vref至電晶體11的第一端111。步驟602:於補償期間中,導通電晶體11與電晶體12,同時關閉電晶體13與電晶體15,並提供參考電位Vref至電晶體11的第一端111。步驟603:於資料寫入期間中,導通電晶體11與電晶體13,以及關閉電晶體12與電晶體15,其中電晶體11與電晶體13的導通時間為部分重疊或不重疊,且電晶體11之導通時間先於電晶體13之導通時間,並在電晶體11導通時提供資料電位Vdata至電晶體11的第一端111。步驟604:於發光期間中,關閉電晶體11與電晶體15,並導通電晶體12與電晶體13,以及提供參考電位Vref至電晶體11的第一端111。在上述的步驟601~604之中,重置期間先於補償期間,補償期間先於資料寫入期間,資料寫入期間先於發光期間。 Step 601: During the reset period, the conductive crystal 11, the transistor 13 and the transistor 15 are electrically connected while the reference potential Vref is supplied to the first end 111 of the transistor 11. Step 602: During the compensation period, the transistor 11 and the transistor 12 are electrically connected, and the transistor 13 and the transistor 15 are turned off at the same time, and the reference potential Vref is supplied to the first end 111 of the transistor 11. Step 603: During the data writing period, the conductive crystal 11 and the transistor 13 are turned on, and the transistor 12 and the transistor 15 are turned off, wherein the conduction time of the transistor 11 and the transistor 13 partially overlap or not overlap, and the transistor The on-time of 11 precedes the on-time of the transistor 13, and provides a data potential Vdata to the first end 111 of the transistor 11 when the transistor 11 is turned on. Step 604: During the illuminating period, the transistor 11 and the transistor 15 are turned off, and the crystal 12 and the transistor 13 are electrically connected, and the reference potential Vref is supplied to the first end 111 of the transistor 11. In the above steps 601 to 604, the reset period precedes the compensation period, the compensation period precedes the data writing period, and the data writing period precedes the lighting period.

綜上所述,在本發明之發光二極體畫素電路的電路架構中,係採用例如是由二個電容與一個電晶體所構成的電容模組來電性耦接於驅動電晶體的控制端與源極端之間,並利用此電晶體來決定是否讓上述二個電容皆電性耦接於驅動電晶體的控制端與源極端之間,或是僅讓其中一個電容電性耦接於驅動電晶體的控制端與源極端之間,藉以在發光二極體畫素電路的不同操作期間中改變電性耦接於驅動電晶體 的控制端與源極端之間的等效電容的容值大小。據此,只要在重置期間與發光期間中導通此電晶體而使得上述二個電容並聯,並在其餘二個期間中關閉此電晶體,那麼本發明之發光二極體畫素電路便可避免發生習知技術中之發光二極體的發光電流減少,以及補償速度變慢等問題。 In summary, in the circuit architecture of the LED pixel circuit of the present invention, a capacitor module composed of two capacitors and a transistor is electrically coupled to the control terminal of the driving transistor. Between the source and the terminal, the transistor is used to determine whether the two capacitors are electrically coupled between the control terminal and the source terminal of the driving transistor, or only one of the capacitors is electrically coupled to the driving. Between the control terminal and the source terminal of the transistor, thereby electrically changing the electrical coupling to the driving transistor during different operation periods of the LED substrate circuit The capacitance of the equivalent capacitance between the control terminal and the source terminal. Accordingly, the light-emitting diode pixel circuit of the present invention can be avoided as long as the two capacitors are connected in parallel during the reset period and during the light-emitting period, and the two capacitors are turned off in parallel during the remaining two periods. There is a problem that the luminous current of the light-emitting diode in the conventional technique is reduced, and the compensation speed is slow.

雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100‧‧‧發光二極體畫素電路 100‧‧‧Light Diode Pixel Circuit

11、12、13、14‧‧‧電晶體 11, 12, 13, 14‧‧‧ transistors

C1、C2、C3‧‧‧電容 C1, C2, C3‧‧‧ capacitors

20‧‧‧發光二極體 20‧‧‧Lighting diode

110、120、130、140‧‧‧控制端 110, 120, 130, 140‧‧‧ control end

111、121、131、141、C11、C21、C31、201‧‧‧第一端 111, 121, 131, 141, C11, C21, C31, 201‧‧‧ first end

112、122、132、142、C12、C22、C32、202‧‧‧第二端 112, 122, 132, 142, C12, C22, C32, 202‧‧‧ second end

OVDD、OVSS‧‧‧操作電源 OVDD, OVSS‧‧‧ operating power supply

Scan、EM、Reset1‧‧‧控制訊號 Scan, EM, Reset1‧‧‧ control signals

Data‧‧‧資料訊號 Data‧‧‧Information Signal

G、S‧‧‧節點 G, S‧‧‧ nodes

Claims (13)

一種發光二極體畫素電路,包括:一第一電晶體,具有一控制端、一第一端以及一第二端,該第一電晶體的該控制端電性耦接一第一控制訊號,該第一電晶體的該第一端用以接收一資料電位或是一參考電位;一第二電晶體,具有一控制端、一第一端、以及一第二端,該第二電晶體的該控制端電性耦接一第二控制訊號,該第二電晶體的該第一端電性耦接一第一操作電源;一第三電晶體,具有一控制端、一第一端、以及一第二端,該第三電晶體的該控制端電性耦接一第三控制訊號;一第四電晶體,具有一控制端、一第一端、以及一第二端,該第四電晶體的該第一端電性耦接於該第二電晶體的該第二端,該第四電晶體的該第二端電性耦接於該第三電晶體的該第二端,而該第四電晶體的該控制端電性耦接於該第一電晶體的該第二端;一第一電容,具有一第一端及一第二端,該第一電容的該第一端電性耦接於該第四電晶體的該控制端,該第一電容的該第二端與該第四電晶體的該第二端及該第三電晶體的該第二端共同電性耦接;一第二電容,具有一第一端及一第二端,該第二電容的該第一端與該第一電晶體的該第二端及該第一電容的該第一端共同電性耦接,該第二電容的該第二端電性耦接於該第三電晶體的該第一端,且該第二電容的電容值大於該第一電容的電容值;以及一發光二極體,具有一第一端以及一第二端,該發光二極體的該第一端電性耦接於該第四電晶體的該第二端,該發 光二極體的該第二端電性耦接於一第二操作電源。 A light-emitting diode pixel circuit includes: a first transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor is electrically coupled to a first control signal The first end of the first transistor is configured to receive a data potential or a reference potential; a second transistor has a control end, a first end, and a second end, the second transistor The control terminal is electrically coupled to a second control signal, the first end of the second transistor is electrically coupled to a first operating power source, and the third transistor has a control end, a first end, And a second end, the control end of the third transistor is electrically coupled to a third control signal; a fourth transistor having a control end, a first end, and a second end, the fourth The first end of the second transistor is electrically coupled to the second end of the second transistor, and the second end of the fourth transistor is electrically coupled to the second end of the third transistor. The control terminal of the fourth transistor is electrically coupled to the second end of the first transistor; a first capacitor has a first The second end of the first capacitor is electrically coupled to the control end of the fourth transistor, the second end of the first capacitor and the second end of the fourth transistor The second end is electrically coupled to the second end of the third transistor; the second capacitor has a first end and a second end, the first end of the second capacitor and the first transistor The second end is electrically coupled to the first end of the first capacitor, the second end of the second capacitor is electrically coupled to the first end of the third transistor, and the second capacitor The capacitance value is greater than the capacitance value of the first capacitor; and a light emitting diode having a first end and a second end, the first end of the light emitting diode being electrically coupled to the fourth transistor The second end of the hair The second end of the photodiode is electrically coupled to a second operating power source. 如申請專利範圍第1項所述之發光二極體畫素電路,其中該第一電晶體用以於一重置期間、一補償期間及一資料寫入期間時導通,且該第一電晶體的該第一端於該資料寫入期間接收該資料電位,並於該重置期間、該補償期間及一發光期間接收該參考電位,該第二電晶體用以於該重置期間、該補償期間及該發光期間時導通,且該第二電晶體的該第一端於該重置期間接收該第一操作電源所提供的一第一電位,而該第二電晶體的該第一端於該補償期間、該資料寫入期間及該發光期間接收該第一操作電源所提供的一第二電位,且該第一電位小於該第二電位,該第三電晶體用以於該重置期間、該資料寫入期間及該發光期間時導通,於該資料寫入期間中,該第三電晶體及該第一電晶體的導通時間為部分重疊或不重疊,且該第三電晶體的導通時間晚於該第一電晶體的導通時間,其中,該重置期間先於該補償期間,該補償期間先於該資料寫入期間,而該資料寫入期間先於該發光期間。 The illuminating diode pixel circuit of claim 1, wherein the first transistor is used to be turned on during a reset period, a compensation period, and a data writing period, and the first transistor The first end receives the data potential during the data writing period, and receives the reference potential during the reset period, the compensation period and a light emitting period, the second transistor is used for the reset period, the compensation During the period and during the illuminating period, the first end of the second transistor receives a first potential provided by the first operating power source during the resetting, and the first end of the second transistor is Receiving a second potential provided by the first operating power source during the compensation period, the data writing period, and the lighting period, and the first potential is less than the second potential, the third transistor is used during the reset period And turning on during the data writing period and the illuminating period, during the data writing period, the conduction time of the third transistor and the first transistor is partially overlapped or not overlapped, and the third transistor is turned on. Time later than the first transistor The turn-on time, wherein the reset period precedes the compensation period, the compensation period precedes the data writing period, and the data writing period precedes the lighting period. 如申請專利範圍第1項所述之發光二極體畫素電路,其更包括有一第三電容,該第三電容具有一第一端及一第二端,該第三電容的該第一端電性耦接於該發光二極體的該第一端,該第三電容的該第二端電性耦接於該發光二極體的該第二端。 The illuminating diode pixel circuit of claim 1, further comprising a third capacitor having a first end and a second end, the first end of the third capacitor The second end of the third capacitor is electrically coupled to the second end of the light emitting diode. 如申請專利範圍第1項所述之發光二極體畫素電路,其更包括一第五電晶體,該第五電晶體具有一控制端、一第一端及一第二端,該第五電晶體的該控制端接收一第四控制訊 號,該第五電晶體的該第一端電性耦接一預設電位,該第五電晶體的該第二端電性耦接於該第三電晶體的該第一端。 The illuminating diode pixel circuit of claim 1, further comprising a fifth transistor having a control end, a first end and a second end, the fifth The control terminal of the transistor receives a fourth control signal The first end of the fifth transistor is electrically coupled to a predetermined potential, and the second end of the fifth transistor is electrically coupled to the first end of the third transistor. 如申請專利範圍第4項所述之發光二極體畫素電路,其中該第一電晶體用以於一重置期間、一補償期間及一資料寫入期間時導通,且該第一電晶體的該第一端於該資料寫入期間接收該資料電位,並於該重置期間、該補償期間及一發光期間接收該參考電位,該第二電晶體用以於該補償期間及該發光期間時導通,該第三電晶體用以於該重置期間、該資料寫入期間及該發光期間時導通,於該資料寫入期間中,該第三電晶體及該第一電晶體的導通時間為部分重疊或不重疊,且該第三電晶體的導通時間晚於該第一電晶體的導通時間,而該第五電晶體用以於該重置期間時導通,且該第五電晶體的該第一端於該重置期間接收該預設電位,其中,該重置期間先於該補償期間,該補償期間先於該資料寫入期間,該資料寫入期間先於該發光期間。 The illuminating diode pixel circuit of claim 4, wherein the first transistor is used to be turned on during a reset period, a compensation period, and a data writing period, and the first transistor The first end receives the data potential during the data writing period, and receives the reference potential during the reset period, the compensation period and a light emitting period, wherein the second transistor is used for the compensation period and the light emitting period Turning on, the third transistor is used to be turned on during the reset period, during the data writing period, and during the light emitting period, during the data writing period, the third transistor and the first transistor are turned on. Partially overlapping or not overlapping, and the conduction time of the third transistor is later than the conduction time of the first transistor, and the fifth transistor is used to be turned on during the reset period, and the fifth transistor is The first terminal receives the preset potential during the reset period, wherein the reset period precedes the compensation period, the compensation period precedes the data writing period, and the data writing period precedes the lighting period. 一種發光二極體畫素電路,包括:一第一電晶體,具有一控制端、一第一端以及一第二端,該第一電晶體的該控制端電性耦接一第一控制訊號,該第一電晶體的該第一端用以接收一資料電位或是一參考電位;一第二電晶體,具有一控制端、一第一端以及一第二端,該第二電晶體的該控制端電性耦接一第二控制訊號,該第二電晶體的該第一端電性耦接一第一操作電源;一第三電晶體,具有一控制端、一第一端以及一第二端,該第三電晶體的該第一端電性耦接於該第二電晶體的該第二端,而該第三電晶體的該控制端電性耦接於該第一電晶體的該第二端; 一發光二極體,具有一第一端以及一第二端,該發光二極體的該第一端電性耦接於該第三電晶體的該第二端,該發光二極體的該第二端電性耦接於一第二操作電源;以及一電容模組,電性耦接於該第三電晶體的該控制端與該第二端之間,該電容模組用以提供該第三電晶體的該控制端與該第二端之間一等效電容,且該電容模組在該二極體畫素電路處於一重置期間與一發光期間時所提供之該等效電容的值大於該二極體畫素電路處於一補償期間與一資料寫入期間時所提供之該等效電容的值。 A light-emitting diode pixel circuit includes: a first transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor is electrically coupled to a first control signal The first end of the first transistor is configured to receive a data potential or a reference potential; a second transistor has a control end, a first end, and a second end, the second transistor The control terminal is electrically coupled to a second control signal, the first end of the second transistor is electrically coupled to a first operating power source, and the third transistor has a control end, a first end, and a The second end of the third transistor is electrically coupled to the second end of the second transistor, and the control end of the third transistor is electrically coupled to the first transistor The second end; a light emitting diode having a first end and a second end, the first end of the light emitting diode being electrically coupled to the second end of the third transistor, the light emitting diode The second end is electrically coupled to a second operating power source; and a capacitor module is electrically coupled between the control end of the third transistor and the second end, the capacitor module is configured to provide the An equivalent capacitance between the control end of the third transistor and the second end, and the equivalent capacitance provided by the capacitor module during the reset period and a light emitting period of the diode pixel circuit The value is greater than the value of the equivalent capacitance provided by the diode pixel circuit during a compensation period and a data write period. 如申請專利範圍第6項所述之發光二極體畫素電路,其中該第一電晶體用以於一重置期間、一補償期間及一資料寫入期間時導通,且該第一電晶體的該第一端於該資料寫入期間接收該資料電位,並於該重置期間、該補償期間及一發光期間接收該參考電位,該第二電晶體用以於該重置期間、該補償期間及該發光期間時導通,且該第二電晶體的該第一端於該重置期間接收該第一操作電源所提供的一第一電位,而該第二電晶體的該第一端於該補償期間、該資料寫入期間及該發光期間接收該第一操作電源所提供的一第二電位,且該第一電位小於該第二電位,其中,該重置期間先於該補償期間,該補償期間先於該資料寫入期間,該資料寫入期間先於該發光期間。 The illuminating diode pixel circuit of claim 6, wherein the first transistor is used to be turned on during a reset period, a compensation period, and a data writing period, and the first transistor The first end receives the data potential during the data writing period, and receives the reference potential during the reset period, the compensation period and a light emitting period, the second transistor is used for the reset period, the compensation During the period and during the illuminating period, the first end of the second transistor receives a first potential provided by the first operating power source during the resetting, and the first end of the second transistor is Receiving a second potential provided by the first operating power source during the compensation period, the data writing period, and the lighting period, and the first potential is less than the second potential, wherein the reset period precedes the compensation period The compensation period precedes the data writing period, and the data writing period precedes the lighting period. 如申請專利範圍第6項所述之發光二極體畫素電路,其中該電容模組包括:一第四電晶體,具有一控制端、一第一端、以及一第二端,該第四電晶體的該控制端電性耦接一第三控制訊號;一第一電容,具有一第一端及一第二端,該第一電容的 該第一端電性耦接於該第三電晶體的該控制端,該第一電容的該第二端與該第三電晶體的該第二端及該第四電晶體的該第二端共同電性耦接;以及一第二電容,具有一第一端及一第二端,該第二電容的該第一端與該第一電晶體的該第二端及該第一電容的該第一端共同電性耦接,該第二電容的該第二端電性耦接於該第四電晶體的該第一端,且該第二電容的電容值大於該第一電容的電容值。 The illuminating diode pixel circuit of claim 6, wherein the capacitor module comprises: a fourth transistor having a control end, a first end, and a second end, the fourth The control terminal of the transistor is electrically coupled to a third control signal; a first capacitor having a first end and a second end, the first capacitor The first end is electrically coupled to the control end of the third transistor, the second end of the first capacitor and the second end of the third transistor and the second end of the fourth transistor a second electrical capacitor having a first end and a second end, the first end of the second capacitor and the second end of the first transistor and the first capacitor The first end is electrically coupled to the first end of the fourth capacitor, and the capacitance of the second capacitor is greater than the capacitance of the first capacitor . 如申請專利範圍第8項所述之發光二極體畫素電路,其中該第一電晶體用以於一重置期間、一補償期間及一資料寫入期間時導通,且該第一電晶體的該第一端於該資料寫入期間接收該資料電位,並於該重置期間、該補償期間及一發光期間接收該參考電位,該第二電晶體用以於該重置期間、該補償期間及該發光期間時導通,且該第二電晶體的該第一端於該重置期間接收該第一操作電源所提供的一第一電位,而該第二電晶體的該第一端於該補償期間、該資料寫入期間及該發光期間接收該第一操作電源所提供的一第二電位,且該第一電位小於該第二電位,該第四電晶體用以於該重置期間、該資料寫入期間及該發光期間時導通,於該資料寫入期間中,該第四電晶體及該第一電晶體的導通為部分重疊或不重疊,且該第四電晶體的導通時間晚於該第一電晶體的導通時間,其中,該重置期間先於該補償期間,該補償期間先於該資料寫入期間,該資料寫入期間先於該發光期間。 The illuminating diode pixel circuit of claim 8, wherein the first transistor is used to be turned on during a reset period, a compensation period, and a data writing period, and the first transistor The first end receives the data potential during the data writing period, and receives the reference potential during the reset period, the compensation period and a light emitting period, the second transistor is used for the reset period, the compensation During the period and during the illuminating period, the first end of the second transistor receives a first potential provided by the first operating power source during the resetting, and the first end of the second transistor is Receiving a second potential provided by the first operating power source during the compensation period, the data writing period, and the illuminating period, and the first potential is less than the second potential, and the fourth transistor is used during the resetting period And turning on during the data writing period and the light emitting period, wherein the fourth transistor and the first transistor are partially overlapped or not overlapped during the data writing period, and the fourth transistor is turned on. Later than the guide of the first transistor The pass time, wherein the reset period precedes the compensation period, the compensation period precedes the data writing period, and the data writing period precedes the lighting period. 如申請專利範圍第8項所述之發光二極體畫素電路,其更包括一第五電晶體,該第五電晶體具有一控制端、一第 一端及一第二端,該第五電晶體的該控制端接收一第四控制訊號,該第五電晶體的該第一端電性耦接一預設電位,該第五電晶體的該第二端電性耦接於該第四電晶體的該第一端。 The illuminating diode pixel circuit of claim 8, further comprising a fifth transistor having a control end and a first The first end of the fifth transistor receives a fourth control signal, and the first end of the fifth transistor is electrically coupled to a predetermined potential, the first portion of the fifth transistor The two ends are electrically coupled to the first end of the fourth transistor. 如申請專利範圍第10項所述之發光二極體畫素電路,其中該第一電晶體用以於一重置期間、一補償期間及一資料寫入期間時導通,且該第一電晶體的該第一端於該資料寫入期間接收該資料電位,並於該重置期間、該補償期間及一發光期間接收該參考電位,該第二電晶體用以於該補償期間及該發光期間時導通,該第四電晶體用以於該重置期間、該資料寫入期間及該發光期間時導通,於該資料寫入期間中,該第四電晶體及該第一電晶體的導通時間為部分重疊或不重疊,且該第四電晶體的導通時間晚於該第一電晶體的導通時間,而該第五電晶體用以於該重置期間時導通,且該第五電晶體的該第一端於該重置期間接收該預設電位,其中,該重置期間先於該補償期間,該補償期間先於該資料寫入期間,該資料寫入期間先於該發光期間。 The illuminating diode pixel circuit of claim 10, wherein the first transistor is used to be turned on during a reset period, a compensation period, and a data writing period, and the first transistor The first end receives the data potential during the data writing period, and receives the reference potential during the reset period, the compensation period and a light emitting period, wherein the second transistor is used for the compensation period and the light emitting period Turning on, the fourth transistor is configured to be turned on during the reset period, the data writing period, and the light emitting period, and the fourth transistor and the first transistor turn-on time during the data writing period Partially overlapping or non-overlapping, and an on-time of the fourth transistor is later than an on-time of the first transistor, and the fifth transistor is used to be turned on during the reset period, and the fifth transistor is The first terminal receives the preset potential during the reset period, wherein the reset period precedes the compensation period, the compensation period precedes the data writing period, and the data writing period precedes the lighting period. 一種發光二極體畫素電路的驅動方法,用以驅動如申請專利範圍第1項的該發光二極體畫素電路,該驅動方法包括:於一重置期間中,使該第一操作電源提供一第一電位,並導通該第一電晶體、該第二電晶體與該第三電晶體,同時提供一參考電位至該第一電晶體的該第一端;於一補償期間中,使該第一操作電源提供一第二電位,該第二電位大於該第一電位,並導通該第一電晶體與該第二電晶體,同時關閉該第三電晶體,並提供該參考電位至該第一電晶體的該第一端; 於一資料寫入期間中,使該第一操作電源提供該第二電位,並導通該第一電晶體與該第三電晶體,以及關閉該第二電晶體,其中該第一電晶體與該第三電晶體的導通時間為部分重疊或不重疊,且該第一電晶體之導通時間先於該第三電晶體之導通時間,並在該第一電晶體導通時提供一資料電位至該第一電晶體的該第一端;以及於一發光期間中,使該第一操作電源提供該第二電位,並關閉該第一電晶體,以及導通該第二電晶體與該第三電晶體,並提供該參考電位至該第一電晶體的該第一端,其中,該重置期間先於該補償期間,該補償期間先於該資料寫入期間,該資料寫入期間先於該發光期間。 A driving method of a light emitting diode pixel circuit for driving the light emitting diode pixel circuit according to claim 1, wherein the driving method comprises: making the first operating power source during a reset period Providing a first potential, and conducting the first transistor, the second transistor and the third transistor, and simultaneously providing a reference potential to the first end of the first transistor; during a compensation period, The first operating power source provides a second potential, the second potential is greater than the first potential, and turns on the first transistor and the second transistor, simultaneously turns off the third transistor, and provides the reference potential to the The first end of the first transistor; The first operating power source provides the second potential during a data writing period, and turns on the first transistor and the third transistor, and turns off the second transistor, wherein the first transistor and the first transistor The on-time of the third transistor is partially overlapped or non-overlapping, and the on-time of the first transistor precedes the on-time of the third transistor, and provides a data potential to the first transistor when the first transistor is turned on a first end of a transistor; and during a light emitting period, causing the first operating power source to provide the second potential, and turning off the first transistor, and turning on the second transistor and the third transistor, And providing the reference potential to the first end of the first transistor, wherein the reset period precedes the compensation period, the compensation period precedes the data writing period, and the data writing period precedes the lighting period . 一種發光二極體畫素電路的驅動方法,用以驅動如申請專利範圍第4項的該發光二極體畫素電路,該驅動方法包括:於一重置期間中,導通該第一電晶體、該第三電晶體與該第五電晶體,同時提供一參考電位至該第一電晶體的該第一端;於一補償期間中,導通該第一電晶體與該第二電晶體,同時關閉該第三電晶體與該第五電晶體,並提供該參考電位至該第一電晶體的該第一端;於一資料寫入期間中,導通該第一電晶體與該第三電晶體,以及關閉該第二電晶體與該第五電晶體,其中該第一電晶體與該第三電晶體的導通時間為部分重疊或不重疊,且該第一電晶體之導通時間先於該第三電晶體之導通時間,並在該第一電晶體導通時提供一資料電位至該第一電晶體的該第一端;以及於一發光期間中,關閉該第一電晶體與該第五電晶體, 並導通該第二電晶體與該第三電晶體,以及提供該參考電位至該第一電晶體的該第一端,其中,該重置期間先於該補償期間,該補償期間先於該資料寫入期間,該資料寫入期間先於該發光期間。 A driving method of a light emitting diode pixel circuit for driving the light emitting diode pixel circuit according to claim 4, wherein the driving method comprises: turning on the first transistor during a reset period The third transistor and the fifth transistor simultaneously provide a reference potential to the first end of the first transistor; during a compensation period, the first transistor and the second transistor are turned on simultaneously Closing the third transistor and the fifth transistor, and providing the reference potential to the first end of the first transistor; during the data writing period, turning on the first transistor and the third transistor And closing the second transistor and the fifth transistor, wherein an on time of the first transistor and the third transistor partially overlaps or does not overlap, and an on time of the first transistor precedes the first a turn-on time of the tri-crystal, and providing a data potential to the first end of the first transistor when the first transistor is turned on; and turning off the first transistor and the fifth electrode during a light-emitting period Crystal, And conducting the second transistor and the third transistor, and providing the reference potential to the first end of the first transistor, wherein the reset period precedes the compensation period, the compensation period precedes the data During writing, the data is written during the pre-lighting period.
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