TWI743476B - 金屬膜沉積 - Google Patents

金屬膜沉積 Download PDF

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TWI743476B
TWI743476B TW108115200A TW108115200A TWI743476B TW I743476 B TWI743476 B TW I743476B TW 108115200 A TW108115200 A TW 108115200A TW 108115200 A TW108115200 A TW 108115200A TW I743476 B TWI743476 B TW I743476B
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metal
substrate
gas
layer
feature
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TW201947642A (zh
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雷雨
李相協
克里斯 帕貝里可
徐翼
河泰泓
先敏 唐
朴真希
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美商應用材料股份有限公司
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Abstract

本案提供一種用於提供具有金屬膜之電子裝置的設備及方法。本揭示案之一些實施例利用金屬鎢層作為襯墊，該襯墊充滿包含鈷之金屬膜。金屬鎢層具有對鈷之良好黏著力，導致增強的鈷縫隙填充效能。

Description

金屬膜沉積
本揭示案之實施例係關於電子裝置製造領域，且更特定而言係關於積體電路(integrated circuit; IC)。特定而言，本揭示案之實施例係關於使用含鎢之CVD/ALD襯墊之鈷填充整合製程。
積體電路可藉由在基板表面上產生複雜圖案化材料層之製程來製造。在基板上產生圖案化材料需要用於沉積所需材料之受控方法。相對於不同表面而在一個表面上選擇性沉積膜對圖案化及其他應用是有用的。
藉由CVD或ALD製程沉積之鈷層相對於藉由PVD製程沉積之類似鈷層具有更大電阻率。大體上，更大電阻率部分歸因於由CVD或ALD製程沉積之薄鈷層的顯著碳含量（例如，約5原子百分比）以及高表面粗糙度。此種高碳含量及表面粗糙度顯著影響作為P型金屬之鈷層的功函數，並且大體導致整個整合閘極堆疊或在其中含有鈷層之其他裝置之高電阻。藉由PVD沉積之鈷層常常為非共形的且具有影響裝置效能及穩定性的其他不規則性。此外，高深寬比特徵通常在由PVD或CVD沉積鈷材料期間產生孔隙。用於諸如ECP及電解之鈷的非氣相沉積製程，大體需要在將鈷層沉積在基板上時，將基板及其上之所有層暴露於液體浴，諸如水溶液。此外，由ECP及電解沉積製程沉積之鈷層可能常常具有相對高電阻率及較差共形膜。
當半導體領域發展到進階節點時，對於＜25 nm之開口及＞5之深寬比，圖案尺寸變得愈來愈具有挑戰。需要襯墊與塊鈷填充之間的強健黏著以便在沉積後步驟期間保持鈷材料，以實現無孔隙填充並且獲得可靠性。
因此，需要用於形成鈷層、膜及材料之改善方法及包含此種鈷層、膜及材料的裝置。
本案描述了用於沉積金屬膜之設備及方法。在一個實施例中，一種方法，包括以下步驟：在基板之頂表面上形成至少一個特徵，該至少一個特徵具有兩個相對側壁、底部及頂表面；在頂表面及至少一個特徵上形成金屬層（含鎢）；在金屬鎢層之頂表面上形成金屬膜；以及使基板退火。
一或多個實施例涉及包括金屬膜之設備。在一個實施例中，一種電子裝置包括：在其上沉積有介電層之基板；具有至少一個特徵之介電層；在介電層及至少一個特徵上之金屬鎢層；以及金屬鎢層上之金屬膜。
在一個實施例中，一種電子裝置包括：具有至少一個特徵之基板；在基板及至少一個特徵上之金屬鎢層；以及金屬鎢層上之金屬膜。
在描述本揭示案之若干示例性實施例之前，應理解，本揭示案不限於在以下描述中闡述的構造或製程步驟細節。本揭示案能夠實現其他實施例，並且能夠以各種方式實踐或進行。
如本文使用的「基板」，指任意基板或在基板上形成的材料表面，在製造過程中在所述基板或所述材料表面上執行薄膜處理。例如，在其上可執行處理的基板表面根據應用包括材料，諸如矽、氧化矽、應變矽、絕緣體上矽(silicon on insulator; SOI)、碳摻雜氧化矽、非晶矽、摻雜矽、鍺、砷化鎵、玻璃、藍寶石，以及任意其他材料，諸如金屬、金屬氮化物、金屬合金，以及其他導電材料。基板包括但不限於半導體晶圓。基板可暴露於預處理製程以研磨、蝕刻、還原、氧化、羥基化、退火及/或烘烤基板表面。除了直接在基板本身的表面上的薄膜處理外，在本揭示案中，所揭露的薄膜處理步驟的任一步也可在基板上形成的下層上執行，如下文更詳細地揭示，且術語「基板表面」意欲包括上下文指出的此種下層。因此，例如，在薄膜/層或部分薄膜/層已經沉積在基板表面上的情況下，新沉積的薄膜/層的暴露表面變成基板表面。
如本說明書及隨附申請專利範圍中使用，術語「前驅物」、「反應物」、「反應氣體」等等可互換使用以指可與基板表面反應之任何氣態物質。
如本文使用，術語「襯墊」指沿開口之側壁及/或底表面之至少一部分共形形成的層，使得在沉積層之前開口的大部分在沉積層之後仍然未填充。在一些實施例中，襯墊可沿開口之整個側壁及底表面而形成。
當前鈷填充方案為利用ALD/CVD氮化鈦(TiN)或氮化鉭(TaN)作為襯墊，然後進行PVD/CVD/電鍍鈷填充。由於對鈷之弱黏著，可觀察到利用ALD/CVD氮化鈦(TiN)或氮化鉭(TaN)襯墊的明顯局限性，其誘發在高熱預算沉積後步驟期間的層脫/分層/夾斷孔隙，及在熱和電應力下的可靠性及遷徙問題。另外，類似氮化鈦(TiN)或氮化鉭(TaN)之氮(N)處理襯墊可導致氮化鈷（CoN，在＞250℃溫度下不穩定）形成於鈷層上，損壞薄膜形態及穩定性並產生高電阻。
有利地，金屬鎢層（即基於非氮化物之襯墊）用於一或多個實施例之電子裝置中。所使用之金屬鎢層不會與含鈷之金屬膜發生不利干擾。當使用一或多個實施例之金屬鎢層時，不形成氮化鈷(CoN)。
本案描述了用於沉積金屬膜之設備及方法。在一個實施例中，一種方法包括以下步驟：在基板之頂表面上形成至少一個特徵，該至少一個特徵具有兩個相對側壁、底部及頂表面；在頂表面及至少一個特徵上形成金屬鎢層；在金屬鎢層之頂表面上形成金屬膜；以及使基板退火。此金屬鎢層主要由鎢組成且可能也包含其他元素，諸如碳、氮、氧。
在一或多個實施例中，可沉積/形成可選的介電層。在一個實施例中，方法進一步包括在形成金屬鎢層之前在基板頂表面上形成介電層的步驟。
在一些實施例中，金屬鎢層藉由將基板暴露於由第一氣體形成之電漿而形成。在一些實施例中，第一氣體包括金屬鎢前驅物氣體。在一些實施例中，第一氣體包括無氟鹵化鎢前驅物，諸如五氯化鎢(WCl5 )或六氯化鎢(WCl6 )。在其他實施例中，第一氣體包括無氟鎢氧鹵化物前驅物，諸如WOCl4 或WO2 Cl2 。在其他實施例中，第一氣體從由以下組成之群組中選出：無氟鹵化物前驅物、無氯鹵化鎢前驅物，諸如五溴化鎢(WBr5 )或六溴化鎢(WBr6 )。在一些實施例中，第一氣體進一步包括反應氣體，諸如含氫氣體，諸如氫氣(H2 )或氨氣(NH3 )或聯氨(N2 H4 )，及載氣，諸如氬氣(Ar)、氦氣(He)、氮氣(N2 )，以及金屬鎢前驅物氣體。在一些實施例中，載氣為惰性氣體。在一些實施例中，第一氣體由金屬鎢前驅物氣體、反應氣體及載氣組成或基本由其組成。在一些實施例中，第一氣體由無氯無氟鹵化鎢前驅物、含氫氣體及惰性氣體組成或基本由其組成。不意欲受理論束縛，應認為第一氣體中氫的存在有利地最小化金屬鎢襯墊層中碳雜質的存在。載氣以約10 sccm至約10 slm之流速提供。
本文所述之金屬鎢(W)襯墊/層有利地經由一或多個改進的鈷回流及改進的裝置性質（諸如電子遷徙及時間依賴的介電質擊穿）來促成改進的鈷互連結構。本發明方法可與任何裝置節點一起使用，但在約25 nm或更小（例如約5 nm至約25 nm）之裝置節點中可能特別有利。另外，在一或多個實施例中，對於藉由使鈷(Co)再流動以填充開口而形成的互連結構，方法可能特別有利。
在一或多個實施例中，金屬膜包含鈷。鈷可以藉由任何適當製程沉積，包括但不限於化學氣相沉積(chemical vapor deposition; CVD)及原子層沉積(atomic layer deposition; ALD)。在一些實施例中，鈷薄膜（亦被稱為層或縫隙填充材料）藉由CVD沉積。在一些實施例中，鈷膜藉由ALD沉積。
為說明目的，圖式示出具有單一特徵之基板；然而，熟習本領域之技術者應理解可存在多於一個特徵。特徵之形狀可為任何適當的形狀，包括但不限於尖峰、溝槽及圓柱形通孔。在特定實施例中，特徵為溝槽。在其他特定實施例中，特徵為通孔。如此方面使用，術語「特徵」意謂任何故意的表面不規則。特徵之適當實例包括但不限於具有頂部、兩個側壁及底部之溝槽、具有頂部及從表面向上延伸之兩個側壁的尖峰、及具有從表面向下延伸之側壁及開放底部的通孔。特徵可具有任何適當的深寬比（特徵之深度與特徵之寬度的比）。在一些實施例中，深寬比大於或等於約5:1、10:1、15:1、20:1、25:1、30:1、35:1或40:1。在一或多個實施例中，深寬比大於10:1。
在一或多個實施例中，至少一個特徵從基板之頂表面或金屬鎢層之頂表面延伸至底表面一深度。至少一個特徵具有由第一側壁及第二側壁定義之寬度。金屬膜沉積在金屬鎢層上以填充至少一個特徵且在金屬鎢層之頂表面上方延伸。金屬膜可經凹進以將金屬膜之頂部降低至等於或低於金屬鎢層之頂表面的高度以形成凹進金屬膜。可擴展金屬膜以形成從至少一個特徵延伸的柱。
參考第1圖及第2圖，一或多個實施例涉及形成半導體裝置100之方法。基板102具備填充有金屬膜108之特徵104。
在一或多個實施例中，金屬膜108為鈷層。在一個實施例中，鈷層為縫隙填充層。如第1圖圖示，在一個實施例中，金屬膜108沉積於特徵104之頂部部分114、特徵104之側壁116及介電層110之頂部部分118上的金屬鎢層/襯墊106上。
在一或多個實施例中，金屬膜108為晶種縫隙填充層。在一個實施例中，晶種縫隙填充層為選擇性生長晶種膜。如第1圖圖示，在一個實施例中，金屬膜108沉積於特徵104之頂部部分114、特徵104之側壁116及介電層110之頂部部分118上的金屬鎢層/襯墊106上。
如第2圖圖示，在另一個實施例中，金屬膜108沉積於特徵104之頂部部分114、特徵104之側壁116及基板102之頂表面120上的金屬鎢層/襯墊106上。
在一或多個實施例中，金屬膜108為鈷層。在一或多個實施例中，鈷層為鈷縫隙填充層。
在一或多個實施例中，金屬膜108為晶種縫隙填充層。在一或多個實施例中，晶種縫隙填充層為鈷層，或其他晶種縫隙填充層，諸如用於提供選擇性生長柱的彼等層。
在其他實施例中，金屬膜108可為另一適當金屬膜。適當的金屬膜包括但不限於，包含鈷(Co)、鉬(Mo)、鎢(W)、鉭(Ta)、鈦(Ti)、釕(Ru)、銠(Rh)、銅(Cu)、鐵(Fe)、錳(Mn)、釩(V)、鈮(Nb)、鉿(Hf)、鋯(Zr)、釔(Y)、鋁(Al)、錫(Sn)、鉻(Cr)、鑭(La)、銥(Ir)、或其組合之一或多個的薄膜。在一些實施例中，金屬膜108包含鈷(Co)縫隙填充層。
在一個實施例中，金屬膜108使用一個沉積技術來沉積，諸如但不限於ALD、CVD、PVD、MBE、MOCVD、旋塗或在微電子裝置製造領域為一般技藝人士熟知之其他襯墊沉積方法。在一個實施例中，金屬膜108使用在微電子裝置製造領域為一般技藝人士熟知之CVD沉積技術來沉積。
在一或多個實施例中，金屬膜108包含鈷。在特定實施例中，金屬膜108包括已藉由任何適當製程沉積的鈷，適當製程包括但不限於化學氣相沉積(chemical vapor deposition; CVD)及原子層沉積(atomic layer deposition; ALD)。在一些實施例中，金屬膜108包括藉由CVD沉積的鈷（亦稱為層或縫隙填充材料）。金屬膜108具有暴露以用於進一步處理的表面112。
在一或多個實施例中，介電層110形成於基板102上。介電層可為任何適當介電材料，包括但不限於鈦或矽之氮化物、氧化物或碳化物。介電層110可在基板102上共形或非共形地形成。
在一個實施例中，介電層110包括具有小於5之介電常數值的介電材料。在一個實施例中，介電層110包括具有小於2之介電常數值的介電材料。在至少一些實施例中，介電層110包括氧化物、碳摻雜氧化物、多孔二氧化矽、碳化物、碳氧化物、氮化物、氮氧化物、氮碳氧化物、聚合物、磷矽酸鹽玻璃、氟矽酸鹽(SiOF)玻璃、有機矽酸鹽玻璃(SiOCH)或其組合。在至少一些實施例中，介電層110可包括聚醯亞胺、環氧樹脂、光可界定材料，諸如苯并環丁烯（benzocyclobutene; BCB）、及WPR系列材料、或旋塗玻璃。
在一個實施例中，介電層110之厚度在約10奈米(nm)至約2微米(μm)之近似範圍中。在實施例中，介電層110使用沉積技術中之一個沉積，諸如但不限於化學氣相沉積(chemical vapor deposition; CVD)、物理氣相沉積(physical vapor deposition; PVD)、分子束磊晶(molecular beam epitaxy; MBE)、金屬有機化學氣相沉積(metalorganic chemical vapor deposition; MOCVD)、原子層沉積(atomic layer deposition; ALD)、旋塗、或在微電子裝置製造領域中為一般技藝人士熟知之其他隔離沉積方法。
在一個實施例中，金屬鎢層106沉積於介電層110上。在一個實施例中，金屬鎢層106為導電襯墊。在一些實施例中，金屬鎢層106藉由將基板102暴露於由第一氣體形成之電漿而形成。在一些實施例中，第一氣體包括金屬鎢前驅物氣體。在一些實施例中，第一氣體包括無氟鹵化鎢前驅物，諸如五氯化鎢(WCl5 )或六氯化鎢(WCl6 )。在其他實施例中，第一氣體包括無氟鎢氧鹵化物前驅物，諸如WOCl4 或WO2 Cl。在其他實施例中，第一氣體從由以下組成之群組中選出：無氟鹵化物前驅物、無氯鹵化鎢前驅物，諸如五溴化鎢(WBr5 )或六溴化合鎢(WBr6 )。在一些實施例中，第一氣體進一步包括反應氣體，諸如含氫氣體，諸如氫氣(H2 )或氨氣(NH3 )或聯氨(N2 H4 )，及載氣，諸如氬氣(Ar)、氦氣(He)、氮氣(N2 )，以及金屬鎢前驅物氣體。在一些實施例中，載氣為惰性氣體。在一些實施例中，第一氣體由金屬鎢前驅物氣體、反應氣體及載氣組成或基本由其組成。在一些實施例中，第一氣體由無氯無氟鹵化鎢前驅物、含氫氣體及惰性氣體組成或基本由其組成。不意欲受理論束縛，應認為第一氣體中氫的存在有利地最小化金屬鎢襯墊層中碳雜質的存在。載氣可以約100 sccm至約3000 seem之流速提供。
在一實施例中，將金屬鎢層106沉積至約5埃至約35埃之厚度。在一實施例中，將金屬鎢層106沉積至約10埃至約30埃之厚度。不意欲受理論束縛，應認為一或多個實施例之金屬鎢層/襯墊提供相比於包含TiN之相當厚度襯墊具有更少抗濕潤性之金屬薄膜。在特定實施例中，金屬鎢層/襯墊提供改進鈷與鎢黏著，並且在TiN上黏著更差時在比10埃薄之金屬鎢上觀察不到抗濕潤。
在一或多個實施例中，金屬膜108包含鈷，且相比於氮化鈦(TiN)襯料，即使使用10埃鎢襯墊，也顯示出對鈷之增強黏著。在一或多個實施例中，在氫(H2 )退火之後，包含鈷之金屬膜108在10埃至30埃的鎢襯墊上未顯示任何抗濕潤，而包含鈷之金屬膜108在氮化鈦(TiN)襯墊上抗濕潤。
在一或多個實施例中，金屬鎢層/襯墊106提供具有較低電阻之電子裝置，電子裝置具有氮化鈦(TiN)或氮化鉭(TaN)襯墊。
在一或多個實施例中，在金屬鎢層106與含鈷之金屬膜108之間不存在擴散或存在非常有限之混合。在一或多個實施例中，當沉積金屬鎢層106時金屬膜108不發生氧化。不意欲受理論束縛，應認為，當金屬鎢層106包含無氟(F)無氯(Cl)鎢層/襯墊時，襯墊阻止氟與金屬膜108相互作用。
在一些實施例中，金屬鎢前驅物流進包含基板102之處理腔室中，處理腔室具有惰性氣體、載氣及/或稀釋氣體。金屬鎢前驅物可化學吸附至基板102或介電層110，以在基板或介電層上留下化學吸附的金屬鎢前驅物。隨後共反應物可流入處理腔室中與化學吸附的金屬鎢前驅物反應，以沉積金屬鎢層106。在一些實施方式中，前驅物與共反應物共流進處理腔室中。前驅物及共反應物可在氣相中反應且形成沉積於基板或圖案化膜上之物質，以生長膜140。
在一實施例中，金屬鎢層106使用原子層沉積(atomic layer deposition; ALD)技術沉積。在一個實施例中，金屬鎢層106使用一個沉積技術來沉積，諸如但不限於CVD、PVD、MBE、MOCVD、旋塗或在微電子裝置製造領域為一般技藝人士熟知之其他襯墊沉積方法。
在形成之後，在低溫及高壓下使金屬膜108退火。如此方面使用，術語「低溫」意謂在退火製程期間之最大溫度小於或等於約400℃。在一些實施例中，最大退火溫度小於或等於約375℃、350℃、325℃、300℃、275℃、250℃、225℃、200℃、180℃、或150℃。如此方面使用，術語「高壓」意謂大於或等於約1托之壓力。在一些實施例中，退火壓力大於或等於2托、3托、4托、5托、6托、7托、8托、9托、10托、15托、20托、25托、30托、35托、40托、45托、50托、60托、70托、80托、90托、100托、110托、120托、130托、140托、150托、200托、250托、300托、350托、400托、450托、500托、550托、600托、650托、或700托。在一些實施例中，退火壓力在約1托至約700托之範圍中，或約5托至約100托之範圍中，或約10托至約80托之範圍中。
退火製程期間之氣氛可根據例如金屬矽化物膜而改變。在一些實施例中，金屬矽化物膜具有包括氫、氘及氬之一或多種的退火氣氛。在一些實施例中，退火氣氛包括氬氣中約2% H2 、氬氣中約4% H2 、氬氣中約6% H2 、氬氣中約8% H2 或氬氣中約10% H2 。在一些實施例中，退火氣氛基本上由在氬氣中之氫氣組成。在一些實施例中，退火氣氛包含氘。在一些實施例中，退火氣氛基本由氘組成。在一些實施例中，退火氣氛基本由氬氣組成。如此方式使用，由組分「基本組成」之退火氣氛意謂氣氛大於或等於所列組分之約98%、99%或99.5%。
退火氣氛可處於靜態條件或恆流條件下。在一些實施例中，退火氣氛為靜態的，以便退火在實質上沒有流動氣體之條件下進行。例如，退火腔室可使用預定氣氛組分加壓且隨後密封，以便在腔室內不存在氣體流動。
經退火金屬鎢層/襯墊106具有小於或等於約20 歐姆-公分、19歐姆-公分、18歐姆-公分、17歐姆-公分、16歐姆-公分、15歐姆-公分、14歐姆-公分、13歐姆-公分、12歐姆-公分、11歐姆-公分或10歐姆-公分。在一或多個實施例中，經退火金屬鎢層/襯墊106顯示比包含ALV/CVD氮化鈦(TiN)之層/襯墊的電阻率小50%以上。在一或多個實施例中，經退火金屬鎢層/襯墊106顯示比包含ALV/CVD氮化鈦(TiN)之層/襯墊的電阻率小75%以上。
在上述說明書中，已經參考本揭示案特定示例性實施例描述了其實施例。顯而易見，可以在不脫離由下列申請專利範圍中闡述之本揭示案之實施例的寬泛精神及範圍之情況下，對其進行各種修改。因此，認為本說明書及附圖是說明性意義而不是限制性意義。
100‧‧‧半導體裝置 102‧‧‧基板 104‧‧‧特徵 106‧‧‧金屬鎢層/襯墊 108‧‧‧金屬膜 110‧‧‧介電層 112‧‧‧表面 114‧‧‧頂部部分 116‧‧‧侧壁 118‧‧‧頂部部分 120‧‧‧頂表面
因此，為了能夠詳細理解本揭示案的上述特徵結構所用方式，上文所簡要概述的本揭示案的更具體的描述可以參考各個實施例進行，所述實施例中的一些示出於附圖中。然而，應注意，附圖僅示出本揭示案的典型實施方式並因此不應視為對本揭示案範圍的限制，因為本揭示案可承認其他同等有效的實施方式。本文所述實施例以舉例方式說明且並不限於隨附的圖式中，其中類似標記表示類似元件。
第1圖根據本揭示案之一或多個實施例圖示半導體裝置之剖面示意圖；以及
第2圖根據本揭示案之一或多個實施例圖示半導體裝置之剖面示意圖。
在附加圖式中，類似部件及/或特徵可具有相同參考標記。另外，相同類型之各種部件藉由在參考標記後面加上的破折號及在類似部件中區分的第二標記來區分。若在說明書中僅使用第一參考標記，則描述適用於具有相同第一參考標記之任一個類似部件，而不管第二參考標記如何。
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無
國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無
100‧‧‧半導體裝置
102‧‧‧基板
104‧‧‧特徵
106‧‧‧金屬鎢層/襯墊
108‧‧‧金屬膜
110‧‧‧介電層
112‧‧‧表面
114‧‧‧頂部部分
116‧‧‧側壁
118‧‧‧頂部部分
120‧‧‧頂表面

Claims (20)

  1. 一種用於沉積金屬膜之方法，包括以下步驟：在一基板之一頂表面上形成至少一個特徵；在該頂表面及該至少一個特徵上形成一金屬鎢層；在該金屬鎢層之一頂表面上形成一金屬膜；以及使該基板退火。
  2. 如請求項1所述之方法，進一步包括以下步驟：在形成該金屬鎢層的步驟之前在該基板之該頂表面上方形成一介電層。
  3. 如請求項1所述之方法，其中該金屬鎢層藉由將該基板暴露於由一第一氣體形成之一電漿而形成。
  4. 如請求項3所述之方法，其中該第一氣體包括一金屬鎢前驅物氣體。
  5. 如請求項3所述之方法，其中該第一氣體從以下組成之群組中選出：無氟鎢氧鹵化物前驅物、無氯鹵化鎢前驅物、無氟無氯鎢前驅物。
  6. 如請求項3所述之方法，其中該第一氣體包括一無氟無氯鎢前驅物。
  7. 如請求項3所述之方法，其中該第一氣體進一步包括一反應氣體。
  8. 如請求項7所述之方法，其中該反應氣體從 由以下組成之群組中選出：氫氣(H2)、氨氣(NH3)、及聯氨(N2H4)。
  9. 如請求項3所述之方法，其中該第一氣體進一步包括從由以下組成之群組中選出之一載氣：氬氣(Ar)、氦氣(He)、氮氣(N2)。
  10. 如請求項1所述之方法，其中該金屬膜包含鈷。
  11. 如請求項10所述之方法，其中該鈷包括CVD鈷。
  12. 如請求項1所述之方法，其中該至少一個特徵從以下選出：一溝槽、一通孔、或一尖峰。
  13. 如請求項1所述之方法，進一步包括以下步驟：在沉積該金屬膜之前真空破壞。
  14. 如請求項1所述之方法，其中該退火步驟發生在一H2(氣體)氣氛中。
  15. 一種電子裝置，包括：一基板；至少一個特徵；一金屬鎢層，形成於該至少一個特徵上；以及一金屬膜，形成於該金屬鎢層上。
  16. 如請求項15所述之電子裝置，其中該金屬膜包含鈷。
  17. 如請求項15所述之電子裝置，其中該特徵從由以下組成之群組中選出：一溝槽、一通孔、及一尖峰。
  18. 如請求項15所述之電子裝置，其中該至少一個特徵形成於該基板上。
  19. 如請求項15所述之電子裝置，進一步包括形成於該基板上之一介電層、形成於該介電層上之該至少一個特徵。
  20. 一種電子裝置，包括：一基板，具有一可選的介電層；至少一個特徵，形成於該基板中或該可選的介電層中；一金屬鎢層，在該基板上及該至少一個特徵上；以及一金屬膜，形成於該金屬鎢層上，該金屬膜包含鈷。
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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115136285A (zh) * 2020-01-16 2022-09-30 恩特格里斯公司 蚀刻或沉积的方法
US11587936B2 (en) 2021-02-26 2023-02-21 Applied Materials, Inc. Low resistivity DRAM buried word line stack

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080085611A1 (en) * 2006-10-09 2008-04-10 Amit Khandelwal Deposition and densification process for titanium nitride barrier layers
US20120231626A1 (en) * 2011-03-10 2012-09-13 Applied Materials, Inc. Formation of liner and barrier for tungsten as gate electrode and as contact plug to reduce resistance and enhance device performance
US20140162451A1 (en) * 2009-04-16 2014-06-12 Novellus Systems, Inc. Methods for depositing ultra thin low resistivity tungsten film for small critical dimension contacts and interconnects

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG87187A1 (en) 1999-10-18 2002-03-19 Applied Materials Inc Pvd-imp tungsten and tungsten nitride as a liner, barrier and/or seed layer for tungsten, aluminium and copper applications
US7074709B2 (en) * 2002-06-28 2006-07-11 Texas Instruments Incorporated Localized doping and/or alloying of metallization for increased interconnect performance
US6930391B2 (en) 2002-08-27 2005-08-16 Intel Corporation Method for alloy-electroplating group IB metals with refractory metals for interconnections
KR101035221B1 (ko) * 2002-12-27 2011-05-18 가부시키가이샤 알박 질화 텅스텐막의 형성 방법
WO2005101473A1 (ja) * 2004-04-12 2005-10-27 Ulvac, Inc. バリア膜の形成方法、及び電極膜の形成方法
KR100806128B1 (ko) * 2006-12-11 2008-02-22 삼성전자주식회사 반도체 소자의 배선 구조물 및 이의 형성방법
US8053861B2 (en) * 2009-01-26 2011-11-08 Novellus Systems, Inc. Diffusion barrier layers
US9129945B2 (en) * 2010-03-24 2015-09-08 Applied Materials, Inc. Formation of liner and barrier for tungsten as gate electrode and as contact plug to reduce resistance and enhance device performance
US9748137B2 (en) * 2014-08-21 2017-08-29 Lam Research Corporation Method for void-free cobalt gap fill
US9349637B2 (en) * 2014-08-21 2016-05-24 Lam Research Corporation Method for void-free cobalt gap fill
US9754824B2 (en) * 2015-05-27 2017-09-05 Lam Research Corporation Tungsten films having low fluorine content
US9972504B2 (en) * 2015-08-07 2018-05-15 Lam Research Corporation Atomic layer etching of tungsten for enhanced tungsten deposition fill
US10121671B2 (en) * 2015-08-28 2018-11-06 Applied Materials, Inc. Methods of depositing metal films using metal oxyhalide precursors
CN108431924B (zh) 2015-11-25 2024-03-22 应用材料公司 通过集成工艺流程系统形成低电阻触点的方法
CN109690755A (zh) * 2016-09-30 2019-04-26 英特尔公司 使用含钨粘合层增强互连可靠性能以实现钴互连的微电子器件和方法
US20180144973A1 (en) 2016-11-01 2018-05-24 Applied Materials, Inc. Electromigration Improvement Using Tungsten For Selective Cobalt Deposition On Copper Surfaces
TW201840903A (zh) 2016-11-20 2018-11-16 美商應用材料股份有限公司 選擇性沉積無腐蝕金屬觸點之方法
US10319632B2 (en) * 2016-12-14 2019-06-11 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor interconnect structure having a graphene barrier layer
US10177030B2 (en) * 2017-01-11 2019-01-08 International Business Machines Corporation Cobalt contact and interconnect structures
US10204828B1 (en) * 2018-02-09 2019-02-12 International Business Machines Corporation Enabling low resistance gates and contacts integrated with bilayer dielectrics

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080085611A1 (en) * 2006-10-09 2008-04-10 Amit Khandelwal Deposition and densification process for titanium nitride barrier layers
US20140162451A1 (en) * 2009-04-16 2014-06-12 Novellus Systems, Inc. Methods for depositing ultra thin low resistivity tungsten film for small critical dimension contacts and interconnects
US20120231626A1 (en) * 2011-03-10 2012-09-13 Applied Materials, Inc. Formation of liner and barrier for tungsten as gate electrode and as contact plug to reduce resistance and enhance device performance

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