CN108431924B - 通过集成工艺流程系统形成低电阻触点的方法 - Google Patents

通过集成工艺流程系统形成低电阻触点的方法 Download PDF

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CN108431924B
CN108431924B CN201680069176.XA CN201680069176A CN108431924B CN 108431924 B CN108431924 B CN 108431924B CN 201680069176 A CN201680069176 A CN 201680069176A CN 108431924 B CN108431924 B CN 108431924B
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tungsten
substrate
gas
layer
liner layer
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CN108431924A (zh
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雷雨
维卡什·班西埃
吴凯
傅新宇
徐毅
大东和也
马飞跃
普及特·阿咖瓦
林驰筹
吴典晔
简国强
薇·V·唐
乔纳森·巴克
张镁
森德·拉马默蒂
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Applied Materials Inc
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Applied Materials Inc
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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    • C23C16/45523—Pulsed gas flow or change of composition over time
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Abstract

本文提供用于形成具有钨衬垫层的金属触点的方法。在一些实施方式中，一种处理基板的方法包括：在第一基板处理腔室内将基板暴露至等离子体以沉积钨衬垫层，该等离子体是由第一气体形成，该第一气体包括金属有机钨前驱物气体或无氟卤化钨前驱物，其中该钨衬垫层沉积在介电层顶上且于特征内，该特征形成在基板的该介电层的第一表面中；将该基板传送到第二基板处理腔室而不将该基板暴露至大气；以及将该基板暴露至第二气体以在该钨衬垫层顶上沉积钨填充层，该第二气体包括氟化钨前驱物。

Description

通过集成工艺流程系统形成低电阻触点的方法
技术领域
本公开内容的实施方式一般涉及处理基板的方法。
背景技术
传统的金属触点的形成是由下伏的金属层、钨衬垫层、与化学气相沉积(CVD)钨层构成，上述层一般都是在分别的系统中处理。于是，在后续的CVD钨层沉积之前及沉积之后，钨衬垫层暴露至大气(atmosphere)。大气中的氧与湿气使钨衬垫层的顶表面氧化，且形成一般为10至20埃的氧化物层。
该衬垫层材料的氧化部分一般具有非常高的电阻率(例如大于约1E3μOhm-cm)，而未氧化的衬垫层材料的电阻率一般是低于1E3μOhm-cm。因此，衬垫层的氧化物部分的存在会引发对金属触点有一些额外的电阻。
后续沉积的CVD钨层形成于该衬垫层的顶表面上。该CVD钨层的培养延迟取决于该衬垫层的表面膜性质而有所差异。氧化物膜引发比未氧化或部分氧化的膜有更多的延迟。此外，培养延迟在基板的场区域及特征(例如，通孔或沟槽)内之间可能有所差异，而造成CVD钨缝隙填充工艺期间有空隙(void)或大接缝(seam)。此类孔隙或大接缝的存在会造成更高的触点电阻及不良的可靠度。
随着集成电路的特征尺寸持续缩小，特别是对于20nm等级的触点结构(例如，沟槽或通孔)而言，来自氧化衬垫材料的对触点电阻的贡献将会显著地增加且引发高触点电阻，而限制装置驱动电流且劣化装置效能。此外，培养延迟差异能够引发严重的缝隙填充问题(诸如空隙)，造成不良的可靠度和高电阻。
从而，发明人已提供用于有钨衬垫层的金属触点形成的改良方法。
发明内容
本文提供形成具有钨衬垫层的金属触点的方法。在一些实施方式中，一种处理基板的方法包括：在第一基板处理腔室内将基板暴露至等离子体以在第一基板处理腔室内沉积钨衬垫层，该等离子体是由第一气体形成，该第一气体包括金属有机钨前驱物气体或无氟卤化钨前驱物，其中该钨衬垫层沉积在介电层顶上且于特征内，该特征形成在基板的该介电层的第一表面中；将该基板传送到第二基板处理腔室而不将该基板暴露至大气；以及将该基板暴露至第二气体以在该钨衬垫层顶上沉积钨填充层，该第二气体包括氟化钨前驱物。
在一些实施方式中，一种处理基板的方法包括：于约200摄氏度至约400摄氏度的温度将该基板暴露至六氟化钨(WF6)气体达约0.5秒至约600秒或于约300摄氏度至约500摄氏度的温度将该基板暴露至氢(H2)气达约0.5秒至约600秒；在第一基板处理腔室内将基板暴露至等离子体以沉积钨衬垫层，该等离子体是由第一气体形成，该第一气体包括金属有机钨前驱物气体或无氟卤化钨前驱物，其中该钨衬垫层沉积在介电层顶上且于特征内，该特征形成在基板的该介电层的第一表面中；将该基板传送到第二基板处理腔室而不将该基板暴露至大气；以及将该基板暴露至第二气体以在该钨衬垫层顶上沉积钨填充层，该第二气体包括氟化钨前驱物。
在一些实施方式中，提供一种计算机可读介质，该计算机可读介质具有存储于该计算机可读媒体上的指令，所述指令当经执行时，引发处理腔室执行处理基板的方法。该方法可包括本文公开的所述方法的任一者。
下文描述本公开内容的其他与进一步的实施方式。
附图说明
通过参考绘示于附图中的本公开内容的说明性实施方式，可得到上文简要总结且于下文更详细论述的本公开内容的实施方式。然而，附图仅说明本公开内容的典型实施方式，因此不应被视为限制本公开内容的范围，因为本公开内容可容许其他等效实施方式。
图1描绘根据本公开内容的一些实施方式的用于处理基板的方法的流程图。
图2A至图2C描绘根据本公开内容的一些实施方式的基板中形成的互连件结构的侧截面视图。
图3描绘群集工具，该群集工具适合执行根据本公开内容的一些实施方式的用于处理基板的方法。
为了促进了解，在可能之处已使用相同的附图标记指定各图共通的相同元件。所述附图并未按照比例尺绘制，且可为了明确起见而经简化。一个实施方式的元件和特征可有利地并入其他实施方式而无须赘述。
具体实施方式
本文提供形成具有钨衬垫层的金属触点的方法。本文所述的发明方法可有利地用于通过避免氧化钨衬垫层而促进形成改良的金属触点、通孔和栅极，以避免高触点电阻与不良的缝隙填充。通过避免氧化钨衬垫层，能够减少衬垫厚度，造成触点电阻减少且供后续CVD钨缝隙填充的空间增加，而减少空隙或较大接缝的风险且改良装置可靠度。
本文所述的发明方法可与任何装置节点并用，但可特别有利于约10nm或更小的装置节点。如本文所用的“衬垫层”可指如此的层：该层沿着特征的侧壁和/或下表面的至少一部分正形地形成，使得在沉积该层前的该特征的实质部分在沉积该层之后维持未填充。在一些实施方式中，该衬垫层可沿着该特征的侧壁与下表面的整体形成。
图1描绘根据本公开内容的一些实施方式的用于形成金属触点的方法100的流程图。该方法100可在任何适合的处理腔室中执行，所述处理腔室配置成用于化学气相沉积(CVD)或原子层沉积(ALD)的一或多者，该原子层沉积诸如为等离子体增强ALD或是热ALD(即，无等离子体形成)。可用于执行本文公开的发明方法的示范性处理系统可包括(但不限于)那些 或/>处理系统线和/>Plus或SIPPVD处理腔室，上述的处理系统与处理腔室都可购自美国加州圣克拉拉市的应用材料公司。其他处理腔室(包括来自其他制造商的那些处理腔室)也可合适地与本文提供的教示一并使用。
可在基板200上执行方法100，如图2A所描绘，该基板200具有特征202，该特征202形成在该基板200的第一表面204中且朝向该基板200的相对的第二表面206延伸进入基板200。基板200可以是任何能够在该基板200上沉积有材料的基板，诸如硅基板、三五族化合物基板、硅锗(SiGe)基板、外延基板、绝缘体上覆硅(SOI)基板、显示器基板(诸如液晶显示器(LCD)、等离子体显示器、电致发光(EL)灯显示器)、太阳能阵列、太阳电池板、发光二极管(LED)基板、半导体晶片、或类似物。在一些实施方式中，一或多个额外层可设置在该基板上，使得该钨衬垫层(如下文所述)可至少部分地形成在该基板上。举例而言，在一些实施方式中，包括金属、氮化物、氧化物、或类似物、或上述的组合的层可设置在基板上且可具有形成在此类的一或多层上的钨层。
基板200可以是在基板中形成有特征202的任何适合的基板。例如，基板200可包括介电材料、硅(Si)、金属、或类似物的一或多者。此外，基板200可包括额外的多层的材料或可具有在基板200上或基板200中形成的一或多个完成的或是部分完成的结构。例如，基板200可包括第一介电层212，该第一介电层212诸如是氧化硅、低k材料(例如，介电常数低于氧化硅或低于约3.9的材料)、或类似物。特征202可形成在第一介电层212中。在一些实施方式中，第一介电层212可设置在第二介电层214顶上，该第二介电层214诸如为氧化硅、氮化硅、碳化硅、或类似物。导电材料(例如导电材料220)可设置在第二介电层214中，且可对齐特征202，使得特征202在填有导电材料时提供至导电材料及来自导电材料的电路径。例如，导电材料可以是互连件所耦接的线路或插塞的一部分。
特征202可以是任何开口，诸如通孔、沟槽、双镶嵌结构、或类似物。在一些实施方式中，特征202可具有高深宽比，例如约1:1或更大的深宽比。如在本文所使用，深宽比是特征的深度对特征的宽度的比例。如图2A中所描绘，特征202可通过使用任何适合的蚀刻工艺蚀刻第一介电层212而形成。特征202包括底表面208与侧壁210。
在一些实施方式中，且如图2A至图2C中虚线所绘示，特征202可延伸完全通过第一介电层212和第二基板228的上表面226，并且该特征202可形成该特征202的底表面208。第二基板228可设置成邻接基板200的第二表面206。另外(且也以虚线绘示)，导电材料(例如导电材料220)可设置在第二基板228的上表面226中且对齐特征202，该导电材料例如为装置(诸如逻辑装置或类似物)的一部分或者为要求电连接性的至装置的电路径的一部分，诸如栅极、接触垫、导电线路、或插塞、或类似物。
在102，且如图2B所描绘，钨衬垫层216沉积在第一介电层212顶上且在特征202内，该特征202形成在基板200的第一介电层212的第一表面204中。例如，特征202的侧壁210、特征202的底表面208、和基板200的第一表面204可被钨衬垫层216所覆盖。
在一些实施方式中，钨衬垫层216是通过将基板200暴露至等离子体而形成，该等离子体是由第一气体形成。在一些实施方式中，第一气体包括金属有机钨前驱物气体。在一些实施方式中，第一气体包括无氟卤化钨前驱物，诸如五氯化钨(WCl5)或六氯化钨(WCl6)。在一些实施方式中，第一气体进一步包括伴随钨前驱物气体的反应物气体和载气，该反应物气体诸如含氢气体(诸如氢(H2)或氨(NH3))，该载气诸如氩、氦、或氮。该载气是惰性气体。在一些实施方式中，该第一气体由金属有机钨前驱物气体、反应物气体、与载气所组成，或基本上由上述气体组成。在一些实施方式中，该第一气体由无氟卤化钨前驱物、含氢气体、与惰性气体所组成，或基本上由上述气体组成。第一气体中氢的存在有利地将钨衬垫层216中碳不纯物的存在减至最小。载气是以约100sccm至约3000sccm的流率提供。
钨衬垫层216作为适合用于后续形成下文所述的钨填充层的表面，且也可用于防止后续沉积的金属层扩散进入下面的层，诸如第一介电层212。钨衬垫层216可具有适合附着至下面的层且促进形成下文所述的钨填充层的任何厚度。例如，在一些实施方式中，钨衬垫层216可具有约10埃至约50埃的厚度。钨衬垫层216的减少的厚度可增加工艺流程系统的产率。
在一些实施方式中，适合的金属有机钨前驱物可包括具有下述化学式的前驱物：W(A)(B)2(C)、或W(A)(B)3(D)、或W(B)6、或W(A)2(D)2、或W(B)6-x(B2)x、或W(E)4、或W(F)3、或W(F)2(B)2、或W(F)(B)4，其中A是带负电6个电子的施主，B是中性2个电子的施主，C是带正电2个电子的施主，D是带负电2个电子的施主，E是带负电4个电子的施主，F是中性4个电子的施主，且x是从0至6的正整数。示范性的适合的前驱物包括：W(CO)6、CpW(CO)2NO、EtCpW(CO)2NO、Cp*W(CO)3NO、Cp2WH2、C4H9CNW(CO)5、(C5H11CN)W(CO)5、W(C3H5)4、W(C3H4CH3)4、W(C4H6)3、W(C4H6)2(CO)2、或W(C4H6)(CO)4。
在一些实施方式中，钨衬垫层216是在第一处理腔室内形成，该第一处理腔室诸如等离子体增强化学气相沉积处理腔室(PECVD)或等离子体增强原子层沉积处理(PEALD)腔室，其中基板200暴露至处于等离子体态的钨前驱物。该等离子体可通过下述方式形成：耦合足够能量(例如来自电源的射频(RF)能量)以将第一气体点燃而形成等离子体。在一些实施方式中，作为说明，电源可提供适当频率(诸如约13.56MHz)下的约50W至约1.2kW的功率。该等离子体促进分解前驱物，引发材料沉积于基板200上，而形成钨衬垫层216。
上文所述的形成钨衬垫层216的大体处理条件包括维持适合的处理腔室压力与温度以供沉积钨衬垫层216。例如，在一些实施方式中，处理腔室处于约0.5至约40托的压力。在一些实施方式中，形成钨衬垫层216期间的处理腔室的温度为约125摄氏度至约425摄氏度。
在一些实施方式中，在将钨衬垫层216沉积于第一介电层212顶上和特征202内(该特征形成于基板200的第一介电层212的第一表面204中，如上文于102所述)之前，先执行预清洁工艺，以从任何下面的金属层(例如导电材料220)的表面移除氧化的材料。最常用的预清洁工艺是以等离子体为基础，使用高能量氩离子或混有氢离子的氩离子轰击金属氧化物。然而，高能量离子也轰击介电质原子或分子且移除一些介电材料，而会例如通过形成悬垂物(overhang)而显著地改变沟槽或通孔的形状，而导致后续缝隙填充工艺中有空隙因而导致高触点电阻。发明人已观察到，基于选择性化学反应的预清洁工艺(尤其是其中存在钨或钴而作为下面的金属层)有利地减少或防止沟槽或通孔的形状改变。该清洁工艺(1)于约200摄氏度至约400摄氏度的温度将六氟化钨(WF6)气体导至基板200的表面，或是(2)于约300摄氏度至约500摄氏度的高温将氢(H2)气导至基板200的表面。该基板暴露至六氟化钨(WF6)气体或氢(H2)气达约0.5秒至约600秒。在其中存在钨或钴而作为下面的导电材料220的实施方式中，氧化物可为氧化钨(WOx)(例如WO3)或氧化钴(CoOx)(例如CoO2)。于如上文所述的温度，氧化钨与六氟化钨(WF6)反应，此是根据下述的反应：WO3+2WF6→3WOF4(气体)。于如上文所述的温度，氧化钴与六氟化钨(WF6)反应，此是根据下述的反应：CoO2+WF6→CoF2(气体)+WOF4(气体)。于如上文所述的温度，氧化钨与氢(H2)气反应，此是根据下述的反应：WO3+6H2→W+6H2O(气体)。于如上文所述的温度，氧化钴与氢(H2)气反应，此是根据下述的反应：CoO2+2H2→Co+2H2O(气体)。在最高达约500摄氏度的温度，导入的预清洁气体(即，六氟化钨(WF6)气体或是氢(H2)气)不会与介电材料反应，该介电材料诸如是氧化硅(SiO2)和氮化硅(Si3N4)。因此，该预清洁工艺有利地限制或防止(由离子轰击引起的)结构上的改变且限制或防止悬垂物形成，而造成良率改良的无空隙的缝隙填充工艺。
接着，在104，基板200从第一腔室传送到第二处理腔室而不将基板暴露至大气。发明人已观察到，暴露至大气中的氧和湿气会氧化钨衬垫层216的顶表面，且形成厚度约10埃至约20埃的氧化物层。发明人已观察到，钨衬垫层216的氧化物部分的存在增加金属触点电阻。此外，发明人已观察到，钨衬垫层216的氧化物部分的存在增加下文中于106所描述的形成钨填充层的培养延迟。培养延迟造成沉积钨填充层期间形成空隙或大接缝。从而，发明人已观察到，避免钨衬垫层216的氧化有利地防止金属触点的电阻增加，且防止金属触点中形成空隙与接缝。
接着，在106(且如图2C所描绘)，钨填充层224沉积覆于钨衬垫层216上，而填充特征202。可通过化学气相沉积工艺使用氟化钨前驱物沉积该钨填充层224。举例而言，在一些实施方式中，可通过化学气相沉积工艺沉积该钨填充层224，该工艺是使用诸如六氟化钨(WF6)或六氟化钨(WF6)与含氢气体(诸如氢(H2)或氨(NH3))的组合的氟化钨前驱物。在一些实施方式中，在沉积钨填充层224之前，将钨成核层沉积在钨衬垫层216顶上。在一些实施方式中，成核层是经由原子层沉积工艺沉积，其中基板200循环式暴露至钨前驱物气体和还原气体，该钨前驱物气体诸如为六氯化钨(WCl6)，该还原气体诸如为硅烷或二硼烷。在一些实施方式中，成核层的厚度为约15埃至约20埃。
可填充特征202达到超过基板200的上表面的水平(level)，且沉积的材料(例如钨衬垫层216)与钨填充层224可留在基板200的上表面上。因此，可使用诸如酸性溶液中的湿清洁、化学或电化学机械研磨、或类似物的技术以从上表面移除过剩的沉积材料，使得特征202填有沉积的导电材料达到大约与基板上表面相当的水平，如图2C所描绘。
可在单独的处理腔室中执行本文所述的方法，该单独的处理腔室可以独自的配置方式设置，或设置成群集工具的一部分，该群集工具例如为下文中针对图3所描述的集成工具300(即，群集工具)。集成工具300的范例包括及/>与/>集成工具产线，上述工具可购自美国加州圣克拉拉市的应用材料公司。可使用其他群集工具实行本文所述的方法或在其他适合的处理腔室中实行本文所述的方法，所述其他群集工具具有与所述工具耦接的适合的处理腔室。例如，在一些实施方式中，上文论述的发明方法可在集成工具中执行，使得处理步骤之间有受限的破真空(vacuum break)或无破真空。例如，减少的破真空可限制或防止对钨衬垫层或基板其他部分的污染(例如，氧化)
集成工具300包括真空密封(vacuum-tight)处理平台(处理平台301)、工厂接口304、与系统控制器302。处理平台301包括多个处理腔室，诸如314A、314B、314C、与314D，上述处理腔室可操作地耦接(operatively coupled)真空基板传送腔室(传送腔室303)。工厂接口304由一或多个装载锁定腔室(两个装载锁定腔室，诸如图4中所示的304A与304B)可操作地耦接传送腔室303。
在一些实施方式中，工厂接口304包括至少一个坞站(docking station)307、至少一个工厂接口机器人338，以促进传送半导体基板。坞站307配置成接收一或多个前开式标准舱(FOUP)。图3的实施方式中显示四个FOUP，诸如305A、305B、305C、与305D。工厂接口机器人338配置成将基板从工厂接口304经由装载锁定腔室(诸如306A、306B)传送到处理平台301。装载锁定腔室306A与306B的各者具有第一通口与第二通口，该第一通口耦接工厂接口304，该第二通口耦接传送腔室303。装载锁定腔室306A与306B耦接压力控制系统(图中未图标)，该压力控制系统泵抽降压装载锁定腔室306A与306B并且使装载锁定腔室306A与306B通气，以促进在传送腔室303的真空环境与工厂接口304的实质上周围(例如大气的)环境之间传递基板。传送腔室303具有真空机器人342，该真空机器人342设置在传送腔室303内。真空机器人342能够在装载锁定腔室306A与306B以及处理腔室314A、314B、314C、与314D之间传送基板321。
在一些实施方式中，处理腔室314A、314B、314C、与314D耦接传送腔室303。处理腔室314A、314B、314C、与314D包括至少等离子体增强原子层沉积(PEALD)腔室、以及化学气相沉积(CVD)腔室。也可设置额外的腔室，诸如额外的CVD腔室和/或退火腔室、物理气相沉积(PVD)腔室、脱气腔室、预清洁腔室、具接缝抑制功能的CVD腔室、或类似腔室。CVD与退火腔室可包括适合执行如上文所论述的本文所述方法的全部或多个部分的那些腔室的任一者。
在一些实施方式中，一或多个视情况任选的服务腔室(显示为316A与316B)可耦接传送腔室303。所述服务腔室316A与316B可配置成执行其他基板工艺，诸如脱气、定向、基板度量、冷却、与类似工艺。
系统控制器302控制工具300的操作，此是通过下述方式实现：使用直接控制处理腔室314A、314B、314C、与314D，或替代地，控制与处理腔室314A、314B、314C、与314D及工具300相联的计算机(或控制器)。在操作中，系统控制器302实现来自各别腔室与系统的数据收集和反馈，以使工具300的效能优化。该系统控制器302大体上包括中央处理单元(CPU)330、存储器334、及支持电路332。CPU 330可以是任何形式的可用在工业设施中的通用计算机处理器。该支持电路332以习知方式耦接CPU 330且可包括高速缓冲存储器、时钟电路、输入/输出子系统、电源、与类似物。软件程序(诸如上文所述的处理方法)可存储在存储器334中，且当由CPU 330执行该软件程序时，会将CPU 330转变成专用计算机(系统控制器302)。该软件程序也可由位在工具300的远程的第二控制器(图中未图示)存储和/或执行。
在一些实施方式中，集成工具300中方法100的典型工艺流程可包括将基板200从FOUP传送至工厂接口机器人、至装载锁定腔室、至脱气腔室、至预清洁腔室、至钨衬垫层沉积腔室(诸如CVD或PEALD腔室)、至钨填充层沉积腔室(诸如CVD或ALD腔室)、至冷却腔室、至装载锁定腔室、至工厂接口、至FOUP。
在一些实施方式中，集成工具300中方法100的典型工艺流程可包括将基板200从FOUP传送至工厂接口机器人、至装载锁定腔室、至预清洁腔室、至钨衬垫层沉积腔室(诸如CVD或PEALD腔室)、至钨填充层沉积腔室(诸如CVD或ALD腔室)、至装载锁定腔室、至工厂接口、至FOUP。
在一些实施方式中，集成工具300中方法100的典型工艺流程可包括将基板200从FOUP传送至工厂接口机器人、至装载锁定腔室、至钨衬垫层沉积腔室(诸如CVD或PEALD腔室)、至钨填充层沉积腔室(诸如CVD或ALD腔室)、至装载锁定腔室、至工厂接口、至FOUP。在一些实施方式中，该装载锁定可用作为冷却腔室。在一些实施方式中，该钨衬垫层沉积腔室也可执行预清洁工艺。在一些实施方式中，该钨衬垫沉积腔室也可用于沉积额外的适合的互连件层，该互连件层诸如为使用四(二甲胺基)钛(TDMAT)的金属氧化物化学气相沉积(MOCVD)氮化钛(TiN)或是使用四氯化钛(TiCl4)的原子层沉积(ALD)TiN、或氮化硅钛(TiSiN)、或氮化铝钛(TiAlN)、或氯化钛(TiC)、或氯化铝钛(TiAlC)、或使用TiCl4的CVDTiN、或TiSiN、或TiAlN、或TiC、或TiAlC、ALD氮化钽(TaN)或硅化钽(TaSi)、或氮化硅钽(TaSiN)。
尽管前述内容涉及本公开内容的实施方式，但可设计其他与进一步的实施方式而不背离本公开内容的基本范围。

Claims (14)

1.一种处理基板的方法，包括以下步骤：
在第一基板处理腔室内将基板暴露至等离子体以沉积钨衬垫层，所述等离子体是由第一气体形成，所述第一气体包括金属有机钨前驱物气体或无氟卤化钨前驱物，其中所述钨衬垫层沉积在介电层顶上且于特征内，所述特征形成在基板的所述介电层的第一表面中；
将所述基板传送到第二基板处理腔室而不将所述基板暴露至大气；
将所述基板暴露至第二气体以在所述钨衬垫层顶上沉积钨填充层，所述第二气体包括氟化钨前驱物；和
在沉积所述钨衬垫层前，在200摄氏度至400摄氏度的温度将所述基板暴露至六氟化钨(WF6)气体，或是在沉积所述钨衬垫层前，在300摄氏度至500摄氏度的温度将所述基板暴露至氢(H2)气，
其中在沉积所述钨填充层之前，将钨成核层沉积在所述钨衬垫层顶上。
2.如权利要求1所述的方法，其中所述钨衬垫层具有10埃至50埃的厚度。
3.如权利要求1所述的方法，其中所述第一气体进一步包括含氢气体。
4.如权利要求3所述的方法，其中所述含氢气体是氢(H2)或氨(NH3)。
5.如权利要求1所述的方法，其中所述第一气体进一步包括载气。
6.如权利要求5所述的方法，其中所述载气是氩、氦、或氮。
7.如权利要求1至6中任一项所述的方法，其中所述金属有机钨前驱物气体是W(CO)6、CpW(CO)2NO、EtCpW(CO)2NO、Cp*W(CO)3NO、Cp2WH2、C4H9CNW(CO)5、(C5H11CN)W(CO)5、W(C3H5)4、W(C3H4CH3)4、W(C4H6)3、W(C4H6)2(CO)2、或W(C4H6)(CO)4。
8.如权利要求1至6中任一项所述的方法，其中所述第一基板处理腔室处于0.5托至40托的压力。
9.如权利要求1至6中任一项所述的方法，其中所述氟化钨前驱物是六氟化钨(WF6)。
10.如权利要求1至6中任一项所述的方法，其中所述无氟卤化钨前驱物是五氯化钨(WCl5)或六氯化钨(WCl6)。
11.如权利要求1至6中任一项所述的方法，其中所述第二气体进一步包括含氢气体。
12.如权利要求11所述的方法，其中所述含氢气体是氢(H2)或氨(NH3)。
13.如权利要求1所述的方法，进一步包括以下步骤：将所述基板暴露至所述六氟化钨(WF6)气体或氢(H2)气达0.5秒至600秒。
14.一种计算机可读介质，所述计算机可读介质具有存储于所述计算机可读介质上的指令，当执行所述指令时，引发处理腔室执行一种处理基板的方法，所述方法是如权利要求1至6中的任一项所述的方法。
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