TWI743007B - Semiconductor structure and manufacuring method thereof - Google Patents

Abstract

A semiconductor structure including a trunk portion and a branch portion. The trunk portion extends in a first direction. The branch portion is connected to the trunk portion. The branch portion includes a handle portion and a two-pronged portion. The handle portion is connected to the trunk portion and extends in a second direction. The second direction intersects the first direction. The two-pronged portion is connected to the handle portion. A line width of the handle portion is greater than a line width of the two-pronged portion.

Description

Semiconductor structure and manufacturing method thereof

The present invention relates to a semiconductor structure and a manufacturing method thereof, and more particularly to a semiconductor structure and a manufacturing method thereof capable of preventing disconnection.

At present, some semiconductor devices (such as flash memory) have a rail pattern and an array pattern connected to the rail pattern. The array pattern can be double-patterned by self-alignment ( The self-alignment double patterning (SADP) process is defined, and the rail pattern can be defined by another patterned photoresist layer.

However, in the process of using the patterned mask layer and the patterned photoresist layer as the mask to define the derailment strip pattern and the array pattern, because the patterned photoresist layer is located in the track area and covers the pattern in the track area The etching rate of the patterned mask layer in the array area that is adjacent to the rail area is relatively fast in the etching process, so sub-trenches are often formed in this portion, and then The patterned mask layer is damaged or broken. As a result, the semiconductor structure formed by the patterned mask layer and the patterned photoresist layer is prone to damage or disconnection, thereby reducing the yield and reliability of the semiconductor device.

The present invention provides a semiconductor structure and a manufacturing method thereof, which can effectively prevent damage or disconnection of the semiconductor structure.

The present invention provides a semiconductor structure including a main part and a branch part. The trunk section extends in the first direction. The branch is connected to the main trunk. The branch includes a handle and a double fork. The handle is connected to the trunk and extends in the second direction. The second direction intersects the first direction. The double fork is connected to the handle. The line width of the handle is greater than the line width of the double fork.

The present invention provides a method for manufacturing a semiconductor structure, which includes the following steps. Provide material layer. A first mask layer is formed on the material layer. A plurality of core patterns are formed on the first mask layer. Each core pattern includes a first core and a second core. The second core is connected to the first core. The line width of the first core is greater than the line width of the second core. A spacer material layer is conformally formed on the core pattern. An etch-back process is performed on the spacer material layer to expose the top surface of the core pattern and the top surface of the first mask layer. After performing the above-mentioned etch-back process, the part of the spacer material layer located on the two ends of the core pattern is removed, and the two ends of the core pattern are exposed, and a plurality of spacer structures are formed. Each spacer structure includes a merged spacer and a non-merged spacer. The merging gap wall is located between two adjacent first cores. The non-merging spacer is located between two adjacent second cores and connected to the merged spacer. The line width of the merged spacer is larger than the line width of the non-merged spacer. Remove the core pattern. A first patterned mask layer is formed. The first patterned mask layer covers a part of the merged spacer and exposes another part of the merged spacer and the non-merged spacer. Using the first patterned mask layer and the spacer structure as a mask, the first mask layer is patterned into a second patterned mask layer.

Based on the foregoing, in the semiconductor structure proposed by the present invention, the branch portion is connected to the main portion through the handle portion, and the line width of the handle portion is larger than the line width of the double fork portion. Therefore, through the above-mentioned pattern design of the semiconductor structure, the semiconductor structure can be effectively prevented from being damaged or disconnected due to the sub-groove phenomenon at the position of the handle. In addition, in the manufacturing method of the semiconductor structure proposed in the present invention, the first patterned mask layer covers a part of the merged spacer and exposes another part of the merged spacer and the non-merged spacer. Since the line width of the merged spacer is larger than the line width of the non-merged spacer (that is, the merged spacer may have a larger line width), the first patterned mask layer and the spacer structure are used as the mask, and the During the patterning of the first mask layer into the second patterned mask layer, the second patterned mask layer can be effectively prevented from being damaged or disconnected due to the sub-groove phenomenon. In this way, in the subsequent process of transferring the pattern of the second patterned mask layer to the material layer to be patterned to form the semiconductor structure, the semiconductor structure can be effectively prevented from being damaged or disconnected.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

1A to FIG. 1I are perspective views of a manufacturing process of a semiconductor structure according to an embodiment of the invention. FIG. 2 is a top view of the spacer structure 108a in FIG. 1D. FIG. 3 is a top view of the patterned mask layer 104a in FIG. 1F. FIG. 4 is a top view of the semiconductor structure 100a in FIG. 1I.

Please refer to FIG. 1A, a material layer 100 is provided. The material layer 100 can be used to form a predetermined semiconductor structure. That is, the material layer 100 can be patterned to have a predetermined semiconductor structure (for example, the semiconductor structure 100a in FIG. 1I) in a subsequent process. In this embodiment, when the predetermined semiconductor structure is an active area, the material layer 100 may be a semiconductor substrate (for example, a silicon substrate), but the invention is not limited to this. In other embodiments, when the predetermined semiconductor structure is a wire, the material layer 100 may be a conductive layer (for example, a metal layer or a doped polysilicon layer, etc.).

Next, a mask layer 102 may be formed on the material layer 100. The material of the mask layer 102 is, for example, oxide (eg, silicon oxide), but the invention is not limited to this. The method of forming the mask layer 102 is, for example, a chemical vapor deposition method.

Then, a mask layer 104 may be formed on the mask layer 102. The material of the mask layer 104 is, for example, polysilicon, and the present invention is not limited thereto. As long as the material of the mask layer 104 and the material of the mask layer 102 have different etching rates in the same etching process, it belongs to the scope of the present invention. The method of forming the mask layer 104 is, for example, a chemical vapor deposition method.

Next, a plurality of core patterns 106 may be formed on the mask layer 104. In some embodiments, a trim process may be performed on the core pattern 106 to further reduce the size of the core pattern 106. The trimming process is, for example, a dry etching process. Each core pattern 106 includes a core 106a and a core 106b. The core 106b is connected to the core 106a. The line width LW1 of the core 106a is greater than the line width LW2 of the core 106b. There may be an opening OP1 between two adjacent cores 106a. There may be an opening OP2 between two adjacent cores 106b. The opening OP1 can be connected to the opening OP2. The width W1 of the opening OP1 may be smaller than the width W2 of the opening OP2.

In addition, the core pattern 106 may have a single-layer structure or a multi-layer structure. The material of the core pattern 106 may be carbon, silicon oxynitride (SiON), bottom anti-reflective coating (BARC), or a combination thereof. In this embodiment, the core pattern 106 is an example of a single-layer structure made of carbon, but the present invention is not limited to this. The core pattern 106 can be formed by a spin coating process, a deposition process, a lithography process, an etching process, or a combination thereof.

Referring to FIG. 1B, a spacer material layer 108 may be formed conformally on the core pattern 106. The material of the spacer material layer 108 is, for example, oxide (eg, silicon oxide). The formation method of the spacer material layer 108 is, for example, a chemical vapor deposition method.

In addition, the width W1 of the opening OP1 may be greater than one time of the thickness T1 of the spacer material layer 108 and less than or equal to twice the thickness T1 of the spacer material layer 108. Thereby, the adjacent parts of the spacer material layer 108 located on the sidewall of the opening OP1 can be merged together. In some embodiments, the spacer material layer 108 may completely fill the opening OP1. In addition, the width W2 of the opening OP2 may be greater than twice the thickness T1 of the spacer material layer 108. On the other hand, the spacer material layer 108 does not completely fill the opening OP2.

1C, an etch-back process is performed on the spacer material layer 108, and the top surface of the core pattern 106 and the top surface of the mask layer 104 are exposed. The etch-back process is, for example, a dry etching process (eg, a reactive ion etching (RIE) process).

1D and FIG. 2, after performing the above-mentioned etch-back process, the part of the spacer material layer 108 located on the two ends of the core pattern 106 is removed, and the two ends of the core pattern 106 are exposed, and a plurality of The spacer structure 108a. In this way, a plurality of spacer structures 108 a can be formed on the mask layer 104. Each spacer structure 108a includes a merged spacer S1 and a non-merged spacer S2. In this embodiment, the definitions of "merging spacer S1" and "non-merging spacer S2" are as follows. As shown in FIG. 1B, in the gap filling process for forming the spacer structure 108a, when the width W1 of the opening OP1 is less than or equal to twice the thickness T1 of the spacer material layer 108, the spacer material layer The adjacent parts of 108 located on the sidewall of the opening OP1 can be merged together to form a "merging part". In the spacer structure 108a, the part formed by the above-mentioned "merging part" is defined as "merging spacer S1". In addition, the part not formed by the above-mentioned "merging part" is defined as "non-merging spacer S2". The merging spacer S1 is located between two adjacent cores 106a. The non-merged spacer S2 is located between two adjacent cores 106b and is connected to the merged spacer S1. The line width LW3 of the merged spacer S1 is greater than the line width LW4 of the non-merged spacer S2. For example, the line width LW3 of the merging spacer S1 may be greater than one time of the line width LW4 of the non-merging spacer S2 and less than or equal to twice the line width LW4 of the non-merging spacer S2. The top view shape of the non-merging spacer S2 is, for example, a U shape.

In addition, the method for removing the portions of the spacer material layer 108 located on the two ends of the core pattern 106 may include the following steps, but the present invention is not limited thereto. A patterned photoresist layer (not shown) is formed on the spacer material layer 108, wherein the patterned photoresist layer exposes the part of the spacer material layer 108 located on the two ends of the core pattern 106. Then, using the patterned photoresist layer as a mask, an etching process (eg, a dry etching process) is performed on the spacer material layer 108, and the parts of the spacer material layer 108 located on the two ends of the core pattern 106 are removed, The spacer structure 108a is formed. In addition, the patterned photoresist layer can be removed by dry stripping or wet stripping.

Referring to FIG. 1E, the core pattern 106 is removed. The method of removing the core pattern 106 is, for example, an ashing method, a dry etching method, or a wet etching method. For example, when the material of the core pattern 106 is carbon, the core pattern 106 can be removed by an ashing method.

Referring to FIG. 1F, a patterned mask layer 110 is formed. The patterned mask layer 110 covers a part of the merging spacer S1, and exposes another part of the merging spacer S1 and the non-merging spacer S2. The patterned mask layer 110 may extend in the first direction D1. The merging spacer S1 may extend in the second direction D2. The second direction D2 may intersect the first direction D1. For example, the first direction D1 may be perpendicular to the second direction D2, but the invention is not limited to this. The patterned mask layer 110 may be a single-layer structure or a multi-layer structure. The material of the patterned mask layer 110 may be spin-on-carbon (SOC), silicon-containing hard-mask bottom anti-reflection coating (SHB) , Bottom anti-reflective coating (BARC), photoresist material or a combination thereof. The patterned mask layer 110 can be formed by a spin coating process, a deposition process, a lithography process, an etching process, or a combination thereof. In this embodiment, the patterned mask layer 110 is an example of a single-layer structure made of spin-coated carbon, but the invention is not limited to this.

1G, using the patterned mask layer 110 and the spacer structure 108a as a mask, the mask layer 104 is patterned into a patterned mask layer 104a. The method of patterning the mask layer 104 into a patterned mask layer 104a is, for example, using the patterned mask layer 110 and the spacer structure 108a as a mask, and performing a dry etching process on the mask layer 104 (eg, a reactive ion etching process). ). In some embodiments, since the part of the merge spacer S1 that is adjacent to the patterned mask layer 110 has a faster etching rate during the etching process, it may be that the merge spacer S1 is adjacent to the patterned mask layer 110. A sub-trench ST is formed in the part. However, even if the auxiliary trench ST is formed in the merged spacer S1, since the line width LW3 of the merged spacer S1 is larger than the line width LW4 of the non-merged spacer S2 (that is, the merged spacer S1 may have a larger line width) Therefore, in the process of patterning the mask layer 104 into the patterned mask layer 104a by using the patterned mask layer 110 and the spacer structure 108a as a mask, the spacer structure 108a can be prevented from breaking, thereby effectively The patterned mask layer 104a is prevented from being damaged or disconnected due to the sub-groove phenomenon at the position of the handle P21. In this way, in the subsequent process of transferring the pattern of the patterned mask layer 104a to the material layer 100 to be patterned to form the semiconductor structure 100a (FIG. 1I), the semiconductor structure 100a can be effectively prevented from being damaged or disconnected. .

In addition, as shown in FIG. 1F, the patterned mask layer 110 covers a part of the merging spacer S1, and exposes another part of the merging spacer S1 and the non-merging spacer S2. Therefore, as shown in FIG. 1G, in the process of patterning the mask layer 104 by the dry etching process, the height of the merged spacer S1 covered by the patterned mask layer 110 can be higher than that of the unpatterned mask. The height of the merged spacer S1 covered by the layer 110 and the height of the non-merged spacer S2.

In some embodiments, in the process of patterning the mask layer 104 by a dry etching process, the patterned mask layer 110 may be removed at the same time, but the invention is not limited to this. In other embodiments, the patterned mask layer 110 may be removed by an additional process (for example, an etching process, etc.).

1G and FIG. 3, the patterned mask layer 104a may include a trunk portion P1 and a branch portion P2. The trunk portion P1 may extend in the first direction D1. The branch part P2 is connected to the trunk part P1. The top view shape of the branch portion P2 is, for example, a bifurcated fork shape. The branch portion P2 may include a handle portion P21 and a double fork portion P22. The handle P21 is connected to the trunk P1 and can extend in the second direction D2. The double fork P22 is connected to the handle P21. That is, one end of the handle P21 can be connected to the trunk P1. The other end of the handle P21 can be connected to the double fork P22. The top view shape of the double fork portion P22 is, for example, a U shape. The line width LW5 of the handle P21 may be greater than the line width LW6 of the double fork P22. For example, the line width LW5 of the handle P21 may be greater than one time of the line width LW6 of the double-forked part P22 and less than or equal to twice the line width LW6 of the double-forked part P22.

1H and FIG. 1I, the pattern of the patterned mask layer 104a can be transferred to the material layer 100 to form the semiconductor structure 100a. For example, the method of transferring the pattern of the patterned mask layer 104a to the material layer 100 may include the following steps, but the present invention is not limited thereto. First, as shown in FIG. 1H, the pattern of the patterned mask layer 104a can be transferred to the mask layer 102 to form the patterned mask layer 102a. The method for forming the patterned mask layer 102a is, for example, using the patterned mask layer 104a as a mask, and performing a dry etching process on the mask layer 102. In addition, in the process of patterning the mask layer 102 by the dry etching process, the spacer structure 108a can be removed at the same time, but the present invention is not limited to this. In other embodiments, the spacer structure 108a can be removed by an additional etching process. In addition, in the process of patterning the mask layer 102 by a dry etching process, part of the patterned mask layer 104a may be removed, so that the height of the patterned mask layer 104a is reduced.

Next, referring to FIG. 1I, the pattern of the patterned mask layer 102a can be transferred to the material layer 100 to form a semiconductor structure 100a. For example, the patterned mask layer 104a and the patterned mask layer 102a can be used as a mask to perform a dry etching process on the material layer 100 to form the semiconductor structure 100a. In addition, in the process of patterning the material layer 100 by the dry etching process, the patterned mask layer 104a can be removed at the same time, but the present invention is not limited to this. In other embodiments, the patterned mask layer 104a can be removed by an additional etching process. In addition, after the semiconductor structure 100a is formed, it can be determined to keep or remove the patterned mask layer 102a according to requirements.

In the above manufacturing method of the semiconductor structure 100a, although two mask layers (ie, the mask layer 102 and the mask layer 104) are used to pattern the material layer 100, the present invention is not limited to this. In other embodiments, a single mask layer or more than three mask layers may be used to pattern the material layer 100.

Based on the foregoing embodiment, it can be seen that in the manufacturing method of the semiconductor structure 100a, the patterned mask layer 110 covers a part of the merged spacer S1, and exposes another part of the merged spacer S1 and the non-merged spacer S2. Since the line width LW3 of the merged spacer S1 is greater than the line width LW4 of the non-merged spacer S2 (that is, the merged spacer S1 may have a larger line width), the patterned mask layer 110 and the spacer structure 108a are used As a mask, the process of patterning the mask layer 104 into the patterned mask layer 104a can effectively prevent the patterned mask layer 104a from being damaged or disconnected due to the sub-groove phenomenon at the position of the handle P21. In this way, in the subsequent process of transferring the pattern of the patterned mask layer 104a to the material layer 100 to be patterned to form the semiconductor structure 100a, the semiconductor structure 100a can be effectively prevented from being damaged or disconnected.

Hereinafter, the semiconductor structure 100a of the above-mentioned embodiment will be described with reference to FIGS. 1I and 4. In addition, although the method for forming the semiconductor structure 100a is described by taking the above-mentioned method as an example, the present invention is not limited thereto.

Referring to FIG. 1I and FIG. 4, the semiconductor structure 100a includes a main portion P3 and a branch portion P4. In some embodiments, the semiconductor structure 100a may be an active area of a semiconductor substrate, such as an active area of a flash memory, but the invention is not limited thereto. For example, the trunk portion P3 may be located in the track area R1, and the branch portion P4 may be located in the array area R2. The rail area R1 may correspond to the area where the patterned mask layer 110 in FIG. 1F is located. In other embodiments, the semiconductor structure 100a may be other types of semiconductor structures, such as wires.

The trunk portion P3 extends in the first direction D1. The branch part P4 is connected to the trunk part P3. As shown in the above embodiment, the semiconductor structure 100a can use a self-aligned double patterning (SADP) process to define the shape of the branch portion P4. The top view shape of the branch portion P4 is, for example, a bifurcated fork shape. The branch P4 includes a handle P41 and a double fork P42. The handle P41 is connected to the trunk P3 and extends in the second direction D2. The second direction D2 intersects the first direction D1. For example, the first direction D1 may be perpendicular to the second direction D2, but the invention is not limited to this. The double fork P42 is connected to the handle P41. That is, one end of the handle P41 can be connected to the trunk P3. The other end of the handle P41 can be connected to the double fork P42. The top view shape of the double fork portion P42 is, for example, a U shape. The line width LW7 of the handle P41 is greater than the line width LW8 of the double-forked part P42. For example, the line width LW7 of the handle P41 may be greater than one time of the line width LW8 of the double-forked part P42 and less than or equal to twice the line width LW8 of the double-forked part P42.

In this embodiment, although the semiconductor structure 100a has a branch portion P4 on a single side of the trunk portion P3 as an example, the present invention is not limited to this. In some embodiments, the semiconductor structure 100a may have branch portions P4 on both sides of the trunk portion P3.

Based on the above embodiment, in the semiconductor structure 100a, the branch portion P4 is connected to the trunk portion P3 through the handle P41, and the line width LW7 of the handle P41 is greater than the line width LW8 of the double fork portion P42. Therefore, through the above-mentioned pattern design of the semiconductor structure 100a, it is possible to effectively prevent the semiconductor structure 100a from being damaged or disconnected due to the sub-groove phenomenon at the position of the handle P41.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100: Material layer 100a: semiconductor structure 102, 104: mask layer 102a, 104a, 110: patterned mask layer 106: core pattern 106a, 106b: core 108: spacer material layer 108a: Spacer structure D1: First direction D2: second direction LW1~LW8: line width OP1, OP2: opening P1, P3: main cadre P2, P4: branch P21, P41: handle P22, P42: Double fork R1: Rail area R2: Array area S1: Merge the interstitial wall S2: non-merging interstitial wall T1: thickness W1, W2: width

1A to FIG. 1I are perspective views of a manufacturing process of a semiconductor structure according to an embodiment of the invention. FIG. 2 is a top view of the spacer structure 108a in FIG. 1D. FIG. 3 is a top view of the patterned mask layer 104a in FIG. 1F. FIG. 4 is a top view of the semiconductor structure 100a in FIG. 1I.

100: Material layer

100a: semiconductor structure

102a: Patterned mask layer

D1: First direction

D2: second direction

LW7, LW8: line width

P3: Main cadre

P4: Branch

P41: handle

P42: Double fork

R1: Rail area

R2: Array area

Claims (14)

A semiconductor structure including: The main part, which extends in the first direction; and The branch part is connected to the trunk part, and the branch part includes: A handle connected to the trunk and extending in a second direction, wherein the second direction intersects the first direction; and The double-forked part is connected to the handle, wherein the line width of the handle is greater than the line width of the double-forked part. The semiconductor structure according to claim 1, wherein the top view shape of the branch portion includes a bifurcated fork shape. The semiconductor structure according to claim 1, wherein the top view shape of the double prongs includes a U shape. The semiconductor structure according to claim 1, wherein the trunk portion is in a rail area, and the branch portion is in an array area. The semiconductor structure according to claim 1, wherein the line width of the shank portion is greater than one time of the line width of the double fork portion and less than or equal to twice the line width of the double fork portion. The semiconductor structure according to claim 1, wherein the first direction is perpendicular to the second direction. A method for manufacturing a semiconductor structure includes: Provide material layer; Forming a first mask layer on the material layer; A plurality of core patterns are formed on the first mask layer, and each of the core patterns includes: The first core; and The second core is connected to the first core, wherein the line width of the first core is greater than the line width of the second core; Forming a spacer material layer conformally on the plurality of core patterns; Performing an etch-back process on the spacer material layer to expose the top surface of the plurality of core patterns and the top surface of the first mask layer; After the etch-back process is performed, the part of the spacer material layer located on the two ends of the core pattern is removed, and the two ends of the core pattern are exposed, and a plurality of spacer structures are formed, Each of the gap wall structures includes: The merged spacer is located between two adjacent first cores; and The non-merged spacer is located between two adjacent second cores and is connected to the merged spacer, wherein the line width of the merged spacer is greater than the line width of the non-merged spacer; Removing a plurality of the core patterns; Forming a first patterned mask layer, wherein the first patterned mask layer covers a part of the merging spacer and exposes another part of the merging spacer and the non-merging spacer; and Using the first patterned mask layer and the spacer structure as a mask, the first mask layer is patterned into a second patterned mask layer. The method of manufacturing a semiconductor structure according to claim 7, wherein the top view shape of the non-merged spacer includes a U shape. The method for manufacturing a semiconductor structure according to claim 7, wherein the line width of the merging spacer is greater than one time of the line width of the non-merging spacer and less than or equal to twice the line width of the non-merging spacer . The method of manufacturing a semiconductor structure according to claim 7, wherein a first opening is provided between two adjacent first cores, and a second opening is provided between adjacent two second cores , The first opening is connected to the second opening, and the width of the first opening is smaller than the width of the second opening. The method for manufacturing a semiconductor structure according to claim 10, wherein adjacent parts of the spacer material layer located on the sidewall of the first opening are merged together, and the spacer material layer is not completely filled The second opening. The method of manufacturing a semiconductor structure according to claim 7, wherein the first patterned mask layer extends in a first direction, and the merging spacer extends in a second direction, wherein the second direction intersects In the first direction. The method for manufacturing a semiconductor structure according to claim 12, wherein the second patterned mask layer includes: The trunk part extends in the first direction; and The branch part is connected to the trunk part, and the branch part includes: A handle connected to the trunk and extending in the second direction; and The double-forked part is connected to the handle, wherein the line width of the handle is greater than the line width of the double-forked part. The manufacturing method of the semiconductor structure as described in claim 7, further including: The pattern of the second patterned mask layer is transferred to the material layer.

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