KR101096230B1 - Method for fabricating capacitor in semiconductor device - Google Patents

Abstract

An object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor device capable of preventing the bottom electrode from being broken and preventing excessive loss of the support layer by the LET process and the loss of the lower electrode. Forming; Stacking a sacrificial layer and a support layer on the etch stop layer; Forming a hard mask pattern on the support layer; Forming a groove by etching the support layer and the sacrificial layer using the hard mask pattern as an etch mask; Removing the hard mask pattern; Increasing the lower line width of the groove; Etching the etch stop layer under the groove to form an open portion; Including the step of removing the damaged layer formed during the formation of the open portion, by performing anisotropic etching in the damage layer removal process to prevent the loss of the support layer, there is also the effect of preventing the loss of the lower electrode, accordingly There is an effect of preventing the breakdown of the lower electrode.

Capacitor, Damage Formation, Etch Rate

Description

METHODS FOR FABRICATING CAPACITOR IN SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly, to a method of manufacturing capacitors in semiconductor devices.

Due to the high integration of semiconductor devices, the area where capacitors are formed is gradually narrowing as the minimum line width decreases and the degree of integration increases. Even if the area where the capacitor is formed is narrowed, the capacitor in the cell must secure the high capacitance required per cell. To this end, a method of manufacturing a cylindrical capacitor that removes the sacrificial layer between the capacitors has been proposed.

1A to 1F are cross-sectional views illustrating a method of manufacturing a cylindrical capacitor according to the prior art.

As shown in FIG. 1A, an insulating oxide film 12 is formed on the substrate 11, and a storage node contact plug 13 connected to the substrate 11 through the insulating oxide film 12 is formed.

Subsequently, an etch stop layer 14 is formed on the entire structure including the storage node contact plugs 13, and the first and second sacrificial layers 15 and 16 are disposed on the etch stop layer 14. The support layer 17 and the third sacrificial layer 18 are laminated.

Subsequently, a photosensitive film pattern 19 is formed on the third sacrificial layer 18.

As shown in FIG. 1B, the third sacrificial layer 18, the support layer 17, the second sacrificial layer 16 and the first sacrificial layer 15 are etched to form a contact hole 20, and a cleaning process. Proceed.

As shown in FIG. 1C, a LET (Light Etch Treatment) process is performed. The LET process is performed by isotropic etching using a plasma using a mixture of CF ₄ and O ₂ gas. Therefore, the damage layer generated during the etching of the contact hole 20 is oxidized, and the critical dimension of the lower portion of the contact hole 20 is increased.

In this case, an undercut may occur between the second sacrificial layer 16 and the third sacrificial layer 18 by partially etching the side surface of the support layer 17.

Subsequently, the cleaning process is performed to remove the oxidized damage layer, thereby reducing the resistance.

As illustrated in FIG. 1D, the etch stop layer 14 is etched to expose the storage node contact plug 13.

Subsequently, the lower electrode conductive film 21 is formed along the step of the entire structure including the contact hole 20.

As shown in FIG. 1E, the lower electrode conductive film 21 (see FIG. 1D) is separated to form the lower electrode 21A.

To form the lower electrode 21A, an etch back may be performed, and the etch back may etch the lower electrode conductive film and the third sacrificial layer on the third sacrificial layer 18 (see FIG. 1D) and contact holes. It is preferable to proceed so that the lower electrode 21A remains only in the region 20.

As shown in FIG. 1F, the first and second sacrificial layers 15 and 16 (see FIG. 1E) are removed to form the cylindrical lower electrode 21A. The first and second sacrificial layers may be removed by dip out.

As described above, the prior art oxidizes the damage layer generated when forming the contact hole 20 through the LET process, and proceeds with the cleaning process to remove the oxidized damage layer, thereby reducing the resistance and at the same time the line width of the lower portion of the contact hole 20. Has the effect of increasing.

However, when the support layer 17 is excessively etched during the LET process, a width difference between the second and third sacrificial layers 16 and 18, that is, undercut is generated. Subsequently, a loss occurs due to physical etching during the etch back process to form the lower electrode, thereby lowering the lower electrode 21A formed at the shoulder of the second sacrificial layer 16 (100, FIG. 1E). See). In addition, the thinned lower electrode 21A is vulnerable to stress, causing a break (200 (see FIG. 1F)) to occur in the deep-out process.

In order to prevent this, when the LET process is omitted, there is a problem in that a resistance reduction effect by removing the damage layer and difficulty in securing a lower line width of the contact hole 20 occur.

The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a method for manufacturing a capacitor of a semiconductor device capable of preventing the lower electrode from breaking.

Another object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor device capable of preventing an excessive loss of a support layer and a loss of a lower electrode.

Capacitor manufacturing method of the present invention for achieving the above object comprises the steps of forming an etch stop film on the substrate; Stacking a sacrificial layer and a support layer on the etch stop layer; Forming a hard mask pattern on the support layer; Forming a groove by etching the support layer and the sacrificial layer using the hard mask pattern as an etch mask; Removing the hard mask pattern; Increasing the lower line width of the groove; Etching the etch stop layer under the groove to form an open portion; And removing the damage layer generated when the open portion is formed.

In particular, the sacrificial layer is a laminated structure of a first sacrificial layer and a second sacrificial layer having a different wet etching rate from the first sacrificial layer.

The method may further include forming a third sacrificial layer on the support layer before forming the hard mask pattern.

In addition, the first to third sacrificial layer is an oxide film, the first sacrificial layer is PSG, the second and third sacrificial layer is characterized in that the TEOS, the support layer is the first to third sacrificial layer And the selectivity is different, the support layer and the etch stop film is characterized in that the nitride film.

The forming of the hard mask pattern may include forming an amorphous carbon layer on the third sacrificial layer; Forming an anti-reflection film on the amorphous carbon layer; Forming a photoresist pattern on the anti-reflection film; And etching the anti-reflection film and the amorphous carbon layer using the photoresist pattern as an etch barrier.

In addition, the etching of the anti-reflection film may use a mixed gas of CF ₄ and O ₂ , and the etching of the amorphous carbon layer may include using a mixed gas of O ₂ and COS.

In the forming of the groove, the third sacrificial layer is etched together when the supporting layer is etched, and the etching of the third sacrificial layer and the supporting layer is a mixture of C ₄ F ₈ , O ₂ , CH ₂ F _2, and Ar. It is characterized by using a gas.

In addition, the step of etching the sacrificial layer, characterized in that using a mixed gas of C ₄ F ₈ , C ₄ F ₆ , O ₂ , COS and Ar.

In addition, the step of removing the hard mask pattern, the dry etching, characterized in that the progress using the mixed gas of CF ₄ , O ₂ and Ar.

In addition, the step of increasing the lower line width of the groove, but proceeds to the cleaning process, the wet etching, and the mixed solution of H ₂ SO ₄ and H ₂ O ₂ or mixed solution of NH ₃ F, HF and H ₂ O It characterized in that to proceed using.

In addition, the step of forming the open, characterized in that using a mixed gas of C ₄ F ₈ , O ₂ , CH ₂ F ₃ And Ar.

In addition, the step of removing the damaged layer, the anisotropic etching proceeds, the step of removing the damaged layer, oxidizing the damaged layer; And removing the oxidized damaged layer, wherein the oxidizing the damaged layer is performed in situ, using plasma using a mixed gas of O ₂ and Ar, and removing the oxidized damaged layer. The step is characterized by proceeding to wet cleaning.

In addition, the removing of the damaged layer may include performing first and second etching; In the cleaning process, the step of removing the damaged layer is carried out to the exciter, and the step of performing the first and second etching is performed in an anisotropic etching chamber to which a bias power is applied, in particular, a poly-etcher ( POLY ECHTER).

The primary etching may be performed using a mixed gas of CF ₄ , Ar, and O ₂ by applying a bias power, and the secondary etching may be performed without applying a bias power, but includes HBr, Cl ₂ , and the like. It is characterized by proceeding using a mixture of SF ₆ , He and O ₂ .

The capacitor manufacturing method of the semiconductor device of the present invention described above has an effect of preventing an loss of the support layer by performing anisotropic etching in a damage layer removing step.

Therefore, there is an effect of preventing the loss of the lower electrode, thereby preventing the breakdown of the lower electrode during the dip out.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

((Example 1))

2A to 2G are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to a first embodiment of the present invention.

As shown in FIG. 2A, an insulating film 32 is formed on the substrate 31. The substrate 31 may be a semiconductor (silicon) substrate on which a DRAM process is performed. In addition, before the insulating film 32 is formed, a predetermined process such as a gate and a bit line is performed on the substrate 31.

The insulating film 32 is for interlayer insulation between the substrate 31 and the upper layer, and is preferably formed of an oxide film. The oxide film is HDP (High Density Plasma) oxide film, BPSG (Boron Phosphorus Silicate Glass) film, PSG (Phosphorus Silicate Glass) film, BSG (Boron Silicate Glass) film, TEOS (Tetra Ethyle Ortho Silicate) film, USG (Un- doped Silicate) film Glass (FSG), Fluorinated Silicate Glass (FSG) film, Carbon Doped Oxide (CDO) film, and Organic Silicate Glass (OSG) film, or any one selected from the group consisting of a laminated film of at least two or more layers can be formed have. Alternatively, the film may be formed by a spin coating method such as a spin on dielectric (SOD) film.

Subsequently, a storage node contact plug 33 connected to the substrate 31 through the insulating layer 32 is formed. The storage node contact plug 33 forms a contact hole through which the insulating layer 32 is etched to expose the substrate 31. The storage node contact plug 33 fills a conductive material in the contact hole and exposes the surface of the insulating layer 32. The target is formed by polishing and etching the conductive material. In this case, for example, the conductive material may be formed of any one selected from the group consisting of a transition metal film, a rare earth metal film, an alloy film thereof, and a silicide film thereof. Also, a polysilicon film doped with impurity ions is formed. In addition, the conductive materials may be formed in a laminated structure in which at least two layers are stacked.

Subsequently, an etch stop layer 34 is formed on the entire structure including the storage node contact plug 33. The etch stop layer 34 serves to stop the loss of the lower layer by forming an etch stop when forming a subsequent contact hole. It is preferable to form, and to form a nitride film.

Subsequently, sacrificial layers 35 and 36 are formed on the etch stop layer 34. The sacrificial layers 35 and 36 are provided to provide contact holes for forming the lower electrode, and are preferably formed of an oxide film. In addition, the sacrificial layers 35 and 36 may be formed in a stacked structure, but may be formed in a stacked structure of the first and second oxide films 35 and 36 having different wet etching rates. In particular, the first oxide layer 35 may be formed of a material having a faster wet etching rate than the second oxide layer 36. For example, the first oxide film 35 is formed of a PSG oxide film, and the second oxide film 36 is formed of a TEOS oxide film. In particular, the first oxide film 35 is preferably formed of a PSG oxide film having a doping concentration of 3% to 7% of phosphorus (P) in the film.

Subsequently, the support layer 37 is formed on the sacrificial layer 36. The support layer 37 is to prevent the lowering of the lower electrode (Leaning) phenomenon during the subsequent dip out, it is preferable to form a material having a wet etching selectivity for the sacrificial layers (35, 36). For example, when the sacrificial layers 35 and 36 are formed of an oxide film, the support layer 37 is preferably formed of a nitride film.

Next, a third oxide film 38 is formed on the support layer 37. The third oxide film 38 may be formed of the same material as the second oxide film 36, that is, a TEOS oxide film.

Subsequently, a mask pattern 39 is formed on the third oxide film 38. The mask pattern 39 may be formed by coating a photoresist layer on the third oxide layer 38 and patterning the contact hole predetermined region to be opened by exposure and development. In addition, a hard mask layer (for example, an amorphous carbon layer) may be formed before forming the photoresist film to secure an insufficient etching margin as the photoresist film, and an antireflection film may be formed on the hard mask layer to prevent reflection during the exposure process of the photoresist film. have. When the hard mask layer is formed of an amorphous carbon layer, a silicon oxynitride layer (SiON) may be further formed between the hard mask layer and the anti-reflection film as an etching mask for etching the amorphous carbon layer.

When the hard mask layer, the silicon oxynitride film and the antireflection film are formed before the photoresist film formation, the antireflection film and the silicon oxynitride film are etched using the patterned photoresist as an etch barrier, and the hard mask layer is etched using the silicon oxynitride film as an etch barrier. In this case, the anti-reflection film and the silicon oxynitride film are etched using a mixed gas of O ₂ and CF ₄ , and when the hard mask layer is an amorphous carbon layer, the anti-reflection film and the silicon oxynitride film are preferably etched using a mixed gas of O ₂ and COS.

As shown in FIG. 2B, the third oxide layer 38, the support layer 37, and the sacrificial layers 35 and 36 are etched using the mask pattern 39 (see FIG. 2A) as an etch barrier to form the grooves 40. . In order to form the grooves 40, the etching process may be performed by dividing the third oxide film 38 and the support layer 37 into the etching process of the sacrificial layers 35 and 36.

First, the third oxide film 38 and the support layer 37 preferably run with a gas in which both the oxide film and the nitride film are etched. For example, etching is performed using a mixed gas of C ₄ F ₈ , O ₂ , CH ₂ F _2, and Ar.

Subsequently, the etching of the sacrificial layers 35 and 36 has a selectivity with respect to the nitride film, and etching is preferably performed using a gas that selectively etches the oxide film. For example, etching is performed using a mixed gas of C ₄ F ₆ , C ₄ F ₈ , O ₂ , COS, and Ar.

Etching is stopped in the etch stop film 34 by etching the sacrificial layers 35 and 36 using an oxide film etching gas having a selectivity with respect to the nitride film. Therefore, the loss of the lower insulating film 32 formed of the oxide film is prevented.

Subsequently, the mask pattern 39 (see FIG. 2A) is removed. Removal of the mask pattern 39 (refer to FIG. 2A) is performed by dry etching, and it is preferable to proceed using a mixed gas of CF ₄ , O _2, and Ar. The removal process of the mask pattern 39 includes a case where the mask pattern 39 is formed in a laminated structure of an amorphous carbon layer, a silicon oxynitride film, an antireflection film, and a photoresist pattern.

As shown in FIG. 2C, the cleaning process is performed. The cleaning process is for removing polymer, etc., generated during the formation of the groove 40, and proceeds to wet cleaning.

In particular, the wet cleaning is preferably carried out under the condition that the wet etching rate of the first oxide layer 35 is faster than that of the second oxide layer 36. For this purpose, a mixed solution of H ₂ SO ₄ and H ₂ O ₂ or Proceed with a mixed solution of NH ₄ F, HF and H ₂ O.

Since the etching of the first oxide film 35 proceeds faster than the second oxide film 36, the lower line width of the groove 40 is increased during the cleaning process, and the lower line width can be controlled by controlling the time and the like during the cleaning process. . In particular, in the present invention, it is preferable to increase the cleaning process time than to proceed with the LET process to compensate for the omission of the LET process. Therefore, a sufficient line width under the contact hole can be ensured even without performing the LET process.

As shown in FIG. 2D, the etch stop layer 34 under the groove 40 (see FIG. 2C) is etched to form an open portion 40A for opening the storage node contact plug 33. The etch stop layer 34 is etched by dry etching, and in the case of a nitride layer, the etch stop layer 34 is etched using a mixed gas of C ₄ F ₈ , O ₂ , CH ₂ F _3, and Ar. After the etching stop layer 34 is etched, the cleaning process may be performed.

The surface of the storage node contact plug 33 exposed in the process of etching the etch stop layer 34 to form the open portion 40A may receive damage, and thus the damage layer (not shown). Since it affects the subsequent formation of the lower electrode, it is necessary to remove the damage layer before proceeding to the subsequent process.

As shown in FIG. 2E, the damage layer is removed through post-treatment. Post-treatment proceeds with anisotropic etching and in situ.

The in situ process proceeds to oxidize the damage layer and to the cleaning process.

First, a damage layer formed on the surface of the storage node contact plug 33 exposed during the etching of the etch stop layer 34 is oxidized. The oxidation process is preferably performed using a plasma using a mixed gas of O ₂ and Ar. In particular, the oxidation process selectively oxidizes only the damage layer using a plasma using a mixed gas of O ₂ and Ar. The oxidized damage layer is then removed. The oxidized damage layer is removed through a cleaning process, and the cleaning process may be performed by wet cleaning.

By selectively removing only the damage layer formed on the surface of the storage node contact plug 33 through an oxidation process and a cleaning process, anisotropic etching is performed as a result.

As described above, the selective removal of the damage layer through the oxidation and cleaning process prevents the loss of the support layer 37, and also undercuts between the second and third oxide films 36 and 37 due to the loss of the support layer 37. -cut) can also be prevented. In addition, by increasing the time during the cleaning process in Figure 2c to secure the line width of the lower portion of the groove (40, see FIG. 2c) it is possible to supplement the problem by eliminating the LET process.

By removing the damage layer, silicide is easily formed in the subsequent formation of the lower electrode, thereby reducing the resistance.

As shown in FIG. 2F, the lower electrode conductive film is formed along the step of the entire structure including the open portion 40A, and the lower electrode 41 is formed by etching back. The lower electrode 41 may be formed of, for example, a titanium nitride film TiN. In addition, the etch back etches the lower electrode conductive film formed on the third oxide film 38 so that the lower electrode 41 is present only in the open portion 40A, and performs sufficient etching so that the lower electrode conductive film does not remain. . In addition, during the etch back process, the third oxide layer 38 may be etched to proceed to the target on which the surface of the support layer 37 is exposed.

Particularly, in the present invention, instead of the LET process having the isotropic etching characteristic in FIG. 2D, the damage layer is removed by anisotropic etching, thereby preventing the loss of the support layer 37 and the undercut, thereby exposing the shoulder portion of the second oxide layer 36. Do not.

Therefore, it is possible to prevent the lower electrode 41 present at the interface between the support layer 37 and the second oxide film 36 from being lost by the etch back or the thickness thereof being reduced due to the loss.

As shown in FIG. 2G, the sacrificial layers 35, 36 (see FIG. 2F) are removed. Since the sacrificial layers 35 and 36 are both oxide films, the sacrificial layers 35 and 36 may be removed by wet etching to remove the oxide films.

In addition, the process proceeds to a dip out using BOE (Buffered Oxide Etchant) or HF. In this case, the etch stop layer 34 prevents the loss of the insulating layer 32 due to the dip-out solution, and the support layer 37 prevents the falling of the lower electrode 41 due to stress. Furthermore, in FIG. 2F, the breakage of the lower electrode 41 due to stress may be prevented by preventing the loss of the lower electrode present at the interface between the support layer 37 and the second oxide layer 36 (see FIG. 2D) during etch back. .

By removing all the sacrificial layers, the cylindrical lower electrode 41 is formed.

In a subsequent process, a dielectric film is formed along a step of the entire structure including the cylindrical lower electrode 41A, and an upper electrode is stacked on the dielectric film to form a cylindrical capacitor.

((Example 2))

3A to 3G are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to a second embodiment of the present invention.

As shown in FIG. 3A, an insulating film 52 is formed on the substrate 51. The substrate 51 may be a semiconductor (silicon) substrate on which a DRAM process is performed. Before the insulating film 52 is formed, a predetermined process such as a gate and a bit line is performed on the substrate 51.

The insulating film 52 is for interlayer insulation between the substrate 51 and the upper layer, and is preferably formed of an oxide film. The oxide film is HDP (High Density Plasma) oxide film, BPSG (Boron Phosphorus Silicate Glass) film, PSG (Phosphorus Silicate Glass) film, BSG (Boron Silicate Glass) film, TEOS (Tetra Ethyle Ortho Silicate) film, USG (Un-doped Silicate) film Glass (FSG), Fluorinated Silicate Glass (FSG) film, Carbon Doped Oxide (CDO) film, and Organic Silicate Glass (OSG) film, or any one selected from the group consisting of a laminated film of at least two or more layers can be formed have. Alternatively, the film may be formed by a spin coating method such as a spin on dielectric (SOD) film.

Subsequently, a storage node contact plug 53 is formed through the insulating layer 52 and connected to the substrate 51. The storage node contact plug 53 etches the insulating film 52 to form a contact hole for exposing the substrate 51, and then fills a conductive material in the contact hole and exposes the surface of the insulating film 52. The target is formed by polishing and etching the conductive material. In this case, for example, the conductive material may be formed of any one selected from the group consisting of a transition metal film, a rare earth metal film, an alloy film thereof, and a silicide film thereof. Also, a polysilicon film doped with impurity ions is formed. In addition, the conductive materials may be formed in a laminated structure in which at least two layers are stacked.

Subsequently, an etch stop layer 54 is formed on the entire structure including the storage node contact plugs 53. The etch stop layer 54 serves as an etch stop to form a subsequent contact hole to prevent loss of the lower layer. The etch stop layer 54 may include a material having a selectivity with respect to the insulating layer 52 and a subsequent sacrificial layer, that is, a material having a selectivity with respect to an oxide film. It is preferable to form, and to form a nitride film.

Subsequently, sacrificial layers 55 and 56 are formed on the etch stop layer 54. The sacrificial layers 55 and 56 are provided to provide contact holes for forming the lower electrode, and are preferably formed of an oxide film. In addition, the sacrificial layers 55 and 56 may be formed in a laminated structure, but may be formed in a laminated structure of the first and second oxide films 55 and 56 having different wet etching rates. In particular, the first oxide film 55 may be formed of a material having a faster wet etching rate than the second oxide film 56. For example, the first oxide film 55 is formed of a PSG oxide film, and the second oxide film 56 is formed of a TEOS oxide film. In particular, the first oxide film 55 is preferably formed of a PSG oxide film having a doping concentration of 3% to 7% in the film.

Subsequently, the support layer 57 is formed on the sacrificial layer 56. The support layer 57 is to prevent the falling of the lower electrode during subsequent dip outs, and is preferably formed of a material having a wet etching selectivity with respect to the sacrificial layers 55 and 56. For example, when the sacrificial layers 55 and 56 are formed of an oxide film, the support layer 57 is preferably formed of a nitride film.

Next, a third oxide film 58 is formed on the support layer 57. The third oxide film 58 may be formed of the same material as the second oxide film 56, that is, a TEOS oxide film.

Subsequently, a mask pattern 59 is formed on the third oxide film 58. The mask pattern 59 may be formed by coating a photoresist layer on the third oxide layer 58 and patterning the contact hole predetermined region to be opened by exposure and development. In addition, a hard mask layer (for example, an amorphous carbon layer) may be formed before forming the photoresist layer to secure an insufficient etching margin as the photoresist layer, and an antireflection layer may be formed on the hard mask layer to prevent reflection during the exposure process of the photoresist layer. have. When the hard mask layer is formed of an amorphous carbon layer, a silicon oxynitride layer (SiON) may be additionally formed between the hard mask layer and the anti-reflection film as an etching mask for etching the amorphous carbon layer.

When the hard mask layer, the silicon oxynitride film and the antireflection film are formed before the photoresist film formation, the antireflection film and the silicon oxynitride film are etched using the patterned photoresist as an etch barrier, and the hard mask layer is etched using the silicon oxynitride film as an etch barrier. In this case, the anti-reflection film and the silicon oxynitride film are etched using a mixed gas of O ₂ and CF ₄ , and when the hard mask layer is an amorphous carbon layer, the anti-reflection film and the silicon oxynitride film are preferably etched using a mixed gas of O ₂ and COS.

As shown in FIG. 3B, the third oxide layer 58, the support layer 57, and the sacrificial layers 55 and 56 are etched using the mask pattern 59 (see FIG. 3A) as an etch barrier to form the grooves 60. . In order to form the grooves 60, the etching process may be performed by dividing the third oxide layer 58 and the support layer 57 into the etching process and the sacrificial layers 55 and 56.

First, the third oxide film 58 and the support layer 57 preferably run with a gas in which both the oxide film and the nitride film are etched. For example, etching is performed using a mixed gas of C ₄ F ₈ , O ₂ , CH ₂ F _2, and Ar.

Subsequently, etching of the sacrificial layers 55 and 56 has a selectivity with respect to the nitride film, and etching is preferably performed using a gas that selectively etches the oxide film. For example, etching is performed using a mixed gas of C ₄ F ₆ , C ₄ F ₈ , O ₂ , COS, and Ar.

Etching is stopped in the etch stop film 54 by etching the sacrificial layers 55 and 56 using an oxide film etching gas having a selectivity with respect to the nitride film. Therefore, the loss of the lower insulating film 52 formed of the oxide film is prevented.

Next, the mask pattern 59 (refer FIG. 3A) is removed. Removal of the mask pattern 59 (refer to FIG. 3A) is performed by dry etching, and it is preferable to proceed using a mixed gas of CF ₄ , O _2, and Ar. The removal process of the mask pattern 59 includes a case where the mask pattern 59 is formed in a laminated structure of an amorphous carbon layer, a silicon oxynitride film, an antireflection film, and a photoresist pattern.

As shown in FIG. 3C, the cleaning process is performed. The cleaning process is for removing polymer, etc., generated during the formation of the grooves 60, and proceeds to wet cleaning.

In particular, the wet cleaning is preferably carried out in a condition that the wet etching rate of the first oxide film 55 is faster than the second oxide film 56, for this purpose, a mixed solution of H ₂ SO ₄ and H ₂ O ₂ or NH ₄ Proceed with a mixed solution of F, HF and H ₂ O.

Since the etching of the first oxide film 55 proceeds faster than the second oxide film 56, the lower line width of the groove 60 is increased during the cleaning process, and the lower line width can be controlled by adjusting the time and the like during the cleaning process. . In particular, in the present invention, it is preferable to increase the cleaning process time than to proceed with the LET process to compensate for the omission of the LET process. Therefore, a sufficient line width under the contact hole can be ensured even without performing the LET process.

As shown in FIG. 3D, the etch stop layer 54 is etched to form an open portion 60A for opening the storage node contact plug 53. The etch stop layer 54 is etched by dry etching and, in the case of a nitride layer, is etched using a mixed gas of C ₄ F ₈ , O ₂ , CH ₂ F ₃ and Ar.

The surface of the storage node contact plug 53 exposed in the process of etching the etch stop layer 54 to form the open portion 60A may receive damage, and the damage layer (not shown) generated by the etch stop layer 54 may be damaged. Since it affects the subsequent formation of the lower electrode, it is necessary to remove the damage layer before proceeding to the subsequent process.

As shown in FIG. 3E, the damage layer is removed through post-treatment. Post-treatment proceeds with anisotropic etching, followed by excitus.

Exitu proceeds to remove the damage layer, surface treatment (roughness mitigation) and cleaning process of the storage node contact plug.

The exciter process is divided into primary etching to remove the damage layer and secondary etching to reduce roughness. First, the primary etching is preferably performed in an anisotropic etching chamber to which a bias power can be applied. For example, the anisotropic etching chamber includes a poly echter. In addition, the primary etching is applied to the bias power in the anisotropic etching chamber, and proceeds using a mixed gas of CF ₄ , Ar, O ₂ .

As described above, anisotropic etching characteristics are increased by applying bias power, and the damage layer formed on the surface of the storage node contact plug 53 is selectively removed using a mixed gas of CF ₄ , Ar, and O ₂ .

Subsequently, the secondary etching proceeds without applying bias power, but proceeds using a mixed gas of HBr, Cl ₂ , SF ₆ , He, and O ₂ to remove the damage layer to relieve roughness of the storage node contact plug 53. Play a role.

Subsequently, the cleaning process is performed to remove the etch byproducts during the primary and secondary etching.

As described above, only the damage layer formed on the surface of the storage node contact plug 53 is selectively removed without loss of the support layer 57 through the primary etching having the anisotropic etching characteristic and the secondary etching for the roughness relief. There is an effect that the resistance is reduced by allowing the silicide to be easily formed during subsequent lower electrode formation.

As shown in FIG. 3F, the lower electrode conductive film is formed along the step of the overall structure including the open portion 60A, and the lower electrode 61 is formed by performing etch back. The lower electrode 61 may be formed of, for example, a titanium nitride film TiN. In addition, the etch back etches the lower electrode conductive film formed on the third oxide film 58 so that the lower electrode 61 exists only in the open portion 60A, and performs sufficient etching so that the lower electrode conductive film does not remain. . In addition, during the etch back process, the third oxide layer 58 may be etched to proceed to the target on which the surface of the support layer 57 is exposed.

In particular, in the present invention, by removing the damage layer through anisotropic etching instead of the LET process having the isotropic etching characteristic in Figure 3d to prevent the loss of the support layer 57 and thereby undercut, the shoulder portion of the second oxide film 56 is exposed Do not.

Therefore, it is possible to prevent the lower electrode 61 present at the interface between the support layer 57 and the second oxide film 56 from being lost by etching back or from reducing the thickness due to the loss.

As shown in FIG. 3G, the sacrificial layers 55, 56 (see FIG. 3F) are removed. Since the sacrificial layers 55 and 56 are both oxide films, the sacrificial layers 55 and 56 may be removed by wet etching to remove the oxide films.

In addition, the process proceeds to a dip out using BOE (Buffered Oxide Etchant) or HF. At this time, the etch stop layer 54 prevents the loss of the insulating layer 52 due to the dip-out solution, and the support layer 57 prevents the falling of the lower electrode 61 due to stress. Furthermore, in FIG. 3F, the breakage of the lower electrode 61 due to stress may be prevented by preventing the loss of the lower electrode present at the interface between the support layer 57 and the second oxide layer 56 (see FIG. 3D) during etch back. .

By removing all the sacrificial layers, the cylindrical lower electrode 61 is formed.

In a subsequent process, a dielectric film is formed along a step of the entire structure including the cylindrical lower electrode 61A, and an upper electrode is stacked on the dielectric film to form a cylindrical type capacitor.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1F are cross-sectional views illustrating a method of manufacturing a cylindrical capacitor according to the prior art;

2A to 2G are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to a first embodiment of the present invention;

3A to 3G are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device in accordance with a second embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31 substrate 32 insulating film

33: storage node contact plug

34: etching stop film 35: first oxide film

36: second oxide film 37: support layer

38: third oxide film 39: mask pattern

40A: open portion 41: lower electrode

Claims (31)

Forming an etch stop layer on the substrate; Stacking a sacrificial layer and a support layer on the etch stop layer; Forming a hard mask pattern on the support layer; Forming a groove by etching the support layer and the sacrificial layer using the hard mask pattern as an etch mask; Removing the hard mask pattern; Increasing the lower line width of the groove; Etching the etch stop layer under the groove to form an open portion; And Performing anisotropic etching to remove the damage layer formed when the open portion is formed. Capacitor manufacturing method of a semiconductor device comprising a. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, The sacrificial layer is a laminate structure of a first sacrificial layer and a second sacrificial layer having a different wet etching rate from the first sacrificial layer. Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1, And forming a third sacrificial layer on the support layer. Claim 4 was abandoned when the registration fee was paid. The method of claim 3, And the first to third sacrificial layers are oxide films. Claim 5 was abandoned upon payment of a set-up fee. 5. The method of claim 4, The first sacrificial layer is PSG, and the second and third sacrificial layers are TEOS. Claim 6 was abandoned when the registration fee was paid. 5. The method of claim 4, The support layer is a capacitor manufacturing method of a semiconductor device, the selectivity is different from the first to third sacrificial layer. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 6, Claim 8 was abandoned when the registration fee was paid. The method of claim 3, Forming the hard mask pattern, Forming an amorphous carbon layer on the third sacrificial layer; Forming an anti-reflection film on the amorphous carbon layer; Forming a photoresist pattern on the anti-reflection film; Etching the anti-reflection film and the amorphous carbon layer using the photoresist pattern as an etch barrier Capacitor manufacturing method of a semiconductor device comprising a. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 8, Etching the anti-reflection film, A method for producing a capacitor of a semiconductor device using a mixed gas of CF ₄ and O ₂ . Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 8, A method for manufacturing a capacitor of a semiconductor device using a mixed gas of O ₂ and COS. Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 7, wherein In the step of forming the groove, The method of manufacturing a capacitor of a semiconductor device which etches the third sacrificial layer together when the supporting layer is etched. Claim 12 was abandoned upon payment of a registration fee. The method of claim 11, In the step of forming the groove, The etching of the third sacrificial layer and the support layer is A method for manufacturing a capacitor of a semiconductor device using a mixed gas of C ₄ F ₈ , O ₂ , CH ₂ F ₂ and Ar. Claim 13 was abandoned upon payment of a registration fee. 5. The method of claim 4, Etching the sacrificial layer, Claim 14 was abandoned when the registration fee was paid. The method of claim 8, Removing the hard mask pattern, A method for manufacturing a capacitor of a semiconductor device that proceeds by dry etching. Claim 15 was abandoned upon payment of a registration fee. The method of claim 14, The dry etching is a capacitor manufacturing method of a semiconductor device that proceeds using a mixed gas of CF ₄ , O ₂ and Ar. Claim 16 was abandoned upon payment of a setup registration fee. The method of claim 1, Increasing the lower line width of the groove, A method for manufacturing a capacitor of a semiconductor device, which proceeds to a cleaning step. Claim 17 has been abandoned due to the setting registration fee. The cleaning process is a capacitor manufacturing method of the semiconductor device to proceed by wet etching. Claim 18 was abandoned upon payment of a set-up fee. The method of claim 17, The wet etching is a capacitor manufacturing method of a semiconductor device to proceed using a mixed solution of H ₂ SO ₄ and H ₂ O ₂ or a mixed solution of NH ₃ F, HF and H ₂ O. Claim 19 was abandoned upon payment of a registration fee. The method of claim 1, Forming the open portion, A method for manufacturing a capacitor of a semiconductor device using a mixed gas of C ₄ F ₈ , O ₂ , CH ₂ F ₃ and Ar. delete Claim 21 has been abandoned due to the setting registration fee. The method of claim 1, Removing the damage layer, Oxidizing the damage layer; And Removing the damaged layer oxidized. Claim 22 is abandoned in setting registration fee. The method of claim 21, Oxidizing the damage layer, A method for manufacturing a capacitor of a semiconductor device that proceeds in situ. Claim 23 was abandoned upon payment of a set-up fee. The method of claim 22, Oxidizing the damage layer, A method for manufacturing a capacitor of a semiconductor device using plasma using a mixed gas of O ₂ and Ar. Claim 24 is abandoned in setting registration fee. Removing the oxidized damage layer, A method for manufacturing a capacitor of a semiconductor device, which proceeds by wet cleaning. Claim 25 is abandoned in setting registration fee. The method of claim 1, Removing the damage layer, Performing first and second etching; And Steps to proceed with cleaning process Capacitor manufacturing method of a semiconductor device comprising a. Claim 26 is abandoned in setting registration fee. The method of claim 25, Removing the damage layer, A capacitor manufacturing method of a semiconductor device which proceeds with excitus. Claim 27 was abandoned upon payment of a registration fee. The method of claim 25, The first and second etching is performed, A method for manufacturing a capacitor of a semiconductor device, which proceeds in an anisotropic etching chamber to which bias power can be applied. Claim 28 has been abandoned due to the set registration fee. The method of claim 27, The first and second etching is performed, A method for manufacturing a capacitor of a semiconductor device proceeding in POLY ECHTER. Claim 29 has been abandoned due to the setting registration fee. The method of claim 28, The primary etching is, A method of manufacturing a capacitor of a semiconductor device, wherein a bias power is applied and the mixture gas of CF ₄ , Ar, and O ₂ is advanced. Claim 30 has been abandoned due to the set registration fee. The method of claim 28, The secondary etching, A capacitor manufacturing method of a semiconductor device that proceeds without applying a bias power. Claim 31 has been abandoned due to the setting registration fee. The method of claim 28, The secondary etching, A method for manufacturing a capacitor of a semiconductor device, which proceeds using a mixed gas of HBr, Cl ₂ , SF ₆ , He, and O ₂ .

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