TW200847341A - Methods for forming a bit line contact - Google Patents

Abstract

A method for forming a bit line contact is provided. The method comprises providing a substrate, and sequentially forming a gate dielectric layer, a gate conductive layer, a gate cap layer and a mask layer on the substrate. A patterned photoresist layer having at least one opening is formed on the mask layer. The mask layer and a portion of the gate cap layer are etched through the opening by using the patterned photoresist layer as a mask. The patterned photoresist layer is removed. Spacers are formed on sidewalls of the mask layer and the gate cap layer. The gate cap layer and the gate conductive layer are removed to form a plurality of gate stack layers by using the mask layer and the spacers as a mask. The spacers are removed to form a plurality of gate structures and a gap having a widened portion thereon between adjacent gate structures. A dielectric layer is formed on the substrate and filled into the gap. The dielectric layer is patterned to form a bit line contact hole. A conductive layer is formed in the bit line contact hole to form a bit line contact.

Description

200847341 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor process, and more particularly to a method for avoiding short-circuiting of bit lines and bit lines [prior art] The development technology of integrated circuits is changing with each passing day, and its development trend is moving toward the function of 'large size reduction and speed acceleration, and the manufacturing technology of dynamic random memory (DRAM) is also the same, but when the features are smaller, For example, if the voltage drops to llOnm, it is easy to cause holes in the ILD due to the poor dielectric filling ability of the interlayer dielectric layer. The problem of short-circuiting between the bit line and the bit line 70 occurs. Knowing the intermediate process profile of the bit line contact forming the memory device, it is said that the problem of short-circuiting between the bit line and the bit line occurs. The memory device is required to be formed in the dream substrate 1 〇Q Semiconductor components, such as capacitors, etc., but here to simplify the drawing, only the flat substrate 100 is shown. The substrate 1 (9) and the memory array region and periphery Peripheral ciixuitregion, for the sake of simplicity of explanation, only the memory array region 1 is described here. "A plurality of gate structures 1 〇 8 are provided above the memory array region 10 for use in making word lines." The gate structure 1 〇 8 includes a dummy conductive layer 150 and a gate upper layer 160, wherein the gate conductive layer i5 〇 includes a polysilicon layer 130, and a metal hydride layer 14 降低 for reducing the resistance value. 108 is formed on the gate dielectric layer 12〇, and a sidewall of the gate is formed on the sidewall of the gate 1〇8. The core is between the adjacent gate junctions

Client's Docket No.: 93079 TT5s Docket No: 0548-A50821-TW/fmal/Claire 5 200847341 has a source/drain region 105 in the substrate 100. The gate dielectric layer 120 is a ruthenium oxide layer formed by a thermal oxidation method; the gate spacer 170 and the gate upper cap layer 160 are formed of nitriding enamel. A dielectric layer 110 is formed over the gate structures 108 and adjacent gate structures 108, such as borophosphsilicate glass (BPSG), which can be formed by chemical vapor deposition (CVD). As an interlayer dielectric layer. However, as the line width is smaller, the aspect ratio (ie, DJW!) of the gap between adjacent gate structures 108 is more and more f, for example, the aspect ratio reaches about 4 to 5, which will result in The dielectric layer 110 has a poor trenching capability resulting in the creation of holes 60 in the dielectric layer 110. A bit line contact window (not shown) is formed in the dielectric layer 110 between the adjacent gate structures 108, and then a conductive material is filled in the bit line contact window to form a bit line. Contact plug (not shown). However, the conductive material filled in is electrically connected to the plugs of other adjacent bit lines by the holes 60. As a result, the bit lines and the bit lines are short-circuited, which seriously affects the reliability of the elements. Therefore, there is a need for a semiconductor manufacturing method that improves the above disadvantages. SUMMARY OF THE INVENTION In view of the above, the object of the present invention is to improve the problem that the bit line and the bit line are short-circuited due to poor filling force of the dielectric layer, and the bit line and bit are avoided by the present invention. The short-circuit method of the element line ensures the reliability of the component. In accordance with the above, the present invention provides a method of fabricating a bit line contact plug comprising: providing a substrate' sequentially forming a gate dielectric layer, a gate

Client's Docket No. :93079 TT's Docket No:0548-A50821-TW/fmal/Claire 6 200847341 A conductive layer, a gate cap layer, and a mask layer on the substrate; forming a patterned photoresist layer on the mask On the screen layer, the patterned photoresist layer has an opening; the patterned photoresist layer is used as a mask, the mask layer and a portion of the gate cap layer are etched through the opening; and the patterned photoresist is removed a layer is formed on the sidewall of the mask layer and the gate cap layer; the mask layer and the spacer layer are used as a mask, and the gate cap upper layer and the gate conductive layer are removed to form a plurality of layers a gate stack; the spacer is removed to form a plurality of gate structures, and a gap having an enlarged/large portion is formed between the adjacent gate structures; and a dielectric layer is formed on the substrate Filling in the gap between the upper and the enlarged portions; patterning the dielectric layer to form a one-dimensional line contact window; and forming a conductive layer in the bit line contact window to form a bit line Contact the plug. The embodiments of the present invention will be described with reference to the drawings, in which like or Zoom out. It is to be noted that the components not shown or described in the drawings may be in a form known to those skilled in the art, and in addition, when a layer is placed on a substrate or another layer, the layer may be directly located. The substrate may be on another layer or may have an interposer therebetween. The following describes the manufacturing method of the bit line contact plug according to the embodiment of the present invention, which can avoid the problem of short circuit between the bit line and the bit line, and is suitable for a memory device, such as a dynamic random access memory. (DRAM). First, please refer to FIG. 2a to provide a substrate 200, such as a stone wafer, and the substrate 200 includes a memory array region and a peripheral circuit region.

Client's Docket No.: 93079 TT's Docket No: 0548-A50821-TW/final/Claire 7 200847341 A simplified description is given here only with memory array area 20. Next, a gate dielectric layer 220, a gate conductive layer 250, a gate cap layer 260, and a mask layer 280 are sequentially formed on the substrate 200 of the memory array region 20. In an embodiment, the gate dielectric layer 220 may be a ruthenium oxide layer formed by thermal oxidation; the gate conductive layer 250 may include a conductive material such as a polysilicon layer 230 and a metal rumination layer 240 for reducing resistance. It can be deposited on the gate dielectric layer 220 by low pressure chemical vapor deposition (LPCVD). The gate cap layer 260 can be a tantalum nitride formed by low pressure chemical vapor deposition. The use of the pole and the insulating layer; the mask layer 280 may include an oxide which may be formed by chemical vapor deposition (CVD). For example, the mask layer 280 may be made of tetraethyl niobate (TEOS). For the yttrium oxide formed by the reactive gas, it is preferred that both the mask layer 280 and the gate cap layer 260 have a high etching selectivity. In other embodiments, an anti-reflective layer, such as a ruthenium oxynitride layer, may be formed between the gate cap layer 260 and the mask layer 280 to increase the process window of the yellow light process. Please refer to section 2b. The first patterned photoresist layer 290 is formed on the mask layer 280 by using a conventional lithography technique, and the first patterned photoresist layer 290 has at least one opening (not shown). Then, the first patterned photoresist layer 290 is used as a mask, and the mask layer 280 and a portion of the gate cap layer 260 are etched through the opening, so that an opening is formed in the mask layer 280 and the gate cap layer 260. Preferably, the gate cap layer 260 is about one-third the thickness removed, leaving about two-thirds the thickness. In one embodiment, the mask layer 280 and portions not covered by the first patterned photoresist layer 290 may be removed by dry etching such as reactive ion etching (RIE) or high density plasma etching. The gate upper cap layer 260.

Client's Docket No.:93079 TT's Docket No:0548-A50821-TW/fmal/Claire 8 200847341 The nightmare picture 2c, using plasma ashing (piaSma ashing) or wet stripping (wet stripping) to remove the first After patterning the photoresist layer 290, a spacer 31 is formed on the sidewalls of the gate cap layer 260 and the cap layer 280. In an embodiment, the spacer 310 material layer may include an oxide, such as an oxidized oxide, which may include a first conformally deposited yttria layer (not exaggerated) to cover the gate cap layer 260 and the mask. Layer 280, followed by etch back the yttrium oxide layer by anisotropic etching, such as dry etch, and the gate cap layer 290 in the opening 190 and

The sidewalls of the mask layer 280 leave a spacer 310 as shown in Figure 2c. Next, please refer to FIG. 2d, with the mask layer 28 〇 and the spacers 31 〇 as the mask, such as the plasma etching or the anti-library fence, the removal of the upper cap layer 260 and the raw : 250 ′ and exposing the gate dielectric layer 22 〇 to form a gate stack 302 composed of a gate conductive layer “ο , a gate cap layer 260 , a mask layer 280 , and a spacer 31 。 . In Fig. 2e, the spacers 31 are removed by wet-spot engraving to form the gate structure 320, and in the gates of the adjacent gate structures 32, the gaps 320a. For example, The dilute: hydrofluoric acid (chime HF'DHF) solution is removed from the yttrium oxide wall 310 to form a gate structure 32 composed of a gate conductive layer 25 〇 and a gate upper 2 2 2 mask layer 280 〇 Since the width of the mask layer 2 and the portion of the gate cap layer 26 在 are small in the width of the closed conductive layer 250, the adjacent gate structure 3 has an upper portion The gap 320a of the enlarged portion. In the gate structure 320, in an embodiment, referring to FIG. 2f, the sidewall of the gate spacer 34 is formed to cover the gate. The sidewall of the pole conductive layer 250.

Client's Docket No::93079 TT5s Docket No:0548-A50821-TW/fmal/Claire 200847341 The gate spacer 340 may include tantalum nitride, which is formed by a chemical vapor deposition method followed by deposition of a tantalum nitride layer. On the gate structure 320 and the gate dielectric layer 220, an anisotropic method is then performed, and the tantalum nitride layer is returned to leave a tantalum nitride layer on the sidewall of the gate structure 320 as a gate. Pole spacer 340. After the gate spacers 340 are formed, the gate structures 320 and the gate spacers 340 can be used as ion implantation masks to perform an ion implantation process to form source/drain regions 350 in the substrate 200. Referring to Fig. 2g, a dielectric layer 400 is formed over the gate structure 320, and a gap 320a having an enlarged portion between the adjacent gate structures 32A is filled. The dielectric layer 400 may include borophosphorus bismuth glass (BPSG) formed by sub-atmospheric chemical vapor deposition (SACVD), and after the BPSG is deposited, a tempering process may be performed to promote the mobility of the BPSG. Preferably, a planarization step is performed after forming the dielectric layer 400, such as by chemical mechanical polishing (CMP), to planarize the dielectric layer 400. It is worth noting that since the upper portion of the gap 320a between the gate structures 320 has an enlarged portion, the aspect ratio thereof is thus reduced, and thus the gap filling force of the dielectric layer 400 can be increased (gap-mi capability). ). In the 2g diagram, the aspect ratio of the gap 320a is d2/W2, and D2/W2 is preferably less than 3. Since the aspect ratio of the gap 320a is lowered, when the dielectric layer 400 is filled in the gap 320a between the gate structures 320, the probability of generating holes in the dielectric layer 400 can be reduced. Referring to FIG. 2h, a second patterned photoresist layer 3 is formed on the dielectric layer 400 to define a bit line contact window, and then a second patterned photoresist layer 380 is used as a mask. The electrical layer 4QQ and the gate dielectric layer 220 thereunder form a bit line contact window 420 between adjacent gate structures 32A. Finally, using plasma ashing or wet

Clienf s Docket No.: 93079 TT’s Docket No: 0548-A50821-TW/fmal/Claire 10 200847341 The second patterned photoresist layer 390 is removed by wet stripping. Next, a conductive layer is filled in the contact window 420 to form a bit line contact plug 440, as shown in Fig. 2i. In one embodiment, a conductive layer material such as tungsten metal may be formed on the dielectric layer 400 by chemical vapor deposition and filled in the bit line contact window 420, preferably formed in a bit line contact. The conductive layer material in the window 420 may further comprise a metal barrier layer, such as titanium, a button, a titanium nitride or a nitride button, and combinations thereof, which are compliantly deposited on the sidewalls and bottom of the bit line contact window 420. Finally, the excess conductive layer material on the dielectric layer 400 can be removed by chemical mechanical polishing (CMP), and the conductive layer material remaining in the bit line contact window 420 constitutes a bit line contact plug. Plug 440. In the above embodiment, since the present invention improves the problem of the excessive aspect ratio of the gap between the conventional gate structures 108, it causes voids in the dielectric layer 110 filled therein. With the concept of the present invention, after the completion of the bit line contact plug 440, the bit line contact plug 440 and other adjacent bit line contact plugs (not shown) are not electrically connected to each other. The occurrence of a short circuit between the bit line and the bit line occurs, so that the reliability of the component can be improved. In addition, it should be noted that the above embodiment is described by using a bit line contact plug of a DRAM as an example. However, the peripheral circuit area of the memory device or other semiconductor device has poor filling ability and the reliability of the component is lowered. The problem can also be solved by applying the concept of the present invention. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached.

Client's Docket No. :93079 TT^s Docket N〇:0548-A50821 -TW/final/Claire 11 200847341 [Simplified Schematic] Figure 1 shows the middle of a bit line contact plug forming a conventional memory device. Process profile view; Figures 2a through 2i illustrate a method of fabricating a bit line contact plug in accordance with an embodiment of the present invention. [Major component symbol description] Prior art 10~ memory array region; 60~ hole; 100~ substrate; 105~ source/drain region; 108~ gate structure; 110~ dielectric layer; 120~ gate dielectric layer; 130~ polycrystalline layer; 140~ metal lithium layer; 150~ gate conductive layer; 160~ gate upper cap layer; 170~ gate spacer. Embodiment 20 to memory array region; 200 to substrate; 220 to gate dielectric layer; 230 to polysilicon layer; 240 to metal layer; 250 to gate conductive layer; 260 to gate upper cap layer; Curtain layer; 290~first patterned photoresist layer; 190~opening; 310~gap; 302~gate stack; 320~gate structure; 320a~gap; 340~gate spacer; 3 50^ Source/> and polar region, 400~dielectric layer; 380~second patterned photoresist layer; 420~bit line contact window; 440~bit line contact plug.

Client’s Docket N〇.:93079 12 TTs Docket No:0548-A50821-TW/final/Claire

Claims (1)

200847341 X. Patent application scope: 1. A method for manufacturing a bit line contact plug, comprising: providing a substrate, sequentially forming a gate dielectric layer, a gate conductive layer, a gate upper cap layer, and a Masking the layer on the substrate; forming a patterned photoresist layer on the mask layer, the patterned photoresist layer having an opening; using the patterned photoresist layer as a mask, etching the mask through the opening a mask layer and a portion of the gate cap layer; f removing the patterned photoresist layer; forming a spacer on the mask layer and sidewalls of the gate cap layer; the mask layer and the spacer layer are Masking, removing the gate cap layer and the gate conductive layer to form a plurality of gate stacks; removing the spacers to form a plurality of gate structures, and forming between the adjacent gate structures a gap having an enlarged portion thereon; forming a dielectric layer on the substrate and filling the gap having the enlarged portion thereon; patterning the dielectric layer to form a one-dimensional line contact window; and forming a conductive Layer in the contact line of the bit line to shape Bit line contact plug. 2. The method of manufacturing a bit line contact plug according to claim 1, wherein the mask layer comprises using an oxide oxide containing tetraethyl phthalate as a reactive gas. 3. The method of manufacturing a bit line contact plug according to claim 1, wherein the gate cap layer comprises tantalum nitride. 4. The method of manufacturing a bit line contact plug according to claim 1, wherein the spacer comprises ruthenium oxide. Clienfs Docket No. :93079 TT^ Docket No:0548-A50821-TW/final/Claire 13 200847341 Method of manufacture, 1;:: 制 峨 峨 : : : : : : : : : : : :: :: The patterned photoresist layer is used as a mask, and the degree of closure is removed in the step of removing the upper layer of the upper layer by the upper cap layer. ', the thickness of the second 77-, leaving about two-thirds of the thickness of the square 6 to the level of the contact line plug as described in the scope of the first paragraph = the cover layer and the gate The sidewall of the upper cap layer is formed by: an upper cover: a layer of spacer material on the mask layer and the pole electrode, and a layer of a gap material layer to form the gap on the sidewall of the mask layer and the free layer wall. Manufacture: The ruthenium cover layer of the bit line contact plug as described in item 1 and the spacer are masks, and the (4) system for removing the gate layer and the secret conductive layer is completed. In the system of the bit line contact plug described in item 7 of the patent scope of the invention, the dry money engraving includes a plasma surname or a reactive ion engraving. 9. The method of applying the bit line contact plug described in the special item (4), wherein the step of removing the spacer is performed using a secret. The method of making a bit line contact plug according to the above item 9, wherein the wet etching is etched with a diluted hydrofluoric acid solution. The method for manufacturing a bit line contact plug according to claim 1, further comprising: forming a gate spacer on a sidewall of the gate conductive layer. 12. Client's Docket No.: 93079 TT5s Docket No: 0548-A50821-TW/fmal/Claire 14 200847341, as claimed in the patent scope, the gate conductive layer including polysilicon Layer or metal telluride layer. 13. The method of manufacturing the avoidance line contact plug of claim 1, wherein the dielectric layer comprises borophosphon glass. 14. The method of fabricating a bit line contact plug according to claim 1, wherein the step of forming the dielectric layer on the substrate is performed by chemical vapor deposition. 15. The method of fabricating a bit line contact plug of claim 1, wherein after forming the dielectric layer on the substrate, further comprising performing a chemical mechanical polishing step. 16. The method of fabricating a bit line contact plug according to claim 1, wherein the step of forming the conductive layer in the bit line contact window is performed by chemical vapor deposition. 17. The method of fabricating a bit line contact plug according to claim 1, wherein the conductive layer comprises a metal barrier layer. 18. The method of fabricating a bit line contact plug according to claim 11, wherein the gate spacer comprises tantalum nitride. Clienf s Docket No.:93079 15 TT’s Docket N〇:0548-A50821 -TW/final/Claire