JP3942814B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device manufacturing technique, and more particularly, to a semiconductor device having a DRAM type memory element and a manufacturing method thereof.
[0002]
[Prior art]
A DRAM is a semiconductor memory device that can be configured with one transistor and one capacitor. Various structures and manufacturing methods for manufacturing a semiconductor memory device with higher density and higher integration have been studied. In particular, from the viewpoint of manufacturing cost reduction, how to achieve the intended purpose while reducing the number of manufacturing steps is important for further miniaturization of semiconductor devices. Although various studies are underway to reduce the number of manufacturing processes, one of them is a technology that reduces the total number of processes by integrally forming the storage electrode and the contact plug connected to the storage electrode. Has been.
[0003]
Hereinafter, a conventional method for manufacturing a semiconductor device in which a storage electrode and a contact plug are integrally formed will be described with reference to FIGS. 20 to 22 are process cross-sectional views illustrating a conventional method for manufacturing a semiconductor device, and FIG. 23 is a plan view illustrating the conventional method for manufacturing a semiconductor device.
[0004]
First, a memory cell transistor having a gate electrode 102 and source / drain diffusion layers 104 and 106 is formed on a silicon substrate 100 in the same manner as in a normal MOS transistor manufacturing method.
[0005]
Next, a bit line 114 electrically connected to the source / drain diffusion layer 104 through the plug 108 is formed on the interlayer insulating film 112 covering the memory cell transistor. Since the bit line 114 does not appear in the cross section shown in the drawing, the bit line 114 is indicated by a dotted line.
[0006]
Next, an interlayer insulating film 116 is formed on the interlayer insulating film 112 on which the bit line 114 is formed (FIG. 20A).
[0007]
Next, an etching stopper film 118 made of, for example, a silicon nitride film, an interlayer insulating film 120 made of, for example, a silicon oxide film, and a hard mask 122 made of, for example, an amorphous silicon film are formed on the interlayer insulating film 116 by, eg, CVD. (FIG. 20B).
[0008]
Here, the etching stopper film 118 is patterned so that an opening is formed on the plug 110 before the interlayer insulating film 120 is deposited. The hard mask 122 defines a region where the storage electrode is formed, and is patterned so that an opening is formed in a region where the storage electrode is to be formed. The opening of the hard mask 122 is formed so as to surround the opening of the etching stopper film 118 as shown in FIG.
[0009]
Next, using the hard mask 122 as a mask and the etching stopper film 118 as a stopper, the interlayer insulating films 120, 116, and 112 are sequentially anisotropically etched to pass through the interlayer insulating films 120, 116, and 112 and reach the plug 110. Is formed (FIG. 21A).
[0010]
Next, after depositing a conductive film made of, for example, a Ru film by, for example, a CVD method, the conductive film and the hard mask 122 are removed flatly until the surface of the interlayer insulating film 120 is exposed. A cylindrical storage electrode 126 made of a film and connected to the plug 110 is formed (FIG. 22B).
[0011]
Next, after forming a photoresist film (not shown) that covers the peripheral circuit region and exposes the memory cell region by a normal lithography technique, the interlayer insulating film is formed using the photoresist film as a mask and the etching stopper film 118 as a stopper. 124 isotropically etched to selectively remove the interlayer insulating film 124 in the memory cell region. Thus, the inner surface and the outer surface of the storage electrode 126 are exposed (FIG. 22A).
[0012]
Next, on the entire surface, for example, by the CVD method, for example, Ta₂O_FiveA dielectric film made of a BST film or the like is deposited, and a capacitor dielectric film 128 made of these dielectric films and covering the storage electrode 126 is formed.
[0013]
Next, a conductive film made of, for example, a Ru film is deposited and patterned on the entire surface by, eg, CVD, and a plate electrode 130 made of this conductive film and covering the storage electrode 126 is formed through the capacitor dielectric film 128 (FIG. 22 (b)).
[0014]
Thus, a capacitor having the storage electrode 126, the capacitor dielectric film 128, and the plate electrode 130 and electrically connected to the source / drain diffusion layer 106 of the memory cell transistor is formed.
[0015]
Thus, a DRAM in which a memory cell is constituted by one transistor and one capacitor has been manufactured.
[0016]
[Problems to be solved by the invention]
However, when the above-described conventional method for manufacturing a semiconductor device is applied, the contact area of the storage electrode 126 with respect to the plug 110 decreases due to misalignment during patterning of the etching stopper film 118 or the hard mask 122, and the underlying structure by etching. Could cause destruction.
[0017]
The storage electrode 126 is formed in the opening 124 opened using the hard mask 122 as a mask. As shown in FIG. 23, the pattern has a flat shape extending in the extending direction of the bit line 114. Therefore, in the patterning of the etching stopper film 118 and the hard mask 122, the alignment with respect to the extending direction of the word line (gate electrode 102) becomes particularly strict.
[0018]
When the patterning of the hard mask 122 occurs in the extending direction of the word line and the opening pattern of the etching stopper film 122 overlaps the edge of the opening pattern of the hard mask 122 as shown in FIGS. 24 and 25A, the interlayer insulating film One of the two sides of the opening 124 formed in 116 and 112 in the word line extending direction is defined by a sidewall insulating film formed on the side wall of the bit line 114, and the other is defined by the hard mask 122. Therefore, an opening 124 having an opening width narrower than the pattern formed in the etching stopper film 118 is formed (FIG. 25B). As a result, the contact area between the storage electrode 126 and the plug 110 decreases, and in the worst case, the contact between the storage electrode 126 and the plug 110 cannot be obtained (FIG. 26A).
[0019]
Such a phenomenon is the same when patterning of the etching stopper film 118 occurs in the extending direction of the word line. Further, if the patterning of the hard mask 122 and the patterning of the etching stopper film 118 are displaced in the opposite directions, the word line extending direction of the opening 124 formed in the interlayer insulating films 116 and 112 as shown in FIG. One of the two sides located at is defined by the etching stopper film 118, and the other is defined by the hard mask 122, so that the contact area is further reduced.
[0020]
Further, when the interlayer insulating film 120 is etched after the storage electrode 126 is formed, there is a region where the etching stopper film 118 is not formed under the interlayer insulating film 120. Therefore, the interlayer insulating film 120 is etched simultaneously with the etching of the interlayer insulating film 120. The films 116, 112, etc. are etched to damage the underlying structure (FIG. 26 (b)).
[0021]
Therefore, when forming the opening 124 for forming the storage electrode 126 that also serves as a contact plug, a semiconductor device that suppresses a decrease in contact area due to misalignment and does not cause destruction of the underlying structure, and a manufacturing method thereof. Was desired.
[0022]
An object of the present invention is to provide a semiconductor device having a storage electrode that also serves as a contact plug, a semiconductor device that suppresses a decrease in contact area due to misalignment, and does not cause destruction of an underlying structure, and a method for manufacturing the same. There is.
[0023]
[Means for Solving the Problems]
  The above purpose isForming a first insulating film on the substrate; forming a second insulating film having etching characteristics different from those of the first insulating film on the first insulating film; and Forming a third insulating film having etching characteristics different from those of the second insulating film on the insulating film; selectively etching the first region of the third insulating film; and Forming a groove having a predetermined depth that does not reach the second insulating film, and selectively selecting the first region of the third insulating film and the second region adjacent to the first region. Etching the second insulating film only in the first region, selectively etching the second insulating film in the first region, and removing the second insulating film in the first region. Exposing the first insulating film and using the second insulating film as a stopper, the first insulating film in the first region. And a step of selectively etching the film and the third insulating film in the second region to form an opening having a contact hole reaching the substrate. Is done.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
The semiconductor device and the manufacturing method thereof according to the first embodiment of the present invention will be described with reference to FIGS.
[0026]
1 is a plan view showing the structure of the semiconductor device according to the present embodiment, FIG. 2 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment, and FIGS. 3 to 13, 16 and 17 are semiconductors according to the present embodiment. FIG. 14 and FIG. 15 are plan layout views showing the semiconductor device manufacturing method according to the present embodiment.
[0027]
First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIGS. FIG. 2 is a schematic cross-sectional view taken along the line AA ′ of FIG.
[0028]
An element isolation film 12 that defines an element region is formed on the silicon substrate 10. A memory cell transistor having a gate electrode 18 and source / drain diffusion layers 20 and 22 is formed on the element region. As shown in FIG. 1, the gate electrode 18 also functions as a conductive film that also serves as a word line. An interlayer insulating film 36 is formed on the silicon substrate 10 on which the memory cell transistors are formed. On the interlayer insulating film 36, a bit line 42 connected to the source / drain diffusion layer 20 through the plug 32 is formed. As shown in FIG. 1, a plurality of bit lines 42 are formed extending in a direction intersecting with the word lines (gate electrodes 18). An interlayer insulating film 46 is formed on the interlayer insulating film 36 on which the bit line 42 is formed. An etching stopper film 48 is formed on the interlayer insulating film 46. A cylindrical storage electrode 60 is formed on the etching stopper film 48 so as to penetrate the etching stopper film 48 and the interlayer insulating films 46 and 36 and to be connected to the plug 34 and to protrude on the etching stopper film 48. A plate electrode 64 is formed on the storage electrode 60 via a capacitor dielectric film 62.
[0029]
Thus, a DRAM having a memory cell composed of one transistor and one capacitor is formed.
[0030]
The semiconductor device according to the present embodiment is not different from the semiconductor device manufactured by the conventional method for manufacturing a semiconductor device shown in FIGS. 20A to 22B in the cross-sectional view shown in FIG. Based on the difference in the manufacturing method described later, there are the following structural features. That is, in the semiconductor device according to the present embodiment, the storage electrode 60 is formed to run on the upper surface of the etching stopper film 48 in the cross section along the extending direction of the bit line 42 (see FIG. 2). In the cross section along the extending direction of the word line (gate electrode 18), the storage electrode 60 is not formed on the upper surface of the etching stopper film 48, and the end portion of the etching stopper film 48 and the end portion of the storage electrode 60 are formed. Is different from the conventional semiconductor device in that it is formed so as to match (see FIGS. 13B and 17B). This difference is a structural feature indicating that the semiconductor device is manufactured by the method of manufacturing a semiconductor device according to the present invention.
[0031]
  Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. 3 to 8 are cross-sectional views taken along the line AA 'in FIG.,9 to 13 are process cross-sectional views along the line BB 'in FIG.
[0032]
First, the element isolation film 12 is formed on the main surface of the semiconductor substrate 10 by, for example, STI (Shallow Trench Isolation) method.
[0033]
Next, a gate insulating film 14 made of a silicon oxide film is formed on the plurality of element regions defined by the element isolation film 12 by, eg, thermal oxidation.
[0034]
Next, for example, a polycrystalline silicon film and a silicon nitride film are sequentially deposited on the entire surface by, eg, CVD, and then this laminated film is patterned, and a gate made of a polycrystalline silicon film whose upper surface is covered with the silicon nitride film 16. The electrode 18 is formed. The gate electrode 18 is not limited to the polycrystalline silicon film, and a polycide structure, a polymetal structure, a metal film, or the like may be applied.
[0035]
Next, ion implantation is performed using the gate electrode 18 as a mask to form source / drain diffusion layers 20 and 22 in the silicon substrate 10 on both sides of the gate electrode 18.
[0036]
Next, a silicon nitride film, for example, is deposited on the entire surface by, eg, CVD, and then etched back to form a sidewall insulating film 24 made of a silicon nitride film on the side walls of the gate electrode 18 and the silicon nitride film 16.
[0037]
Thus, a memory cell transistor having the gate electrode 18 and the source / drain diffusion layers 20 and 22 formed in the silicon substrate 10 on both sides thereof is formed (FIGS. 3A and 9A).
[0038]
Next, a silicon oxide film, for example, is deposited on the entire surface by, for example, a CVD method, and then the surface is polished by a CMP (Chemical Mechanical Polishing) method or the like until the silicon nitride film 16 is exposed. An interlayer insulating film 26 made of the formed silicon oxide film is formed.
[0039]
Subsequently, the contact hole 28 reaching the source / drain diffusion layer 20 and the contact hole 30 reaching the source / drain diffusion layer 22 are formed in the interlayer insulating film 26 by the normal lithography technique and etching technique. It is formed in a self-aligned manner with respect to the insulating film 24 (FIGS. 3B and 9B).
[0040]
Next, plugs 32 and 34 are embedded in the contact holes 28 and 30 opened in the interlayer insulating film 26 (FIGS. 3C and 4C). For example, a polycrystalline silicon film is deposited by CVD and etched back to leave the polycrystalline silicon film only in the contact holes 28 and 30, and then doped into the polycrystalline silicon film by ion implantation to reduce the resistance. Then, plugs 32 and 34 made of doped polysilicon are formed.
[0041]
Next, a silicon oxide film having a film thickness of, for example, 50 to 100 nm is deposited on the entire surface by, eg, CVD, and an interlayer insulating film 36 made of the silicon oxide film is formed.
[0042]
Next, a contact hole 38 reaching the plug 32 is formed in the interlayer insulating film 36 by a normal lithography technique and etching technique (FIGS. 3D and 9D). Note that the contact hole 38 reaching the plug 32 does not appear in the cross section shown in FIG. 3D, but is represented by a dotted line in the following drawings in order to clarify the positional relationship with other components.
[0043]
Next, a Ti (titanium) film, a TiN (titanium nitride) film, a W (tungsten) film, and a silicon nitride film are sequentially deposited and patterned on the entire surface by, for example, the CVD method, and the upper surface is covered with the silicon nitride film 40 and is plugged. A bit line 42 connected to the source / drain diffusion layer 20 is formed. In addition, although the bit line 42 does not appear in the cross section shown in FIG. 3E, it is represented by a dotted line in the subsequent drawings in order to clarify the positional relationship with other components.
[0044]
Next, a silicon nitride film is deposited on the entire surface by, eg, CVD, and then etched back to form a sidewall insulating film 44 on the side walls of the bit line 42 and the silicon nitride film 40 (FIGS. 3E and 9E). ).
[0045]
Next, a silicon oxide film of, eg, a 500 nm-thickness is deposited on the entire surface by, eg, CVD, the surface is polished by CMP until the silicon nitride film 40 is exposed, and the surface is made of a silicon oxide film having a flattened surface. An interlayer insulating film 46 is formed (FIGS. 4A and 10A).
[0046]
Next, a silicon nitride film having a thickness of, eg, about 40 nm is deposited on the entire surface by, eg, CVD, and an etching stopper film 48 made of a silicon nitride film is formed.
[0047]
Next, a silicon oxide film of, eg, a 700 nm-thickness is deposited on the etching stopper film 48 by, eg, CVD, to form an interlayer insulating film 50 made of a silicon oxide film.
[0048]
Next, an amorphous silicon film of, eg, a 50 nm-thickness is deposited on the interlayer insulating film 50 by, eg, CVD, and a hard mask 52 made of the amorphous silicon film is formed.
[0049]
Next, the hard mask 52 is patterned by a normal lithography technique and etching technique, and the hard mask 52 in the region where the storage electrode is to be formed is removed (FIGS. 4B and 10B).
[0050]
Next, on the interlayer insulating film 50 and the hard mask 52, a region for forming a contact hole for connecting the storage electrode to the plug 34 is exposed by a normal lithography technique, and the word line (gate electrode 18) extends in the extending direction. A resist film 54 having an extended stripe-shaped opening is formed (FIGS. 5A and 14). This resist film 54 has a periodic pattern only in the direction in which the bit line 42 extends, and has no periodicity in the direction in which the word line extends. Therefore, even if misalignment occurs in the extending direction of the word line, it does not affect the subsequent processes.
[0051]
Next, using the resist film 54 and the hard mask 52 as a mask, the interlayer insulating film 50 is anisotropically etched halfway to form a groove 56 having a depth D of, for example, about 100 to 300 nm in the interlayer insulating film 50 (FIG. 5 ( b), FIG. 11 (a)).
[0052]
Next, after removing the resist film 54, the interlayer insulating film 50 is anisotropically etched using the hard mask 52 as a mask, the etching stopper film 48 as a stopper, and the groove 56 is deepened until the etching stopper film 48 is exposed. Then, the interlayer insulating film 50 in the region where the storage electrode is to be formed is removed halfway (FIGS. 6A and 11B).
[0053]
Next, the etching stopper film 48 is anisotropically etched using the hard mask 52 and the interlayer insulating film 50 as a mask, and the etching stopper film 48 exposed in the trench 56 is selectively removed (FIG. 6B). As a result, the etching stopper film 48 only in the region where the contact hole for forming the storage electrode and the plug 34 is to be formed is removed.
[0054]
Next, using the hard mask 52 as a mask and the etching stopper film 48 as a stopper, the interlayer insulating films 50, 46 and 36 are anisotropically etched to penetrate the interlayer insulating film 50, the etching stopper film 48 and the interlayer insulating films 46 and 36. An opening 58 having a contact hole reaching the plug 34 is formed (FIGS. 7A and 12A). At this time, the opening 58 can be opened in a self-aligned manner with respect to the silicon nitride film 40 and the sidewall insulating film 44 covering the bit line 42.
[0055]
Here, the depth of the groove 56 formed in the interlayer insulating film 50 in the steps shown in FIGS. 5B and 11A is set as follows, for example.
[0056]
In general, when an insulating film having a thickness T is formed, for example, a thickness of T ± t is allowed. Further, the etching amount itself varies, and for example, E ± e is within an allowable range. Then, considering the case where the etching amount is small due to variation (E−e) and the deposited film thickness is increased (T + t), a = √ (t²+ E²Etching of the insulating film is performed under the condition of adding over-etching).
[0057]
In consideration of the process shown in FIG. 6A, in the process of etching the groove 56 up to the etching stopper film 48, the etching stopper film 48 needs to be exposed in the region where the groove 56 is formed. The interlayer insulating film 50 needs to remain. If the film thickness of the interlayer insulating film 50 to be etched in the step shown in FIG. 6A is TD, the etching corresponding to (TD + a) is actually performed in consideration of variations. At this time, the film thickness of the interlayer insulating film 50 is T in a region where the trench 56 is not formed, and the amount of etching needs to be smaller than T in order to leave the interlayer insulating film 50 in this region. Therefore, in this etching, it is necessary to set the depth D of the groove to (D >> a) so that T >> (TD−a).
[0058]
On the other hand, the interlayer insulating film 50 remaining on the etching stopper film 48 is removed simultaneously with the opening of the contact hole that penetrates the interlayer insulating films 46 and 36 in the step shown in FIG. If the interlayer insulating film 50 is too thick, the underlying structure such as the plug 34 may be greatly damaged in the process of removing the interlayer insulating film 50. Therefore, it is desirable that the interlayer insulating film 50 remaining on the etching stopper film 48 be thinner than the depth b of the contact hole that penetrates the interlayer insulating films 46 and 36. Since the film thickness of the interlayer insulating film remaining on the etching stopper film 48 is (D−a), the depth D of the groove 56 can be made thinner than (a + b) from (D−a) <b. It is valid.
[0059]
Next, after depositing a Ru film of, eg, a 30 nm-thickness on the entire surface by, eg, CVD, the Ru film and the hard mask 52 are removed flatly, for example, by CMP, until the surface of the interlayer insulating film 50 is exposed. Thus, the storage electrode 60 made of a Ru film and connected to the plug 34 is formed in the opening 58 (FIGS. 7B and 12B).
[0060]
The conductive film for constituting the storage electrode 60 is appropriately selected according to the compatibility with the capacitor dielectric film 62 to be formed later. For example, Ta as the capacitor dielectric film 62₂O_FiveWhen the dielectric film is used, Ru (ruthenium), RuOx (ruthenium oxide), W (tungsten), WN (tungsten nitride), or the like can be used as the storage electrode 60. When a dielectric film such as BST (BaSrTiOx) or ST (SrTiOx) is used as the capacitor dielectric 62, the storage electrode 60 is Pt (platinum), Ru, RuOx, W, SRO (SrRuO)._Three) Etc. can be used. Further, the capacitor dielectric film 62 is turned ON (SiO 2₂In the case of using a dielectric film such as a / SiN) film, doped polysilicon or the like can be used as the storage electrode 60. Further, when a dielectric film such as PZT is used as the capacitor dielectric film 62, Pt or the like can be used as the storage electrode 60. In addition, TiOx (titanium oxide), SiN (silicon nitride), SiON (silicon nitride oxide), Al₂O_ThreeIn the case of using a dielectric film such as (alumina) or SBT (SrBiTiOx), it may be appropriately selected according to the compatibility with these dielectric films.
[0061]
In addition, a conductive film having excellent adhesion to the etching stopper film 48, the interlayer insulating film 46, and the like may be provided as an adhesion layer on the base of the Ru film constituting the storage electrode 60. By providing the adhesion layer, it is possible to prevent the etchant from permeating from the interface between the etching stopper film 48 and the storage electrode 60 when the interlayer insulating film 50 is removed later. As the conductive film for forming the adhesion layer, for example, TiN (titanium nitride), WN (tungsten nitride), or the like can be used. The compatibility between the adhesion layer and the capacitor dielectric film to be formed later is desirably good. However, when these films have poor compatibility, for example, various applications described in Japanese Patent Application No. 10-315370 by the same applicant are used. Using this technique, a part of the adhesion layer may be removed after the interlayer insulating film 50 is etched.
[0062]
Next, the interlayer insulating film 50 is selectively etched by wet etching using, for example, a hydrofluoric acid aqueous solution, using the etching stopper film 48 as a stopper (FIGS. 8A and 13A).
[0063]
Next, Ta, for example, with a film thickness of 10 to 30 nm is formed on the entire surface by, eg, CVD.₂O_FiveA film or BST film is deposited and Ta₂O_FiveAlternatively, a capacitor dielectric film 62 made of BST is formed.
[0064]
Next, a Ru film having a film thickness of 50 to 300 nm, for example, is deposited on the entire surface by, eg, CVD, and then this Ru film is patterned by a normal lithography technique and etching technique to form a plate electrode 64 made of a Ru film ( FIG. 8B and FIG. 13B).
[0065]
The material constituting the plate electrode 64 is preferably selected as appropriate based on the compatibility with the capacitor dielectric film 62, as in the case of the material constituting the storage electrode 60. In addition to the Ru film, materials such as a RuOjsx film, a W film, a WN film, an SRO film, a Pt film, and a TiN film can be selected.
[0066]
Next, if necessary, a wiring layer (not shown) connected to the plate electrode 64, a wiring layer (not shown) connected to a peripheral circuit region (not shown), and the like are formed.
[0067]
Thus, a DRAM comprising one transistor and one capacitor can be manufactured.
[0068]
Next, in the semiconductor device manufacturing method according to the present embodiment, a case where misalignment occurs in the word line extending direction in the lithography process when the hard mask 52 is patterned will be described.
[0069]
In the step shown in FIG. 10B, when the pattern of the hard mask 52 is misaligned in the extending direction of the word line and the planar layout shown in FIG. 15 is obtained, the cross section along the line BB ′. The figure is as shown in FIG.
[0070]
In this layout, similarly to the steps shown in FIGS. 11A to 12A, the interlayer insulating film 50, the etching stopper film 48, and the interlayer insulating films 46 and 36 are made anisotropic by using the hard mask 52 as a mask. When etched, two sides located in the word line extending direction of the opening 56 formed in the interlayer insulating films 46 and 36 are defined by the side wall insulating film 44 formed on the side wall of the bit line 42, The other is defined by the hard mask 52 (FIG. 16B). As a result, the opening width of the opening 56 is reduced as compared with the case where there is no misalignment, and the contact area between the storage electrode 60 and the plug 34 is reduced as in the case of the conventional semiconductor device (FIG. 17). (A)). However, in the semiconductor device manufacturing method according to the present embodiment, the opening width of the opening 56 in the word line extending direction depends only on the misalignment amount of the hard mask 52 and does not depend on the pattern of the etching stopper film 48. The opening width of the opening 56 does not narrow beyond the amount of misalignment of the hard mask 52 as in the conventional method of manufacturing a semiconductor device.
[0071]
Further, by applying the semiconductor device manufacturing method according to the present embodiment, the lower surface of the interlayer insulating film 50 is completely covered with the etching stopper film 48, so that the interlayer insulating film 50 is etched in the step of FIG. In some cases, the etching solution does not penetrate into the lower layer of the etching stopper film 48 (FIG. 17B).
[0072]
As described above, according to this embodiment, in the semiconductor device having the storage electrode that also serves as the contact plug, it is possible to suppress a decrease in contact area due to misalignment. Further, it is possible to prevent the lower layer structure from being damaged by etching in the etching process of the interlayer insulating film exposing the outer surface of the storage electrode.
[0073]
[Second Embodiment]
A method for fabricating a semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS. The same components as those of the semiconductor device and the manufacturing method thereof according to the first embodiment shown in FIGS. 1 to 17 are denoted by the same reference numerals, and description thereof is omitted or simplified.
[0074]
18 and 19 are process cross-sectional views illustrating the method for fabricating the semiconductor device according to the present embodiment.
[0075]
First, in the same way as in the semiconductor device manufacturing method according to the first embodiment shown in FIGS. 3A to 4A, for example, a memory cell transistor, a bit line 42, an interlayer insulating film 46, and the like are formed.
[0076]
Next, a silicon nitride film of, eg, a 40 nm-thickness is deposited on the interlayer insulating film 46 by, eg, CVD, and an etching stopper film 48 made of a silicon nitride film is formed.
[0077]
Next, a silicon oxide film of, eg, a 700 nm-thickness is deposited on the etching stopper film 48 by, eg, CVD, to form an interlayer insulating film 50 made of a silicon oxide film.
[0078]
Next, an amorphous silicon film of, eg, a 50 nm-thickness is deposited on the interlayer insulating film 50 by, eg, CVD, and a hard mask 52 made of the amorphous silicon film is formed.
[0079]
Next, a resist film 66 that exposes a region where the storage electrode 60 is to be formed is formed on the hard mask 52.
[0080]
Next, using the resist film 66 as a mask, inclined ion implantation is performed from a direction inclined by a predetermined angle in the extending direction of the bit line 42 (FIG. 18A). For example, P (phosphorus) ion, acceleration energy is 20 keV, and dose is 1 × 10.¹⁵cm^-2Then, ions are implanted from a direction inclined by 20 °. In the tilted ion implantation, the ion incident angle is adjusted so that ions are implanted only into about 2/3 of the opening of the resist film 66 and the remaining about 1/3 of the region is not implanted by the shadow effect. . For example, if the opening width of the resist film 66 is 0.4 μm and the film thickness of the resist film 66 is 3 μm, ion implantation is performed at an angle of about 24 ° from the vertical direction of the substrate. Ion implantation can be performed only in the region of about 2/3 of the opening. By performing such ion implantation while tilting in both directions in which the bit lines extend, ion implantation is performed in a region about 1/3 of the center of the opening of the resist film 66 at a dose twice that of other regions. It can be carried out.
[0081]
A region where ion implantation is performed with a double dose corresponds to a region where a contact hole for connecting the storage electrode 60 and the plug 34 is to be formed. In this embodiment, the ion implantation is performed at a dose twice as large as the center of the opening of the resist film 66 by connecting the storage electrode 60 and the plug 34 in the planar layout shown in FIG. This is because a region for forming a contact hole for this purpose corresponds to this area. Therefore, the numerical value of 1/3 is not critical, but the region where ion implantation is performed at a double dose amount depends on the region where the contact hole for connecting the storage electrode 60 and the plug 34 is to be formed. May be set as appropriate.
[0082]
In addition, the technique for performing tilted ion implantation from four directions has already been established in terms of the apparatus, and there is no problem in adopting the above process.
[0083]
Then, for example, HF + HNO_Three+ CH_ThreeBy wet etching using an etching solution of COOH = 1: 3: 8, the hard mask 52 in the region where the ion implantation is performed with a double dose is selectively removed (FIG. 18B).
[0084]
This etching solution has a property that the etching rate rapidly decreases as the impurity concentration of p-type silicon increases. Therefore, a P-type silicon film is deposited in the process of depositing the hard mask 52, an N-type impurity is implanted in the ion implantation step, and only the central region in which ion implantation is performed at a double dose is selectively made N-type. By reversing, the mask film in this region can be selectively removed with the etching solution.
[0085]
In addition, by using NaOH, KOH, hydrazine, ethylenediamine, etc. whose etching amount is dependent on the dose amount as an etching solution and controlling the etching conditions, it is possible to harden the region where ion implantation has been performed at a double dose amount. The mask 52 can be selectively removed.
[0086]
The etching rate of the hard mask 52 depends on the dose amount of ion implantation, and when the dose rate exceeds a certain dose amount, the etching rate increases rapidly. Therefore, by setting the ion implantation dose so that the dose is less than this critical value and the double dose exceeds this critical value, the hard mask in the region where the ion implantation is performed with the double dose. 52 can be selectively removed.
[0087]
Next, in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIG. 5B, the interlayer insulating film 50 is anisotropically etched using the resist film 66 and the hard mask 52 as a mask, and the interlayer insulating film 50 A groove 56 is formed in the substrate (FIG. 19A).
[0088]
Next, the hard mask 52 is anisotropically etched using the resist film 66 as a mask, and the hard mask 52 in the region where the storage electrode 60 is to be formed is removed (FIG. 19B). Thereby, a structure similar to that shown in FIG. 5B can be formed.
[0089]
Next, a DRAM including one transistor and one capacitor is manufactured in the same manner as the method for manufacturing the semiconductor device according to the first embodiment shown in FIGS. 6A to 8B.
[0090]
As described above, according to the present embodiment, by utilizing the shadow effect associated with the tilted ion implantation, the contact hole formation scheduled region for connecting the storage electrode 60 and the plug 34 can be formed by one lithography process. Since the region where the storage electrode 60 is to be formed can be defined, the lithography process that greatly affects the manufacturing cost can be reduced by one process.
[0091]
[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications can be made.
[0092]
For example, in the above embodiment, the case where the present invention is applied to a semiconductor device having a cylindrical capacitor has been described, but the present invention can be similarly applied to a semiconductor device having a columnar capacitor. In this case, the storage electrode 60 may be formed so as to completely fill the opening 58 in the steps of FIGS. 7B, 12B, and 17A.
[0093]
In the above-described embodiment, etching is performed using the etching stopper film 48 as a stopper in the process of forming the opening 58. However, similar etching is performed by controlling etching conditions such as etching time instead of forming the etching stopper film 48. May be. In this case, the depth of D may be the same as or slightly deeper than b, and the etching may be stopped when the tip of the groove 56 reaches the plug 34. However, it is desirable to form the etching stopper film 48 from the viewpoint of controllability.
[0094]
In the above-described embodiment, the example in which the present invention is applied to the capacitor of the DRAM has been described. However, the present invention is not limited to the DRAM, and can be widely applied to semiconductor integrated circuit devices that require a large number of capacitors. In particular, when applied to a ferroelectric memory (FeRAM) having a configuration similar to that of a DRAM, a highly integrated FeRAM can be manufactured.
[0095]
In the above embodiment, the case where the present invention is applied to the step of forming the opening 58 for embedding the storage electrode 60 has been described. However, the present invention forms a contact hole and a contact in the lower insulating film, and performs etching. The present invention can be widely applied to a method for manufacturing a semiconductor device in which an opening wider than a contact hole is formed in an upper insulating film formed through a stopper film. For example, the present invention may be applied to via holes and wiring trench openings in a dual damascene process.
[0096]
In the above-described embodiment, the case where the present invention is applied to a COB (Capacitor Over Bit Line) structure in which a capacitor is disposed above the bit line has been described. However, the present invention relates to formation of a capacitor, There is no direct relationship with the position of Therefore, the present invention can be similarly applied to a CUB (Capacitor Under Bit Line) structure in which a bit line is arranged on an upper layer of a capacitor.
[0097]
【The invention's effect】
As described above, according to the present invention, in a semiconductor device having a storage electrode that also serves as a contact plug, a reduction in contact area due to misalignment can be suppressed. Further, it is possible to prevent the lower layer structure from being damaged by etching in the etching process of the interlayer insulating film that exposes the outer surface of the storage electrode.
[Brief description of the drawings]
FIG. 1 is a plan view showing a structure of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view showing the structure of the semiconductor device according to the first embodiment of the present invention.
FIG. 3 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention;
FIG. 4 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention;
FIG. 5 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
6 is a process cross-sectional view (No. 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention; FIG.
FIG. 7 is a process sectional view (No. 5) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention;
FIG. 8 is a process cross-sectional view (No. 6) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention;
FIG. 9 is a process cross-sectional view (No. 7) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention;
FIG. 10 is a process cross-sectional view (No. 8) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention;
FIG. 11 is a process cross-sectional view (No. 9) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention;
FIG. 12 is a process cross-sectional view (No. 10) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention;
FIG. 13 is a process cross-sectional view (No. 11) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention;
FIG. 14 is a plan layout view (No. 1) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention;
FIG. 15 is a plan layout view (No. 2) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention;
FIG. 16 is a process cross-sectional view (No. 12) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention;
FIG. 17 is a process cross-sectional view (No. 13) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention;
FIG. 18 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the second embodiment of the invention;
FIG. 19 is a process cross-sectional view (No. 2) illustrating the method for manufacturing the semiconductor device according to the second embodiment of the invention;
FIG. 20 is a process cross-sectional view (part 1) illustrating the conventional method for manufacturing a semiconductor device;
FIG. 21 is a process cross-sectional view (part 2) illustrating the conventional method for manufacturing a semiconductor device;
FIG. 22 is a process cross-sectional view (part 3) illustrating the conventional method for manufacturing a semiconductor device;
FIG. 23 is a plan layout view showing a conventional method of manufacturing a semiconductor device.
FIG. 24 is a plan layout view illustrating a problem in the conventional method of manufacturing a semiconductor device.
FIG. 25 is a process cross-sectional view (No. 1) for explaining a problem in the conventional method of manufacturing a semiconductor device;
FIG. 26 is a process cross-sectional view (No. 2) for explaining a problem in the conventional method of manufacturing a semiconductor device;
FIG. 27 is a process cross-sectional view (part 3) for explaining a problem in the conventional method of manufacturing a semiconductor device;
[Explanation of symbols]
10 ... Silicon substrate
12 ... element isolation film
14 ... Gate insulating film
16 ... Silicon nitride film
18 ... Gate electrode
20, 22 ... Source / drain diffusion layer
24, 44 ... sidewall insulating film
26, 36, 46, 50 ... interlayer insulating film
28, 30, 38 ... contact holes
32, 34 ... plug
40. Silicon nitride film
42 ... bit line
48 ... Etching stopper film
52 ... Hard mask
54, 66 ... resist film
56 ... Groove
58 ... Opening
60 ... Storage electrode
62. Capacitor dielectric film
64 ... Plate electrode
100: Silicon substrate
102 ... Gate electrode
104, 106 ... Source / drain diffusion layer
108, 110 ... plug
112, 116, 120 ... interlayer insulating film
114: Bit line
118 ... Etching stopper film
122 ... Hard mask
124 ... opening
126 ... Storage electrode
128: Capacitor dielectric film
130 ... Plate electrode

Claims (3)

Forming a first insulating film on the substrate;
Forming a second insulating film having etching characteristics different from those of the first insulating film on the first insulating film;
Forming a third insulating film having etching characteristics different from those of the second insulating film on the second insulating film;
Selectively etching the first region of the third insulating film to form a groove having a predetermined depth that does not reach the second insulating film in the first region;
Selectively etching the first region of the third insulating film and the second region adjacent to the first region to expose the second insulating film only in the first region; ,
Selectively etching the second insulating film in the first region to expose the first insulating film in the first region;
Using the second insulating film as a stopper, the first insulating film in the first region and the third insulating film in the second region are selectively etched to have a contact hole reaching the substrate. And a step of forming an opening. A method of manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 1 ,
After the step of forming the third insulating film, a step of forming a first mask film that exposes the first region and the second region, and the first region covering the second region Forming a second mask film that exposes
In the step of forming the groove, the third insulating film is etched using the first mask film and the second mask film as a mask,
In the step of exposing the second insulating film, the step of exposing the first insulating film, and the step of forming the opening, the first insulating film, the first insulating film using only the first mask film as a mask Etching the second insulating film and the third insulating film. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 1 ,
After the step of forming the third insulating film, a step of forming a first mask film on the third insulating film, and the first region and the second region on the first mask film Forming a second mask film exposing the region, and performing ion implantation in the first region at a higher concentration than the second region using the shadow effect of the second mask film; And selectively etching the first mask film in the first region using a difference in etching rate due to a difference in concentration of implanted ions ,
After the step of forming the groove, the method further comprises a step of selectively removing the first mask film in the second region using the second mask film as a mask,
In the step of forming the groove, the step of exposing the second insulating film, the step of exposing the first insulating film, and the step of forming the opening, the first mask film and the second mask Etching the first insulating film, the second insulating film, and the third insulating film using a film as a mask. A method for manufacturing a semiconductor device, comprising:

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