KR101083821B1 - Method for fabricating semicondoctor device - Google Patents

Abstract

The present invention is to provide a method for manufacturing a semiconductor device that can ensure the exposure margin of the photosensitive film, the present invention comprises the steps of forming an insulating film on the substrate; Forming a hard mask layer on the insulating film; Forming a photoresist pattern on the hard mask layer; Etching the hard mask layer by isotropic etching to form a hard mask pattern which opens a wider line width than the photoresist pattern; Including the step of etching the insulating film using the hard mask pattern as an etch barrier, the present invention forms a hard mask pattern for opening a wider line width than the photoresist pattern by isotropic etching to secure the exposure margin of the photoresist film, There is an effect of preventing the bridge between the holes, further increasing the line width defined by the upper portion of the hard mask pattern, and reducing the sheet resistance with the lower layer by increasing the area of the holes.

Storage capacity, line width, capacitor

Description

Manufacturing Method of Semiconductor Device {METHOD FOR FABRICATING SEMICONDOCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly to a method for manufacturing a contact hole in a semiconductor device.

Recently, due to the miniaturization of patterns in highly integrated memory devices, the line width of holes is narrowed, and the spacing between holes is also narrowed. In addition, the high aspect ratio reduces the etch margin and narrows the line width.

In order to increase the charge capacity of the charge storage electrode (Capacitor), the line width of the hole must be increased. In this case, there is a limit to the mask process using the photosensitive film. That is, due to the limitation of the exposure process of the photoresist film, it is not possible to form the maximum hole line width that can prevent the bridge and increase the storage capacity at the same time.

In addition, if the line width of the hole (Hole) is reduced to secure the exposure margin of the photoresist film, the storage capacity of the capacitor is reduced, resulting in deterioration of electrical characteristics. This electrical deterioration is a major cause of refresh deterioration.

Therefore, there is a need for a method that can increase the line width of holes while preventing bridges between holes.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of manufacturing a semiconductor device capable of securing an exposure margin of a photosensitive film.

Method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of forming an insulating film on the substrate; Forming a hard mask layer on the insulating film; Forming a photoresist pattern on the hard mask layer; Etching the hard mask layer by isotropic etching to form a hard mask pattern which opens a wider line width than the photoresist pattern; And etching the insulating layer using the hard mask pattern as an etch barrier.

In particular, the isotropic etching is characterized in that the progress in the equipment of MERIE (Magnetically Enhanced Reactive Ion Beam Etching) method.

In addition, the isotropic etching is characterized in that the proceeding in the absence of magnetic flux (Magnetic Flux) in the etching equipment.

The isotropic etching may be performed by applying a bias power of 50 W to 60 W in an etching apparatus and applying a pressure of 35 mTorr to 40 mTorr.

In addition, the isotropic etching is characterized in that to proceed by maintaining the electrode (Electrode) temperature of the etching equipment to 60 ℃ ~ 80 ℃.

The method may further include ar sputtering the hard mask pattern after forming the hard mask pattern.

According to another aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device. Forming a sacrificial layer on the insulating film; Forming a hard mask layer on the sacrificial layer; Forming a photoresist pattern on the hard mask layer; Etching the hard mask layer by isotropic etching to form a hard mask pattern which opens a wider line width than the photoresist pattern; Forming a storage node hole for opening the storage node contact plug by etching the sacrificial layer using the hard mask pattern as an etch barrier; And forming a storage node connected to the storage node contact plug in the storage node hole.

In particular, the hard mask layer is characterized in that it comprises polysilicon.

In addition, the isotropic etching is performed using a mixed gas of Cl ₂ , HBr and O ₂ , the Cl ₂ is characterized in that the flow proceeds at a flow rate of 5sccm ~ 10sccm, the HBr flows from 150sccm ~ 200sccm.

The method may further include forming a cylindrical storage node by removing the sacrificial layer after forming the storage node.

The method of manufacturing the semiconductor device of the present invention described above has the effect of securing the exposure margin of the photosensitive film by forming a hard mask pattern which opens a wider line width than the photosensitive film pattern by isotropic etching.

In addition, the present invention has an effect that can prevent the bridge (Bridge) between the holes due to lack of exposure by securing the exposure margin of the photosensitive film.

In addition, the present invention can further increase the line width defined by the upper portion of the hard mask pattern by arranging the upper portion of the hard mask pattern rounded and inclined by Ar sputtering.

In addition, the present invention has the effect of increasing the area of the hole by forming a hole using a hard mask pattern that opens a wider line width than the photosensitive film pattern.

In addition, the present invention has the effect of reducing the sheet resistance with the lower layer by increasing the area of the hole.

In addition, the capacitor manufacturing method of the semiconductor device of the present invention has an effect of increasing the storage capacity and refresh of the subsequent capacitor by increasing the area of the storage node hole.

In addition, the method of manufacturing a capacitor of the semiconductor device of the present invention has an effect of preventing the collapse of the storage node during the subsequent deep-out process by increasing the area of the storage node hole.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

The present invention is to form a hard mask pattern to open a wider line width than the photoresist pattern by using isotropic etching after the photoresist pattern is formed to secure the exposure margin of the photoresist, the description is shown in Figures 1a to 1d. .

1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 1A, an insulating film 12 is formed on the substrate 11. The substrate 11 may be a silicon substrate, and may include an isolation layer and a well. The substrate 11 may include a series of structures formed on a silicon substrate.

The insulating film 12 is for interlayer insulation and may be an oxide film. The oxide film is HDP (High Density Plasma) oxide film, BPSG (Boron Phosphorus Silicate Glass) film, PSG (Phosphorus Silicate Glass) film, BSG (Boron Silicate Glass) film, TEOS (Tetra Ethyle Ortho Silicate) film, USG (Un-doped Silicate) film Glass (FSG), Fluorinated Silicate Glass (FSG) film, Carbon Doped Oxide (CDO) film, and Organic Silicate Glass (OSG) film, or any one selected from the group consisting of a laminated film of at least two or more layers can be formed have. Alternatively, the film may be formed by a spin coating method such as a spin on dielectric (SOD) film.

Subsequently, a hard mask layer 13 is formed on the insulating film 12. The hard mask layer 13 may serve as an etch barrier when the insulating layer 12 is etched, and may be formed of a material having a selectivity with respect to the insulating layer 12. The hard mask layer 13 may be formed of a material having an insulating property, and the material having the insulating property is a group consisting of a carbon-based polymer, an amorphous carbon, a silicon-based polymer, a polysilicon, an oxide film, a nitride film, and an oxynitride film. Any one selected from can be used. When the insulating film 12 is an oxide film, the hard mask layer 13 may be formed of a material other than the oxide film for the selectivity with respect to the insulating film.

Subsequently, the photoresist pattern 14 is formed on the hard mask layer 13. The photoresist layer pattern 14 may be formed by coating a photoresist layer on the hard mask layer 13 and patterning the photoresist layer by exposure and development.

As shown in FIG. 1B, the hard mask layer 13 (see FIG. 1A) is etched by isotropic etching to form a hard mask pattern 13A that opens a wider line width than the photoresist pattern 14.

Isotropic etching can be performed on equipment of Magnetically Enhanced Reactive Ion Beam Etching (MERIE). In addition, the isotropic etching may be performed in the absence of magnetic flux in the etching equipment. This means that when the magnetic flux is used as 0 Ｇ as compared to when the magnetic flux is used as 50 로 as the comparative example, the impact force of the particles is lowered to reduce the etch rate and laterally etched by isotropic etching. This can be induced.

In addition, the isotropic etching may be performed by applying a bias power of 50W ~ 60W, and a pressure of 35mTorr ~ 40mTorr in the etching equipment. When the bias power is reduced to 50W to 60W, the linearity of the etching particles may be degraded, thereby increasing the isotropic etching effect. In addition, increasing the pressure from 35mTorr to 40mTorr reduces the free path of the etching gas and at the same time increases the scattering effect of the particles to induce isotropic etching to secure an open area. can do.

In addition, isotropic etching may amplify the isotropic etching by maintaining the electrode temperature of the etching equipment at 60 ℃ to 80 ℃ to increase the reaction activity of the plasma.

As described above, by forming the hard mask pattern 13A by isotropic etching, the line width W ₂ wider than the line width W ₁ opened by the photosensitive film pattern 14 may be opened. In addition, by defining the line width by isotropically etching the hard mask pattern 13A, the exposure margin of the photosensitive film pattern 14 can be ensured to prevent the bridge between holes due to the exposure shortage.

In particular, when the open portion opened by the photoresist pattern 14 is elliptical, the etching speeds of the wide and narrow portions are different from each other, and the hard mask pattern 13A has a rectangular open portion. This etching pattern will be described in detail later in FIGS. 3A and 3B.

As shown in FIG. 1C, the photoresist pattern 14 is removed. The photoresist pattern 14 may be removed by dry etching, and the dry etching may be performed by an oxygen strip process.

Subsequently, Ar sputtering is performed on the hard mask pattern 13B. Ar sputtering may round the top of the hard mask pattern 13B and increase the line width defined by the top of the hard mask pattern 13B by having an inclined profile.

As shown in FIG. 1D, the insulating layer 12 is etched using the hard mask pattern 13B as an etch barrier to form the recess 15 in the form of a hole or a groove. The recess 15 may be a damascene structure having vias, trenches or a mixture thereof.

 The concave portion 15 is formed with a wider line width by etching using the hard mask pattern 13B which opens the line width wider than the line width of the photoresist pattern through isotropic etching in FIG. 1B, and hardly forms Ar sputtering in FIG. 1C. By increasing the line width defined by the upper portion of the mask pattern 13B, the profile of the hard mask pattern 13B can be transferred, so that the upper width of the concave portion 15 can also be increased.

The hard mask pattern may be removed when the formation of the recess 15 is completed, or may be removed through the removal process after the recess 15 is formed.

As described above, the concave portion 15 having the increased line width may increase a space of 20% or more as compared with the concave portion etched by the line width of the photoresist pattern. In addition, when the recess 15 is used as a subsequent contact plug, the sheet resistance Rs may be reduced by increasing the contact area between the upper layer and the lower layer. When the recess 15 is a storage node hole for subsequent storage node formation, it is possible to improve the storage capacity and refresh of the capacitor. In addition, by increasing the area of the storage node holes, it is possible to prevent the storage node from falling down during the subsequent deep-out process.

In a specific embodiment to which the embodiment of the present invention is applied, a method of manufacturing a capacitor of a semiconductor device is illustrated in FIGS. 2A to 2F.

2A to 2F are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 2A, an insulating film 22 is formed on the substrate 21. The substrate 21 may be a silicon substrate on which a DRAM process is performed, and may include an isolation layer and a well. In addition, before the insulating layer 22 is formed, a series of structures may include a gate pattern and the like.

The insulating layer 22 is for interlayer insulation, and a bit line pattern may be formed before forming the insulating layer 22. The insulating film 22 may be an oxide film. The oxide film is HDP (High Density Plasma) oxide film, BPSG (Boron Phosphorus Silicate Glass) film, PSG (Phosphorus Silicate Glass) film, BSG (Boron Silicate Glass) film, TEOS (Tetra Ethyle Ortho Silicate) film, USG (Un-doped Silicate) film Glass (FSG), Fluorinated Silicate Glass (FSG) film, Carbon Doped Oxide (CDO) film, and Organic Silicate Glass (OSG) film, or any one selected from the group consisting of a laminated film of at least two or more layers can be formed have. Alternatively, the film may be formed by a spin coating method such as a spin on dielectric (SOD) film.

Subsequently, a storage node contact plug 23 is formed through the insulating layer 22 and connected to the substrate 21. The storage node contact plug 23 selectively etches the insulating film 22 to form a contact hole for opening the substrate 21, and then fills a conductive material and exposes the surface of the insulating film 22. It can be formed by flattening. The contact hole may be formed through the embodiment of the present invention illustrated in FIGS. 1A to 1C. In addition, the contact hole may be formed by a self aligned contact etching.

For example, the conductive material may be formed of any one selected from the group consisting of a transition metal film, a rare earth metal film, an alloy film thereof, and a silicide film thereof. Further, it may be formed of a polysilicon film doped with impurity ions. In addition, the conductive materials may be formed in a laminated structure in which at least two layers are stacked.

On the other hand, when the contact plug 23 is made of a metal film (transition metal, rare earth metal), a barrier metal layer (not shown) may be further formed between the contact plug 23 and the contact hole. In this case, the barrier metal layer is formed of a laminated film or a single layer film composed of an adhesive layer and a diffusion barrier film. Here, the laminated film (adhesive layer / diffusion prevention film) is formed of any one selected from the group consisting of Ti / TiN, Ta / TaN or W / WN. Further, the single layer film is formed of any one selected from the group consisting of AlSiTiN, NiTi, TiBN, ZrBN, TiAlN or TiB ₂ . In addition, it may be formed by an atomic layer deposition (ALD) process so as not to degrade the buried characteristics of the contact plug 23 to be formed through a subsequent process.

The planarization may be performed by an etch back or chemical mechanical polishing process, but is preferably performed by a chemical mechanical polishing process having excellent planarization characteristics.

Subsequently, an etch stop film 24 is formed on the insulating film 22. The etch stop layer 24 prevents the insulating layer 22 from being lost during subsequent sacrificial layer etching or from being attacked by the etching solution during the dip-out for forming the cylindrical storage node. The etch stop layer 24 may be formed of a material having a selectivity with respect to the insulating layer 22 and the sacrificial layer. When the insulating film 22 is an oxide film, the etch stop film 24 may be formed of a nitride film. The nitride film may include a silicon nitride film.

Subsequently, a sacrificial layer 25 is formed on the etch stop layer 24. The sacrificial layer 25 is to provide a subsequent storage node hole and may be formed of an oxide layer. The oxide film is HDP (High Density Plasma) oxide film, BPSG (Boron Phosphorus Silicate Glass) film, PSG (Phosphorus Silicate Glass) film, BSG (Boron Silicate Glass) film, TEOS (Tetra Ethyle Ortho Silicate) film, USG (Un-doped Silicate) film Glass (FSG), Fluorinated Silicate Glass (FSG) film, Carbon Doped Oxide (CDO) film, and Organic Silicate Glass (OSG) film, or any one selected from the group consisting of a laminated film of at least two or more layers can be formed have. Alternatively, the film may be formed by a spin coating method such as a spin on dielectric (SOD) film.

Subsequently, a hard mask layer 26 is formed on the sacrificial layer 25. The hard mask layer 26 may serve as an etch barrier when the hard mask layer 26 is etched from the sacrificial layer 25, and may be formed of a material having a selectivity with respect to the sacrificial layer 25. The hard mask layer 26 may be formed of a material having an insulating property, and the material having the insulating property is a group consisting of a carbon-based polymer, amorphous carbon, a silicon-based polymer, polysilicon, an oxide film, a nitride film, and an oxynitride film. Any one selected from can be used. When the sacrificial layer 25 is an oxide film, the hard mask layer 26 may be formed of a material other than the oxide film for the selectivity with respect to the sacrificial layer, and is preferably formed of polysilicon.

Subsequently, a photosensitive film pattern 27 is formed on the hard mask layer 26. The photoresist layer pattern 27 may be formed by coating a photoresist layer on the hard mask layer 26 and patterning the storage node hole to be opened by exposure and development.

As shown in FIG. 2B, the hard mask layer 26 (see FIG. 2A) is etched by isotropic etching to form a hard mask pattern 26A that opens a wider line width than the photoresist pattern 27.

Isotropic etching can be performed on equipment of Magnetically Enhanced Reactive Ion Beam Etching (MERIE). In addition, the isotropic etching may be performed in the absence of magnetic flux in the etching equipment. This means that when the magnetic flux is used as 0 Ｇ as compared to when the magnetic flux is used as 50 로 as the comparative example, the impact force of the particles is lowered to reduce the etch rate and laterally etched by isotropic etching. This can be induced.

In addition, the isotropic etching may be performed by applying a bias power of 50W to 60W and a pressure of 35mTorr to 40mTorr in the etching equipment. When the bias power is reduced to 50W to 60W, the straightness of the etch particles may be degraded, thereby increasing the isotropic etching effect. In addition, increasing the pressure from 35mTorr to 40mTorr reduces the free path of the etching gas and at the same time increases the scattering effect of the particles to induce isotropic etching to secure an open area. can do.

In addition, isotropic etching may amplify the isotropic etching by maintaining the electrode temperature of the etching equipment at 60 ℃ to 80 ℃ to increase the reaction activity of the plasma.

In addition, when the hard mask layer 26 is polysilicon, isotropic etching may be performed using a mixed gas of Cl ₂ , HBr, and O ₂ . In this case, Cl ₂ may flow at a flow rate of 5 sccm to 10 sccm, and the HBr may flow at a flow rate of 150 sccm to 200 sccm. This may induce isotropic etching by increasing the gas ratio of HBr to Cl ₂ .

As described above, by forming the hard mask pattern 26A by isotropic etching, the line width W ₂ wider than the line width W ₁ opened by the photosensitive film pattern 27 may be opened. In addition, by defining the line width by isotropically etching the hard mask pattern 26A, an exposure margin of the photosensitive film pattern 27 can be ensured to prevent a bridge between the storage node holes due to exposure shortage.

In particular, when the storage node hole opened by the photoresist pattern 27 is elliptical, the etching speeds of the wide and narrow portions are different from each other, and the hard mask pattern 26A has a rectangular storage node hole. This etching pattern will be described in detail later in FIGS. 3A and 3B.

As shown in FIG. 2C, the photoresist pattern 27 (see FIG. 2B) is removed. The photoresist pattern 27 may be removed by dry etching, and the dry etching may be performed by an oxygen strip process.

Subsequently, Ar sputtering is performed on the hard mask pattern 26B. Ar sputtering can round the top of the hard mask pattern 26B and have an inclined profile to further increase the line width defined by the top of the hard mask pattern 26B.

As shown in FIG. 2D, the storage node hole exposing the storage node contact plug 23 by etching the sacrificial layer 25A and the etch stop layer 24A using the hard mask pattern 26B (see FIG. 2C) as an etch barrier. (28, Storage Node Hole) is formed.

The storage node hole 28 first etches the sacrificial layer 25A with a gas for etching an oxide film, and then etches the etch stop layer 24A with a gas for etching a nitride film. This is to prevent the insulating layer 22 under the etch stop layer 24A from being lost during the etching of the sacrificial layer 25A.

The storage node hole 28 is formed with a wider line width by etching using a hard mask pattern that opens a line width wider than the line width of the photoresist pattern through isotropic etching in FIG. 2B, and hard sputtering by ar sputtering in FIG. 2C. By increasing the line width defined by the top of the hard mask pattern profile can be transferred, the top width of the storage node hole 28 can also be increased.

The hard mask pattern may be removed when the formation of the storage node hole 28 is completed, or after the storage node hole 28 is formed, it may be removed through a removal process.

As described above, the storage node hole 28 having an increased line width may increase a space of 20% or more than the storage node hole etched by the line width of the photoresist pattern.

As shown in FIG. 2E, the storage node 29 is formed along the surface in the storage node hole 28. The storage node 29 may be formed by forming a material for an electrode on the overall structure including the storage node hole 28 and then planarizing the target to expose the surface of the sacrificial layer 25A.

For example, the material for the electrode is aluminum (Al), copper (Cu), ruthenium (Ru), titanium (Ti), tantalum (Ta), tungsten (W), hafnium (Hf), zirconium (Zr), platinum (Pt) Using any one metal electrode selected from a group of metal electrodes such as iridium (Ir), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), hafnium nitride (HfN), and zirconium nitride (ZrN). The nitride electrode of any one selected from the group of nitride electrodes, such as) may be used. In addition, a metal electrode and an oxide electrode may be stacked, such as a ruthenium / ruthenium oxide film (Ru / RuO2), an iridium / iridium oxide film (Ir / IrO2), or may be formed of an oxide electrode such as a strontium ruthenium oxide film (SrUrO3). have. In addition, the metal may be formed of metal silicide such as cobalt silicide (CoSi2), titanium silicide (TiSi2), or the like, in which silicon is bonded to the metal.

Planarization can proceed with chemical mechanical polishing or etch back.

As described above, the storage node 29 may have a 20% or more space as shown in FIG. 2D to decrease the sheet resistance Rs by increasing the contact area with the storage node contact plug 23.

As shown in FIG. 2F, the sacrificial layer 25A (see FIG. 2E) is removed. The sacrificial layer can be removed by Dip Out. Deep out may be performed using a buffered oxide etchant (BOE) or an etching solution of Hf. In addition, it is possible to prevent the insulating film 22 from being attacked by the etching solution by the etching stop film 24A during the deep out.

Since the storage node 29 is formed in an increased space of 20% or more compared to the storage node holes etched by the line width of the photoresist pattern, the floor area is also increased to prevent the phenomenon of falling during deep out.

In a subsequent process, a dielectric layer and a plate node may be formed on the entire structure including the storage node 29 to form a capacitor. The capacitor can have a storage capacity increased by 10% or more than the comparative example, and can improve storage capacity and refresh. The increase in storage capacity will be described later in detail with reference to FIG. 4.

3A and 3B are layout photographs for comparing a comparative example with an embodiment of the present invention.

Referring to FIG. 3A, the area opened by the photoresist pattern may be confirmed. At this time, the open area may have an elliptical structure. The elliptical structure has different etching speeds between the relatively wide and narrow portions.

Accordingly, as shown in FIG. 3B, the relatively wide portion may have a fast etching speed, and the narrow portion may have an open area having a rectangular shape due to the slow etching speed.

When the open area has a rectangular shape, the rhombic aligned open areas are increased toward the edges rather than the sidewalls, thereby further preventing the bridge between the open areas.

4 is a graph for comparing the storage capacity of the comparative example and the embodiment of the present invention.

As shown in FIG. 4, the storage capacity Cs according to the comparative example and the embodiment of the present invention can be confirmed. The comparative example is a case of etching into an area opened by the photoresist pattern, and the embodiment of the present invention is a case of isotropic etching of a hard mask pattern which opens a wider line width than the photoresist pattern. Comparing the graph of the present invention with a comparative example, it can be seen that the storage capacity (Cs) is improved by 10%.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention;

2A to 2F are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention;

3A and 3B are layout photos for comparing a comparative example with an embodiment of the present invention;

Figure 4 is a graph for comparing the storage capacity of the comparative example and the embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

11 substrate 12 insulating film

13: hard mask layer 14: photoresist pattern

15: recess

Claims (15)

Forming an insulating film on the substrate; Forming a hard mask layer on the insulating film; Forming a photoresist pattern on the hard mask layer; Etching the hard mask layer by isotropic etching to form a hard mask pattern which opens a wider line width than the photoresist pattern; Selectively etching the hard mask pattern such that a sidewall of the hard mask pattern has an inclined profile; And Etching the insulating layer using the hard mask pattern as an etch barrier Method of manufacturing a semiconductor device comprising a. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, The isotropic etching is, A method of manufacturing a semiconductor device that proceeds in MERIE (Magnetically Enhanced Reactive Ion Beam Etching) equipment. Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1, The isotropic etching is a semiconductor device manufacturing method that proceeds in the absence of magnetic flux (Magnetic Flux) in the etching equipment. Claim 4 was abandoned when the registration fee was paid. The method of claim 1, The isotropic etching is performed by applying a bias power of 50W to 60W in the etching equipment, the pressure is applied to 35mTorr ~ 40mTorr. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1, The isotropic etching process is performed by maintaining the electrode (Electrode) temperature of the etching equipment to 60 ℃ ~ 80 ℃. Claim 6 was abandoned when the registration fee was paid. The method of claim 1, Selectively etching the hard mask pattern such that a sidewall of the hard mask pattern has an inclined profile, A method for manufacturing a semiconductor device by Ar sputtering.  Forming an insulating film interposed between the storage node contact plugs on the substrate; Forming a sacrificial layer on the insulating film; Forming a hard mask layer on the sacrificial layer; Forming a photoresist pattern on the hard mask layer; Etching the hard mask layer by isotropic etching to form a hard mask pattern which opens a wider line width than the photoresist pattern; Selectively etching the hard mask pattern such that a sidewall of the hard mask pattern has an inclined profile; Forming a storage node hole for opening the storage node contact plug by etching the sacrificial layer using the hard mask pattern as an etch barrier; And Forming a storage node connected to the storage node contact plug in the storage node hole; Capacitor manufacturing method of a semiconductor device comprising a. Claim 8 was abandoned when the registration fee was paid. The method of claim 7, wherein The isotropic etching is, A method for manufacturing a capacitor of a semiconductor device that proceeds in the equipment of MERIE (Magnetically Enhanced Reactive Ion Beam Etching). Claim 9 was abandoned upon payment of a set-up fee. The method of claim 7, wherein The isotropic etching is a capacitor manufacturing method of a semiconductor device that proceeds in the condition that there is no magnetic flux (Magnetic Flux) in the etching equipment. Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 7, wherein The isotropic etching is a capacitor manufacturing method of the semiconductor device proceeds by applying a bias power of 50W ~ 60W in the etching equipment, and applying a pressure of 35mTorr ~ 40mTorr. Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 7, wherein The isotropic etching is a capacitor manufacturing method of the semiconductor device to proceed by maintaining the electrode (Electrode) temperature of the etching equipment to 60 ℃ ~ 80 ℃. Claim 12 was abandoned upon payment of a registration fee. The method of claim 7, wherein The hard mask layer is a capacitor manufacturing method of a semiconductor device containing polysilicon. Claim 13 was abandoned upon payment of a registration fee. The method of claim 12, The isotropic etching is performed using a mixed gas of Cl ₂ , HBr and O ₂ , wherein Cl ₂ flows at a flow rate of 5 sccm to 10 sccm, and HBr flows at a flow rate of 150 sccm to 200 sccm. Claim 14 was abandoned when the registration fee was paid. The method of claim 7, wherein Selectively etching the hard mask pattern such that a sidewall of the hard mask pattern has an inclined profile, A method for manufacturing a capacitor of a semiconductor device by Ar sputtering. Claim 15 was abandoned upon payment of a registration fee. The method of claim 7, wherein After forming the storage node, And removing the sacrificial layer to form a cylindrical storage node.

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