翅濟部中央揉準局属工消费合作社印家 ____405227 B7___ 五、發明説明（1 ) 發明背景： —種複矽晶負載及其製法方法，尤其指一種應用於4T (4-transistor)靜態隨機存取記億體元件(SRAM Cell)中的複矽晶負載，以 及其製作的方法。： 按’在4T SRAM Cell中，一般多是使用高阻値的複砂晶線作爲 負載(load)。請參第一圖，傳統的複矽晶負載的作法，是先沉積—層 複矽晶層(polysilicon film)12，再以高能量離子，植入雜質(dopant)的 方式，來調整其阻値，雜質植入濃度越高，導電性越佳，阻値越 低。反之，植入濃度低，則阻値較高。經過雜質植入後，再對該複 矽晶層12進行微影、蝕刻，以得到所需的複砍晶線的圖案。接著， 對部份複矽晶線13，植入第二次的高濃度雜質(comiector· implantation)，使被値入的複砍晶線的阻抗下降，則，經過二次植入 的部份h‘，當作連接器(connector)使用，而其它的部份h，則當作4 載，例如第一圖所示。 在4T SRAM Cell小型化的過程中，遇到的阻礙之一，是傳統的 複砂晶負載的作法，在有限的空間內，無法獲得所需的高阻値，因 .而限制了記憶體元件的小型化，這在電路日趨密集的情況下，問題 尤待解決。 因此，本發明之目的之一，即在於提供一種複矽晶負載及其製作 方法，可以在不增加記憶體元件大小的情形下，大幅增加複砍晶負 載的長度，故阻抗値亦可大幅提高。 爲了達到上述發明目的，本發明必提供一種製作複矽晶負載的方 法，包括以下步驟：設一介電層，並於該介電層上’設一氧化層’ 並使用微影、蝕刻，將該氧化層，蝕刻出橫跨複砂晶負載方向的突 起。於該氧化層突起的側邊，設間隔物後，蝕去該氧化餍。於該間 n n I I 15 --I - n l ^ (請先閲讀背氣之注«Λ事項再填寫本頁) A7 A7 經濟部中央揉準局負工消費合作社印装 --405227--- 五、發明説明U ) 隔物上沉積一層複晶矽層，並對該複矽晶層進行第一次離子植入。 使用微影'蝕刻，定義該複矽晶層的圖案。再使用微影，將不需進 行第二次離子植入的部份，覆蓋光阻，進行第二次離子植入，以及 除去光阻。由於複p晶負載跨越了間隔物，使得複晶矽負載的長 度，得以在有限的銮間內增長，而得提高阻抗値。因此，使用本發 明可以改善polysilicon load對cell小型化的限制，使cell的大小，不 再受限於 polysilicon load。 發明槪要： 爲了達到前述目的，本發明所提供之製作複砍晶負載的方法’包 括以下步驟：首先設一下層元件，並在該下層元件的上方’設—介 電層。在該介電層上方，設置一氧化層，然後使用微影、蝕刻’將 該氧化層，蝕刻出橫跨複矽晶負載方向的突起。於該氧化層突起^ 側邊，設間隔物後，蝕去該氧化層。而後在該間隔物上沉積一層^ 晶矽層，並對該複矽晶層進行第一次離子植入，以調整該複晶矽層 的阻抗。再使用微影、蝕刻，定義出該複矽晶層的圖案。使用微 影，將不需進行第二次離子植入的部份，覆蓋光阻’再進行第二次 離子植入，以及除去光阻，而得到複砂晶負載。 由此說明可知，因爲複砂晶負載跨越了間隔物，使得複晶矽負載 的長度得以在有限的空間內增長，而得提高阻抗値° 以下藉由一實施例，說明本發明進一步之細節，以及本發明之其 它特點。 圖式簡單說明： 第一圖爲習知複砂晶負載的示意圖。_ 第二圖爲本發明實施例中製程一步驟^不意圖 第三圖爲上述實施例製程進一步驟的示？圖 第四圖爲第三圖實施例製程進一步驟的示意圖 本紙張尺度適用中困國家標準（CNS )八4规格（210X297公瘦） ----------裝-----Ί訂-------銶 I - * (請先閱讀背面之注意事項再填寫本頁) 經濟部中央搮準扃貞工消费合作社印家 --β7_ 五、發明説明（3 ) 第五圖爲第四圖實施例製程進一步驟的示意圖 第六圖爲第五圖實施例製程進一步驟的示意圖 第七圖爲第六圖實施例製程進一步驟的示意圖 第八圖爲第七圖實施例製程進一步驟的示意圖 發明說明： 請參第二圖，設一下層元件21，該下層元件21，可以是基板， 或是電路上的任何一層，例如，氧化層、是複晶砍層或其它任何 材料層。在該下層元件的上方，設製一介電層22( interpoly dielectric ;IPD)，例如，未攙雜雜質的原矽酸四乙酯(undoped TEOS; Tetra-Ethy-Ortho-Silicate)，其厚度可爲 2000~5000 埃(A)〇 請參第三圖，在該介電層22上，再沉積一層攙雜質的氧化層 23 ’例如擒雜硼碟的原矽酸四乙酯(BP-TEOS) ’設其厚度爲d，範圃 在500〜2000埃。而此d値，係由電路的需求來決定》接著使用微 影、蝕刻，將此攙雜質的氧化層，蝕刻出橫跨複政晶負載方向的突 起23。 請參第四圖，沉積一層未擒雜質的原矽酸四乙酯（圖上未示）， 進行回蝕刻(Etching Back)，則在突起23的側邊，會形成一對間隔物 24、25(SpaCer)橫跨複砍晶負載方向。 請參第五圖，利用選擇性蝕刻，例如Vapor HF選擇性蝕刻，將 讎質氧化層23蝕去，則間隔物24、25會留在Wafer表面上。 請參第六圖，接下來的製程，與一般習知製作複砂晶負載的製程 相同。在本實施例中，先以微影、蝕刻，做出介窗(poly via)27。 請參第七圖，再沉積一層複晶矽層29 ,並對此複砂晶層29進行 第一次離子植入，以調整其阻抗。 本纸At尺度適用t國國家梯準（CNS ) Α4洗格（210X297公釐） -----------裴------Γΐτ (請先閲讀背面之注意I事項再填寫本頁) --405837--- 五、發明説明（4·) 請參第八圖，使用微影、蝕刻，作出複矽晶層30的圖案，然後 再一次，使用微影，將不需進行第二次離子植入的部份，覆蓋光阻 (圖上未示），接著進行第二次離子植入，用以降低當作連結器31的 阻値》 , 最後將光阻除去，即可獲得高電阻値的複矽晶負載30。 由以上的說明可知，因爲複矽晶負載30跨越了間隔物24、 25，使得複晶矽負載30的長度得以在有限的空間內增長，而得提高 阻抗値。 而對於習於此項技藝之人士而言，當可少許修改，而不脫離本發 明之精神。例如，將製作間隔物的材料，_由未攙雜質的原矽酸四乙 酯，改用如氮化矽材料，惟此等變化，屬於習於此項技藝之人士所 易於推及者，當仍在本發明的保護範圍之內。本發明的保護範圍： 應當以申請專利範圍所載爲準》 : 产. ;-ir—-----^ (請先聞讀背面之注t-事項再填寫本頁) 經濟部中央樑率局負工消费合作社印裂 本紙似埴用 ( CNS ) Α4ΛίΓ( 210X297^*7The central government of the Ministry of Economic Affairs of the Ministry of Industry and Commerce of India, ____405227 B7___ V. Description of the invention (1) Background of the invention:-A complex silicon crystal load and its manufacturing method, especially a 4T (4-transistor) static random Access to a complex silicon crystal load in a SRAM cell and a method for making the same. : In the 4T SRAM Cell, generally, a high-resistance chirped composite sand crystal line is generally used as a load. Please refer to the first figure. The traditional method of loading polysilicon is to deposit polysilicon film 12 first, and then adjust its resistance by implanting impurities (dopant) with high energy ions. The higher the impurity implantation concentration, the better the conductivity and the lower the resistance. Conversely, a low implantation concentration results in a high resistance. After the implantation of impurities, the complex silicon crystal layer 12 is lithographed and etched to obtain the desired pattern of the polycrystalline silicon lines. Next, a second high concentration impurity (comiector implantation) is implanted into a part of the complex silicon crystal line 13 to reduce the impedance of the inserted polycrystalline line. ', Used as a connector, and the other parts h are used as 4 loads, as shown in the first figure. One of the obstacles encountered during the miniaturization of 4T SRAM Cells is the traditional method of loading sand crystals. In a limited space, the required high resistance can not be obtained, which limits the memory components. The miniaturization of the circuit is especially problematic in the case of increasingly dense circuits. Therefore, one of the objectives of the present invention is to provide a complex silicon crystal load and a manufacturing method thereof, which can greatly increase the length of the complex crystal load without increasing the size of the memory element, so the impedance 値 can also be greatly improved. . In order to achieve the above-mentioned object of the present invention, the present invention must provide a method for making a complex silicon load, which includes the following steps: a dielectric layer is provided, and an oxide layer is provided on the dielectric layer; This oxide layer etched a protrusion across the direction of loading of the sand crystal. After the spacer is provided on the side of the protrusion of the oxide layer, the hafnium oxide is etched away. In this room nn II 15 --I-nl ^ (Please read the note of anger «Λ before filling out this page) A7 A7 Printed by the Central Consumers’ Bureau of the Ministry of Economic Affairs, Consumer Cooperatives --405227 --- V. Description of the invention: A) A polycrystalline silicon layer is deposited on the spacer, and the first polyimide silicon layer is ion implanted. Lithography is used to define the pattern of the polysilicon layer. The lithography is then used to cover the part that does not require the second ion implantation, cover the photoresist, perform the second ion implantation, and remove the photoresist. Since the p-crystal load crosses the spacer, the length of the poly-silicon load can be increased within a limited range, and the impedance 値 must be increased. Therefore, using the present invention can improve the limitation of the miniaturization of the polysilicon load on the cell, so that the size of the cell is no longer limited by the polysilicon load. Summary of the invention: In order to achieve the foregoing object, the method for making a multi-cut crystal load provided by the present invention 'includes the following steps: firstly, a layer element is provided, and a dielectric layer is provided above the lower layer element. An oxide layer is provided above the dielectric layer, and then the oxide layer is etched by lithography, etching 'to protrude across the load direction of the complex silicon crystal. A spacer is disposed on the side of the oxide layer, and the oxide layer is etched away. A crystalline silicon layer is then deposited on the spacer, and the complex silicon layer is first ion-implanted to adjust the impedance of the complex silicon layer. Then use lithography and etching to define the pattern of the complex silicon crystal layer. Using lithography, the part that does not require the second ion implantation is covered with photoresist 'and then the second ion implantation is performed, and the photoresist is removed to obtain a composite sand crystal load. From this explanation, it can be known that because the load of the composite sand crystal crosses the spacer, the length of the load of the composite silicon silicon can be increased in a limited space, and the impedance must be increased. Below, an embodiment will be used to explain further details of the present invention. And other features of the invention. Brief description of the diagram: The first diagram is a schematic diagram of a conventional compound sand crystal load. _ The second diagram is a step of the manufacturing process in the embodiment of the present invention ^ Not intended The third diagram is a further step of the manufacturing process of the above embodiment? The fourth figure is a schematic diagram of the further steps in the embodiment of the third figure. The paper size is applicable to the National Standard for Medium and Difficulties (CNS) 8-4 specifications (210X297 male thin). ΊOrder ------- 銶 I-* (Please read the notes on the back before filling this page) Central Government of the Ministry of Economic Affairs, Zhunzhen Zhengong Consumer Cooperative Press-β7_ V. Invention Description (3) Fifth The figure is a schematic diagram of the further process in the fourth embodiment. The sixth diagram is a schematic diagram of the further process in the fifth embodiment. The seventh diagram is a schematic diagram of the further process in the sixth embodiment. The eighth diagram is the seventh embodiment. A further schematic illustration of the invention: Please refer to the second figure, and set up a lower layer element 21, which can be a substrate or any layer on the circuit, such as an oxide layer, a polycrystalline layer or any other material Floor. Above the lower layer device, a dielectric layer 22 (interpoly dielectric; IPD) is provided, for example, undoped TEOS (Tetra-Ethy-Ortho-Silicate), which is not doped with impurities, and the thickness may be 2000 ~ 5000 Angstroms (A). Please refer to the third figure. On the dielectric layer 22, an additional oxide layer 23 of plutonium impurities is deposited, such as tetraethyl orthosilicate (BP-TEOS) doped with boron disks. Suppose its thickness is d, and the fan garden is between 500 and 2000 angstroms. This d 値 is determined by the requirements of the circuit. ”Then, using lithography and etching, the oxide layer of this 搀 impurity is etched to form a protrusion 23 across the load direction of the crystal. Please refer to the fourth figure, deposit a layer of tetraethyl orthosilicate (not shown in the figure) without impurities, and perform etch back (Etching Back), a pair of spacers 24, 25 will be formed on the side of the protrusion 23 (SpaCer) Across the load direction of the multi-cut crystal. Please refer to the fifth figure. Using selective etching, such as Vapor HF selective etching, to remove the hafnium oxide layer 23, the spacers 24 and 25 will remain on the Wafer surface. Please refer to the sixth figure. The next process is the same as the conventional process for making sand crystal load. In this embodiment, first, lithography and etching are performed to form a poly via 27. Please refer to the seventh figure, and deposit a layer of polycrystalline silicon layer 29, and perform the first ion implantation on the polycrystalline silicon layer 29 to adjust its impedance. At size of this paper is applicable to National Standards of China (CNS) Α4 Washing (210X297 mm) ----------- Pei ------ Γΐτ (Please read the precautions on the back before reading I (Fill in this page) --405837 --- 5. Description of the invention (4 ·) Please refer to the eighth figure, use lithography and etching to make a pattern of the polysilicon layer 30, and then use lithography again. The second ion implantation is performed to cover the photoresist (not shown in the figure), and then the second ion implantation is performed to reduce the resistance of the connector 31. Finally, the photoresist is removed, that is, A high-resistance chirped polysilicon load 30 is obtained. As can be seen from the above description, since the polysilicon load 30 crosses the spacers 24 and 25, the length of the polysilicon load 30 can be increased in a limited space, and the impedance 値 must be increased. For those who are accustomed to this skill, it should be slightly modified without departing from the spirit of the present invention. For example, the material used to make the spacer will be changed from tetraethyl orthosilicate without impurities to materials such as silicon nitride. However, these changes are easily accessible to those skilled in the art. It is still within the protection scope of the present invention. The scope of protection of the present invention: It shall be subject to the scope of application for patents: "." Printed paper-like paper used by bureau-consumer cooperatives (CNS) Α4ΛίΓ (210X297 ^ * 7