經濟部中央標率局貝工消费合作社印製 A 7 B7 五、發明説明（） t明領递： 本發明係與一種半導體製程有關，特別是有關於一種 4除埋入式接觸之溝渠缺陷（buried contact trench)的方 法’可應用於如形成靜態隨機存取記憶體（static random access memory; SRAM)等的製程之中。 螢明背景： 自從第一個積體電路於西元I960年首先發明以來，半 導體製程中單一晶片上的元件數目，即以爆炸性的速度快 速成長’隨著現階段的半導體製程技術已邁入極大型積艘 電路（ultra large scale integration; ULSI)、甚至更高密度的 時代，單一晶片上的元件數目也由以往的數千個元件，增 加至數百萬個元件’甚至可達到單一晶片上製作數千萬或 是更多個元件的密度》 單一晶片上元件數目的大幅增加，形成對半導體製程 技術的一大挑戰，每一個半導體元件皆必須在不影響其功 能的前提下，進一步縮減其尺寸或占用的面積，而在更高 的積集度（packing density)之下，整體元件或電路仍須維持 不變、甚至必須具有更好的可靠度、工作壽命、以及低功 率消耗及低發熱率的特性。因此半導體製程中的四大製程 技術，也就是包含微影、蝕刻、薄膜、及擴散的製程技術， 必須同時的研究與發展，以達成下一代積體電路的發展目 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐〉 ----U---裝------訂------ /\ (請先閱讀背面之注意事項再填寫本頁) 經濟部中央揉準局貝工消费合作社印製 A7 B7 五、發明説明（） 標。 在記憶想元件的應用之中，靜態隨機存取記挽鱧 (SRAM)具有能將電位狀態長時間鎖定的特性，而能在電源 的持續供應下穩定維持所寫入的狀態，在記憶裝置的應用 上具有相當重要的角色。一般而言，靜態隨機存取記憶想 的記憶胞是由雙穩態的正反器（bistable filp-fiops)所组 成’此正反器可由數個電晶雄所構成’因此一個靜態隨機 存取的記憶胞所使用的元件或是電晶體數目，會較傳統使 用一個電晶體及一個電容器的動態隨機存取記憶禮 (dynamic random access memory; DRAM)為多，也因此使用 更多的晶片面積’使晶片上的積集度成為形成靜態隨機存 取記憶體陣列的重要考量及要求之一，以增加單一晶片上 所容納的記憶胞數目。 埋入式接觸的技術，是用以增加元件積集度的有效方 法之一，利用形成如多晶矽或氮化鈦等的導II層，可做為 元件間的區域性内連線（local interconnect)之用，以更有效 的利用晶片面積。在美國專利第4,701，423號中，N. J. Szluk 提出了自行對準的互補式金氧半（complementary metal oxide semiconductor; CMOS)電晶體的製程，並表示埋入式 接觸、或是自行對準的埋入式接觸，是用以提昇元件效能 及元件密度的有效方法之一’然而在實際製程的應用上， 要合併應用埋入式接觸及其他如輕推雜没極（lightly doped drain; LDD)、閘極電極摻雜及自行對準式接觸的技術，會 本紙張尺度適用中國國家榇準（CNS ) A4規格（210X297公釐） ----l·|_裝------訂------G (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消费合作社印裝 A7 B7 五、發明説明（） ， 有相當的困難，而導致其製程步驟較為繁複，生產的良率 也會下降。 Μ. H. E-Downy等人於美國專利第5,082,796號中，揭 露有關利用多晶矽層以形成區域性内連線的技術，應用於 具有金氧半電晶體或雙接面電晶體製程中的方法，並強調 由於在晶圓上單一區域内所能形成之金屬層數目有其上 限’因此藉由多晶矽層做為區域性内連線層，可使原來用 以形成區域性内連線的金屬層，轉而做為形成全面性的連 線（global connect)之用’並可由於元件雜散區域的減少而 增加電晶體的效能。 埋入式接觸可用以提供各交互連接之電晶體之閘極、 汲極間之連接，然而傳統的埋入式接觸製程，會由於蝕刻 時對基材的侵害，而於埋入式接觸區域内形成溝渠的缺 陷，而影蜜或阻斷元件間的電流，導致元件效能降低或受 損等的問題。 在美國專利第5,686,336中，J.T.Lee提出生產四個電 晶體之靜態隨機存取記憶體的方法，其中並說明由於撖影 製程中對準誤差的問題，會導致光軍的位置有偏移的現 象，使基材上的埋入式接觸區因而外露，而在多晶矽層定 義時過度蝕刻的影举下，埋入式接觸區内的部分區域會被 蝕刻而形成溝渠，迫使電流需導向摻雜濃度較低的區域’ 因而導致埋入式接觸的電阻大幅增加，使元件的效能下 降，此發明中並提出利用額外的離子植入製程來解決電阻 本紙張尺度適用中國國家橾準（CNS ) A4规格（210X297公釐） -----:---------tT------^-u (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局負工消费合作社印製 A7 B7 五、發明説明（） 增加的問題。 T. T. Chang等人於美國專利第5,580,806號中，亦揭 露有關應用埋入式接觸於靜態隨機存取記憶體的方法，於 使用金氧半電晶體之記憶胞中，會使用兩個負載電晶體及 兩個交互連接之金氧半電晶體，埋入式接觸用以提供交互 連接之金氧半電晶想之閘極、汲極間之連接，其中並介紹 了傳統製程中溝渠缺陷形成的問題，而使得其電阻因摻雜 濃度的減少而增加。 K.H. Lee及C.-H. D. Yu所獲的美國專利第5,654,240 中，介紹形成接觸開口之精艘電路製造及光阻層對準誤差 所導致的接面溝渠缺陷問題。溝渠缺陷會影響接面處的效 能，在較嚴重的狀況下，會完全穿過接面區。此專利中提 出以氧化層罩幕定義矽化金屬層，以提供多晶矽區域間之 電性連接’來避免溝渠缺陷的風險及影響之方法。 在美國專利第5,705,437號中，Y.H. Wu等人提出傳统 製程中的溝渠缺陷問題，未摻雜的溝渠缺陷會導致如電阻 增加或是漏電等的問題，而若需解決溝渠缺陷問題，往往 需使用複雜的步驟，增加製程的負擔及成本。 因此，目前需要以更簡化的製程步驟，來消除溝渠的 產生，以形成無溝渠缺陷的埋入式接觸。 務明目的及概述： 本發明的目的為提供一種形成埋入式接觸的方法。 本紙張尺度逋用中國國家標準（CNS ) Α4規格（2ΐ〇χ297公釐） -----!—c,✓•裝------訂------'υ (請先閱讀背面之注意事項再填寫本頁) A7 B7 經濟部中央標準局貝工消费合作社印褽 五、發明说明（ 本發明的另—目的為提供/種埋入式接觸的形成方 法，可消除溝渠缺陷之形成。 本發明的再〜目的為提供—種消除埋入式接觸之溝渠 缺陷的方法’以簡化形成靜態随機存取記憶艎所需的製程 步驟。 本發明的再一目的為提供一種形成埋入式接斶的方 法’可提高元件的積集度。 本發明中形成埋入式接觸於半導體基材之方法，可包 含以下步驟：首先形成一閘極絕緣層於基材上；並形成一 第一碎層於閉極％緣層上；再定義一埋入式接觸開口於第 一梦層及閘極絕緣層内，並延伸至基材上；接著摻雜基材 位於埋入式接觸開口下方之區域，以形成一埋入式接觸 區。 接著形成一第二矽層於基材及第一矽層之上；並去除 部分之第二矽層以定義一閘極區域及一内連線；再摻雜基 材’以形成一第二摻雜區於基材内未被閘極區域及内連線 復蓋之區域；《後進行一熱氧化製程，以氧化第一矽層外 露之部分及第二矽層之表面區域；再形成側壁結構於閘極 區域及内連線之側壁上；最後並摻雜基材，以形成一第三 摻雜區於第二摻雜區内未被側壁結構覆蓋之區域。 除了由埋入式接觸形成的連線之外，並可加入後續的 製程，以形成全面性的導艘連線。可先形成一介電層於基 材上；再進行-熱製程；並進行一金屬化製程以形成連 本紙張尺度逋用中國國家標準（CNS ) Λ4規格(210X297公釐)— , ) r !γ -----：----------,1T------c (請先閲讀背面之注意事項再填寫本頁) A7 B7 -----:----------訂------ (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消费合作社印製 五、發明説明（） 線。 圈式簡單說明： 第 一 圖 顯 示 本 發明 層 於 基 材上 第 -— 圖 顯 示 本 發明 成 一 埋 入式 第 三 圖 顯 示 本 發明 —Λ 矽 層 上之 第 四 圖 .顯 示 本 發明 '— 閘 極 區域 一 第 二 摻雜 第 五 圖 顯 示 本 發明 — 矽 層 外露 之 截 面 示意 第 六 圊 顯 示 本 發明 内 連 線 之側 第 七 圊 顯 示 本 發明 區 於 第 二摻 第 八 圖 顯 示 本 發明 一 熱 製 程後 第 九 圖 顯 示 本 發明 之 截 面 示意 中形成一閘極絕緣層及第一矽 之截面示意圓。 中定義一埋入式接觸開口及形 接觸區之截面示意圖。 中形成一第二矽層於基材及第 截面示意圖。 中去除部分之第二矽層以定義 及一内連線，並摻雜基材以形成 區之截面示意圖。 中進行一熱氧化製程，以氧化第 之部分及第二矽層之表面區域 圖。 中形成側壁結構'於閘極區域及 壁上的截面示意圖。 中摻雜基材，以形成一第三摻雜 雜區内之截面示意圖。 形成一介電層於基材上並進行 之截面示意圖。 進行一金屬化製程以形成連線 圖。 本紙張尺度適用中國國家梂準（CNS ) A4規格（210X297公釐） Μ Β7 經濟部中央樣準局員工消費合作社印製 五、發明説明（） 發明詳細說明： 本發明中提供一種形成埋入式接觸的方法，可消除溝 渠缺陷之形成並可簡化傳統製程中解決溝渠缺陷問題的 繁複步驟’利用-第一矽層的形纟，可避免定義埋入式接 觸開口時’光阻層的污染問題，並提高蝕刻製程的寬容度’ 而藉由應用本發明的方法於形成靜態隨機存取記憶級的製 程中’可提高元件的積集度。 參見第一圖所示，首先提供一基材10，一般最常見的 材料是矽材質、晶向為<100>之半導體基材，亦可使用其他 材質或晶向的半導體材料。基材10上方並有做為隔離區域 的場氧化層12形成於其上，以隔離基材1〇上方的各個元 件’隔離區域亦可使用其他的隔離製程來形成，如溝渠隔 離等。以場氧化隔離區域12而言，一般常應用的形成方式， 係以氧化層及氣化層將不須氧化的區域復蓋之後，使基材 10於含氣環境中將其部分區域加熱氧化成長，而形成場氟 化隔離區域1 2 » 接著形成一閘極絕緣層14於基材上，閘極絕緣層14 於本例中使用一氧化層，氧化層係由基材1〇加熱氡化成長 而成’其厚度可為50埃（angstroms)至400埃之間。之後形 成一第一矽層16於閘極絕緣層14上，第一矽層16可做為 基材1〇與後續的光阻層間的緩衝層或保護層，以避免光阻 材質對基材10所造成的污染問題，第一矽廣16可使用一 8 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） I — I I L/ν 裝— I i I 訂 n I n 1 I (請先閱讀背面之注意事項再填寫本頁) 經濟部中央揉準局貝工消费合作社印製 A7 B7 五、發明説明（） 未換雜之多晶矽層，此多晶矽層可以化學氣相沈積法 (chemical vapor deposition; CVD)或是低壓化學氣相沈積法 (low pressure CVD; LPCVD)形成’以本實施例而言，第一 珍層16的厚度約為1〇奈米（nan〇ineter)至5〇奈米之間。 參見第二圖所示，定義一埋入式接觸開口 2〇於第一矽 層16及閘極絕緣層14内，埋入式接觸開口 2〇並延伸至基 材10表面處。埋入式接觸開口 2〇的定義方法，可使用一 圊案化製程’先形成一光阻層18於第一矽層16之上，並 以微影製程將光罩上的圈案轉移至光阻層18，加以顯影之 後’再以光阻層18為罩幕’進行一非等向性飪刻的製程， 本例中可利用反應性離子姓刻（reactive i〇I1 etching; RIE)的 方式’來去除部分之第一矽層16及閘極絕緣層14,以定義 埋入式接觸開口 20，同時藉由第一矽層16的保護，可避免 基材10受到光阻層18的污染。 接著摻雜基材10’以形成一埋入式接觸區22、位於埋 入式接觸開口 20下方之基材10内，埋入式接觸區22即為 一利用摻雜以降低其阻值而成為導電性較高的區域，因此· 可以植入含磷或含砷離子的方式來形成，植入時可以光阻 層18及場氧化層12為革幕，植入之能量約為1〇 KeV至 100 KeV 之間’剤量約為 5E14 atoms/cm2 至 5E16 atoms/cm2 之間。 之後形成一第二矽層24於基材1〇及第一矽層16的上 方，如第二圏所示，同樣的，第二梦層24可使用一未摻雜 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨OX297公釐） ----^——------1T-----」w (請先閲讀背面之注意事項再填寫本頁) A7 B7 五、發明説明（） 之多晶梦層’此多晶矽層可以化學氣相沈積法（CVD)或是低 壓化學氣相沈積法（LPCVD)形成，本例中第二梦層之厚度約 為500埃至3,000埃之間》 參見第四圈所示，接著去除部分之第二矽層24以定義 一閘極區域24a及一内連線24b，閘極區域24a及内連線 24b之定義，同樣可使用包含微影製程及蝕刻製程的圓案化 製程’其細節即不多做介紹》藉由對第二矽層24的定義， 會在閘極區域24a及内連線24b之間形成一用以摻雜低摻 雜接面區的開口 26，一般而言，第一矽層16及第二矽層 24之間，會於製程進行的過程時形成一自然長成的薄氧化 層，而在蝕刻開口 26時，蝕刻製程即可藉由偵測蝕刻進行 至此氧化層的方式’來產生良好的控制，而不會有過度姓 刻的情形’而即使有稍微過度蝕刻的狀況發生，基材1〇仍 能藉由第一矽層16的保護來避免蝕刻的傷害’因此蝕刻製 程的製程寬容度可大幅提高。 經濟部中央標準局貝工消費合作社印製 -----:——c裝 (請先聞讀背面之注意事項再填寫本頁) 在定義開口 26時’可於開口 26與埋入式接觸區22的 位置之間保留一安全距離28，在¥例中，安全距離28的寬 度可設定在數百埃的範圍之内，藉由此一距離的存在，可 減少製程受到對準誤差所導致的圊案偏移的影響，而使製 程對於微影製程的寬容度增加，因而可避免傳統製程中的 溝渠缺陷問題。 參見第五圖所示，接著摻雜基材1〇，以形成一第二捧 雜區30於基材内未被閘極區域24a及内連線24b復蓋之區 10 本纸張尺度適用中國國家梯準{ CNS > A4規格（210X297公羡） A7 經濟部中央梯準局負工消费合作社印製 B7五、發明説明（） ~ 域"第二摻雜區30為一摻雜劑量較低的區域，用以形成電 晶髖的低摻雜汲極（LDD)及源極的結構，因此可藉由離子植 入方式，透過厚度極薄的第一矽層16植入含磷或含砰的離 子’搲入之能f約為10 KeV至80 KeV之間，劑量約為 5E12atoms/cm2 至 5E14atoms/cm2 之 Γ·1。 之後進行一熱氧化製程’以氧化第一矽層16外露之部 分’也就是其於開口 26下方的部分，並同時氧化第二矽層 24，也就是閘極區域24a及内連線24b的表面區域，利用 高溫的氧化製程，可形成氧化層32，本例中氧化製程的溫 度可約為750 °C至11501之間，而埋入式接觸區22及第二 換雜區30内的離子’會在高溫下擴散並活化，而使埋入式 接觸區22及第二掺雜區3〇間因擴散形成良好的電性連 接’同時並可消除閘極區域24a及内連線24b處於蝕刻時 所產生的缺陷。 參見第六圖所示，接著形成側壁結構34於閘極區域24a 及内連線24b之侧壁上，在本實施例中，側壁結構34可為 氧化層間隊壁，氧化層間陈壁可由沈積並回蝕一氧化層來 形成’同時由於氧化層間隙壁的回蝕製程，大部分的氧化 層32會被去除，僅留下一部分於側壁結構34的氧化層材 質中。 接著摻雜基材10,以形成一第三摻雜區36於第二摻雜 區30内未被側壁結搆34復蓋之區域，如第七圈所示，在 摻雜的同時，閘極區域24a及内連線24b處的矽材質也會 本紙張尺度適用中國國家橾準（CNS ) A4規格（210X297公瘦） (請先閲讀背面之注意事項再填寫本頁) ~裝. 訂 C· 經濟部中央標率局貝工消费合作社印製 A7 B7 五、發明説明（） 受到掺雜’而降低其阻值。第三摻雜區36為一換雜劑量較 高的區域，用以做為電晶艘的源汲極接面區’因此可以側 壁結構34為罩幕，利用離子植入方式植入含磷或含砷的離 子，植入之能量約為10 KeV至100 KeV之間’劑量約為 5E14 atoms/cm2 至 5E16 atoms/cm2 之間。利用以上步 驟，可形成一具有埋入式接觸的高效能、高積集度的電晶 艎結構，以應用於如靜態記憶體等的製程之中。 除了由埋入式接觸形成的連線之外，並可加入後續的 製程，以形成全面性的導體連線。首先可形成一介電層38 於基材10上，如第八圈所示，本例中介電層可使用如硼磷 梦玻璃（13〇1>0卩11〇3卩11〇3丨1丨0汪16;6?8〇)，棚構梦玻填可以一般 的化學氣相沈積方式形成，亦可使用以TEOS(tetra-ethyl-ortho-silicate)為反應氣II的化學氣相沈精過程，並加入含 硼或含磷之氣體，以沈積由 TEOS形成之硼磷矽玻璃（BP-TEOS)。接著並進行一熱製程，以使介電層38的表面因熱 流動而得到較佳的平坦度，並同時擴散及活化第三摻雜區 36中的離子，而使埋入式接觸區22舆接面區3¾及38間形 成良好的連接，並透過内連線24b形成舆其他區域間的連 線’而能有效避免傳統製程中溝渠缺陷的問題，提昇製程 的元件良率。接著並進行一金屬化製程以形成連線4〇，並 可進一步進行多次的金屬化製程來形成更多層的連線。 本發明以一較佳實施例說明如上，僅用於藉以幫助了 解本發明之實施，非用以限定本發明之精神，而熟悉此領 本纸張尺度適用中國困家梯準（CNS ) A4規格（210X297公釐） -----^---------ίτ------c (請先閱讀背面之注意事項再填寫本頁) A7 B7 五、發明説明（） 域技藝者於領悟本發明之精神後，在不脫離本發明之精神 範圍内，當可作些許更動潤飾及等同之變化替換，其專利 保護範圍當視後附之申請專利範圍及其等同領域而定。 --------^裝------訂------ο (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消费合作社印製 本紙張尺度逋用中國國家標準（CNS ) A4規格（210X297公釐）Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, printed A 7 B7 V. Description of the invention () Delivery: The present invention is related to a semiconductor process, and in particular, it relates to a trench defect of 4 removal buried contacts ( The method of "buried contact trench" can be applied to processes such as forming a static random access memory (SRAM). Fluorescent background: Since the first integrated circuit was first invented in I960, the number of components on a single wafer in the semiconductor process has grown rapidly at an explosive rate. With the current stage of semiconductor process technology, it has entered a very large scale. In the era of ultra large scale integration (ULSI) and even higher density, the number of components on a single chip has increased from thousands of components in the past to millions of components. Density of ten million or more components "The large increase in the number of components on a single wafer poses a major challenge to semiconductor process technology. Each semiconductor component must be further reduced in size or without affecting its function. The area occupied, and under a higher packing density, the overall component or circuit must still remain the same, and it must even have better reliability, working life, and low power consumption and low heating rate. characteristic. Therefore, the four major process technologies in the semiconductor process, that is, the lithography, etching, thin film, and diffusion process technologies, must be researched and developed simultaneously to achieve the development goals of the next-generation integrated circuit. The paper standards are applicable to Chinese national standards. (CNS) A4 specification (210X297 mm) ---- U --- installation ------ order ------ / \ (Please read the precautions on the back before filling this page) Central Ministry of Economic Affairs Printed on A7 B7 by Zhunzhu Bureau Consumer Cooperative V. Description of invention () In the application of memory devices, static random access memory (SRAM) has the characteristics of being able to lock the potential state for a long time, and It can stably maintain the written state under the continuous power supply, and plays a very important role in the application of memory devices. Generally speaking, the memory cell of static random access memory is a bistable flip-flop ( bistable filp-fiops) is composed of 'the flip-flop can be composed of several crystal males'. Therefore, the number of components or transistors used in a static random access memory cell will be larger than that of a traditional transistor and capacitor. Dynamic There are many dynamic random access memory (DRAM), and therefore more chip area is used 'to make the accumulation on the chip one of the important considerations and requirements for forming a static random access memory array. Increase the number of memory cells contained on a single chip. Buried contact technology is one of the effective methods to increase the degree of component accumulation. It can be used as a device by forming a conductive II layer such as polycrystalline silicon or titanium nitride. Local interconnects are used to more effectively use the chip area. In US Patent No. 4,701,423, NJ Szluk proposed a self-aligned complementary metal oxide semiconductor ; CMOS) transistor manufacturing process, and indicates that buried contacts, or self-aligned buried contacts, is one of the effective methods to improve component performance and component density. However, in the actual process application, it is necessary to Combined application of buried contact and other technologies such as lightly doped drain (LDD), gate electrode doping, and self-aligned contact. Applicable to China National Standard (CNS) A4 specification (210X297mm) ---- l · | _installation ------ order ------ G (Please read the precautions on the back before filling this page ) Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives, printed A7 B7 5. The description of the invention () has considerable difficulties, which leads to more complicated process steps and lower production yields. Μ. H. E-Downy et al. In U.S. Patent No. 5,082,796, the method of using polycrystalline silicon layers to form regional interconnects was disclosed and applied to the process with metal-oxide-semiconductor or double-junction transistors, and emphasized that There is an upper limit to the number of metal layers that can be formed in a single region. Therefore, by using a polycrystalline silicon layer as a regional interconnect layer, the metal layer that was originally used to form the regional interconnect can be turned into a comprehensive one. The use of global connection can increase the performance of the transistor due to the reduction of the stray area of the component. The buried contact can be used to provide the connection between the gate and the drain of the transistor. However, the traditional buried contact process will be in the buried contact area due to the damage to the substrate during etching. Defects in the formation of trenches, and shadow honey or block currents between components, leading to problems such as reduced or damaged component performance. In U.S. Patent No. 5,686,336, JTLee proposed a method for producing static random access memory of four transistors. It also explained that due to the alignment error in the shadow process, the position of the optical army would be shifted. So that the buried contact area on the substrate is exposed, and under the influence of over-etching during the definition of the polycrystalline silicon layer, a part of the buried contact area will be etched to form a trench, forcing the current to be directed to the doping concentration. The lower area 'therefore leads to a substantial increase in the resistance of the buried contact, which reduces the efficiency of the component. In this invention, it is proposed to use an additional ion implantation process to solve the resistance. This paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -----: --------- tT ------ ^-u (Please read the precautions on the back before filling out this page) Ministry of Economic Affairs Central Standards Bureau Printed by Consumer Cooperatives A7 B7 V. Description of Invention () Increased issues. TT Chang et al., In U.S. Patent No. 5,580,806, also discloses a method for applying embedded contact to static random access memory. In a memory cell using a metal-oxide semiconductor transistor, two load transistors and Two interconnected metal-oxide-semiconductor crystals are embedded to provide the connection between the gate and the drain of the metal-oxide-semiconductor crystals that are connected to each other. It also introduces the problem of the formation of trench defects in the traditional process. As a result, its resistance increases due to the decrease in doping concentration. K.H. Lee and C.-H. D. Yu's US Patent No. 5,654,240 introduces the problem of junction trench defects caused by the fabrication of precision circuits for forming contact openings and the alignment error of photoresist layers. Ditch defects will affect the performance at the junction, and in more severe cases, it will completely penetrate the junction area. This patent proposes a method of defining a silicided metal layer with an oxide mask to provide an electrical connection between polycrystalline silicon regions' to avoid the risks and effects of trench defects. In U.S. Patent No. 5,705,437, YH Wu et al. Proposed the problem of trench defects in the traditional process. Undoped trench defects can cause problems such as increased resistance or leakage. To solve the problem of trench defects, it is often necessary to use Complex steps increase the burden and cost of the process. Therefore, there is a need for more simplified process steps to eliminate trenches in order to form buried contacts without trench defects. Clear Purpose and Summary: An object of the present invention is to provide a method for forming a buried contact. This paper uses China National Standard (CNS) Α4 size (2ΐ〇χ297mm) -----! — C, ✓ • Installation ------ Order ------ 'υ (please first Read the notes on the back and fill in this page again) A7 B7 Seal of the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention The purpose of the present invention is to provide a method for eliminating the defects of buried contact trenches to simplify the process steps required to form a static random access memory. Another object of the present invention is to provide a formation The method of buried connection can increase the accumulation degree of the device. The method for forming a buried contact with a semiconductor substrate in the present invention may include the following steps: firstly forming a gate insulating layer on the substrate; and forming A first broken layer is on the closed electrode edge layer; a buried contact opening is defined in the first dream layer and the gate insulating layer, and extends to the substrate; then the doped substrate is located on the buried contact The area under the opening to form a buried contact area. Forming a second silicon layer on the substrate and the first silicon layer; removing a portion of the second silicon layer to define a gate region and an interconnect; and re-doping the substrate 'to form a second doping Area in the substrate that is not covered by the gate area and interconnects; "Later, a thermal oxidation process is performed to oxidize the exposed portion of the first silicon layer and the surface area of the second silicon layer; The gate region and the sidewalls of the interconnects; and finally the substrate is doped to form a third doped region in the second doped region that is not covered by the sidewall structure. Except for the contact formed by the buried contact It can be added to the subsequent process to form a comprehensive pilot line. A dielectric layer can be formed on the substrate first; then-thermal process; and a metallization process to form a continuous paper Standards are in accordance with Chinese National Standard (CNS) Λ4 specification (210X297 mm) —,) r! Γ -----: ----------, 1T ------ c (please first Read the notes on the back and fill in this page) A7 B7 -----: ---------- Order ------ (Please read the notes on the back before filling in this page) Ministry of Economy Central standard HIGHLAND consumer cooperatives printed V. invention is described in () line. Brief description of the circle type: The first figure shows the layer of the present invention on a substrate. The first figure shows the present invention as an embedded type. The third figure shows the present invention-the fourth figure on a silicon layer. The present invention shows the gate electrode. Area one, second doping, the fifth figure shows the present invention—the exposed cross-section of the silicon layer shows the sixth, showing the side of the interconnect of the present invention, seventh, shows the present invention region, and the second doping, the eighth figure shows a thermal process of the present invention. The last ninth figure shows a schematic cross-section of a gate insulating layer and the first silicon formed in the cross-sectional view of the present invention. It defines a cross-sectional schematic diagram of a buried contact opening and a shaped contact area. A second silicon layer is formed on the substrate and a schematic cross-sectional view. The second silicon layer is removed to define and an interconnect, and the substrate is doped to form a cross-sectional schematic of the region. A thermal oxidation process is performed to oxidize the first part and the surface area map of the second silicon layer. A schematic cross-sectional view of a sidewall structure formed in the gate region and the wall is formed. A mid-doped substrate to form a cross-sectional view of a third doped impurity region. A schematic cross-sectional view of a dielectric layer formed on a substrate and proceeding. A metallization process is performed to form a wiring pattern. This paper size is applicable to China National Standards (CNS) A4 (210X297mm) Μ B7 Printed by the Consumer Cooperatives of the Central Procurement Bureau of the Ministry of Economic Affairs 5. Description of the invention () Detailed description of the invention: This invention provides a form of embedded The contact method can eliminate the formation of trench defects and simplify the complicated steps to solve the trench defect problem in the traditional process. 'Utilization-the shape of the first silicon layer can avoid the problem of contamination of the photoresist layer when the buried contact opening is defined. And increase the latitude of the etching process ', and by applying the method of the present invention in the process of forming a static random access memory level,' the accumulation degree of the device can be improved. Referring to the first figure, a substrate 10 is first provided. Generally, the most common material is a silicon substrate with a crystal orientation of < 100 >, and other materials or crystal orientation semiconductor materials can also be used. A field oxide layer 12 as an isolation region is formed on the substrate 10 to isolate the individual elements' isolation regions above the substrate 10. The isolation region can also be formed using other isolation processes, such as trench isolation. The field oxidation isolation region 12 is generally formed by covering the regions that need not be oxidized with an oxide layer and a gasification layer, and then the substrate 10 is heated and oxidized to grow in a gas-containing environment. Then, a field fluorinated isolation region 1 2 is formed. Next, a gate insulating layer 14 is formed on the substrate. The gate insulating layer 14 in this example uses an oxide layer. The oxide layer is heated and grown by the substrate 10. The thickness can be between 50 angstroms and 400 angstroms. Thereafter, a first silicon layer 16 is formed on the gate insulating layer 14. The first silicon layer 16 can be used as a buffer layer or a protective layer between the substrate 10 and the subsequent photoresist layer to prevent the photoresist material from affecting the substrate 10. Pollution caused by the problem, the first silicon wide 16 can use a 8 paper size applicable to the Chinese National Standard (CNS) A4 specifications (210X297 mm) I — IIL / ν installation — I i I order n I n 1 I (please (Please read the notes on the back before filling in this page.) A7 B7 printed by Shelley Consumer Cooperative, Central Bureau of the Ministry of Economic Affairs. 5. Description of the invention () The polycrystalline silicon layer has not been replaced. This polycrystalline silicon layer can be chemical vapor deposited. deposition (CVD) or low pressure chemical vapor deposition (LPCVD). In this embodiment, the thickness of the first layer 16 is about 10 nanometers to 50 nanometers. Between meters. Referring to the second figure, a buried contact opening 20 is defined in the first silicon layer 16 and the gate insulating layer 14, and the buried contact opening 20 extends to the surface of the substrate 10. The definition method of the buried contact opening 20 can be formed by using a photolithography process' to first form a photoresist layer 18 on the first silicon layer 16 and transfer the circles on the photomask to light by a lithography process. After the development of the resist layer 18, the photoresist layer 18 is used as a mask to perform an anisotropic cooking process. In this example, a reactive ion etching (RIE) method may be used. 'To remove part of the first silicon layer 16 and the gate insulating layer 14 to define the buried contact opening 20, and at the same time, by protecting the first silicon layer 16, the substrate 10 can be prevented from being contaminated by the photoresist layer 18. The substrate 10 'is then doped to form a buried contact region 22, which is located in the substrate 10 below the buried contact opening 20. The buried contact region 22 is a doping to reduce its resistance to Areas with high conductivity can be formed by implanting phosphorus or arsenic ions. During implantation, the photoresist layer 18 and field oxide layer 12 can be used as leather screens. The implanted energy is about 10 KeV to The amount between 100 KeV and about 5E14 atoms / cm2 to 5E16 atoms / cm2. Then, a second silicon layer 24 is formed on the substrate 10 and the first silicon layer 16 as shown in the second figure. Similarly, the second dream layer 24 can use an un-doped paper standard applicable to Chinese national standards. (CNS) A4 specifications (2 丨 OX297 mm) ---- ^ --------- 1T ----- "w (Please read the notes on the back before filling this page) A7 B7 V. Description of the invention () Polycrystalline dream layer 'This polycrystalline silicon layer can be formed by chemical vapor deposition (CVD) or low pressure chemical vapor deposition (LPCVD). The thickness of the second dream layer in this example is about 500 Angstroms to 3,000 Between Angstroms ", as shown in the fourth circle, and then remove a part of the second silicon layer 24 to define a gate region 24a and an interconnect 24b. The definition of the gate region 24a and the interconnect 24b can also be used. The lithographic process and the etching process of the circular process process, 'the details are not much introduced.' By the definition of the second silicon layer 24, a doping will be formed between the gate region 24a and the interconnect 24b. In general, the opening 26 in the low-doped junction region will form a natural space between the first silicon layer 16 and the second silicon layer 24 during the process. Thin oxide layer, and when the opening 26 is etched, the etching process can detect the way the oxide layer has progressed to this point to “generate good control without excessive engraving”, even if there is a slight excess The state of the etching occurs, and the substrate 10 can still be protected from the damage of the etching by the protection of the first silicon layer 16. Therefore, the process latitude of the etching process can be greatly improved. Printed by the Central Laboratories of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives -----: ---- c pack (please read the precautions on the back before filling out this page) When defining the opening 26, 'can be in contact with the embedded 26 A safety distance 28 is reserved between the positions of the areas 22. In the example, the width of the safety distance 28 can be set within the range of hundreds of angstroms. With this distance, the process can be reduced due to alignment errors. Due to the impact of the shift of the case, the tolerance of the process to the lithography process is increased, and the problem of trench defects in the traditional process can be avoided. Referring to the fifth figure, the substrate 10 is then doped to form a second miscellaneous region 30 in the substrate which is not covered by the gate region 24a and the interconnect 24b. 10 This paper is applicable to China National Ladder Standard {CNS > A4 specification (210X297 public envy) A7 Printed by B7 of the Central Ladder Standard Bureau of the Ministry of Economic Affairs and Consumer Cooperatives V. Description of the invention () ~ The second doping region 30 is a doping dose The low region is used to form the low-doped drain (LDD) and source structure of the transistor hip, so it can be implanted with phosphorus or containing silicon through the very thin first silicon layer 16 by ion implantation. The energy f of the ping ion is about 10 KeV to 80 KeV, and the dose is about Γ · 1 of 5E12atoms / cm2 to 5E14atoms / cm2. Thereafter, a thermal oxidation process is performed to oxidize the exposed portion of the first silicon layer 16, that is, the portion below the opening 26, and simultaneously oxidize the second silicon layer 24, that is, the surface of the gate region 24 a and the interconnect 24 b. In this region, the oxidation layer 32 can be formed by using a high-temperature oxidation process. In this example, the temperature of the oxidation process can be between about 750 ° C and 11501, and the ions in the buried contact region 22 and the second doping region 30 ' Will diffuse and activate at high temperature, so that a good electrical connection is formed between the buried contact region 22 and the second doped region 30 due to diffusion. At the same time, the gate region 24a and the interconnect 24b can be eliminated when the etching is performed. The resulting defect. Referring to the sixth figure, a sidewall structure 34 is then formed on the sidewalls of the gate region 24a and the interconnect 24b. In this embodiment, the sidewall structure 34 can be an oxide layer wall, and the oxide wall can be deposited and deposited. An oxide layer is etched back to form the 'at the same time, due to the etch-back process of the oxide spacer, most of the oxide layer 32 will be removed, leaving only a part of the oxide layer material of the sidewall structure 34. The substrate 10 is then doped to form a third doped region 36 in the second doped region 30 which is not covered by the sidewall structure 34. As shown in the seventh circle, the gate region The silicon material at 24a and 24b is also applicable to the Chinese standard (CNS) A4 size (210X297 male thin) (Please read the precautions on the back before filling this page) ~ Packing. Order C · Economy Printed by the Central Bureau of Standards, Shellfish Consumer Cooperative A7, B7 V. Description of the invention () The resistance value was reduced due to doping. The third doped region 36 is a region with a higher doping amount, and is used as a source-drain junction region of the transistor. Therefore, the sidewall structure 34 can be used as a mask, and the phosphorus-containing or The ions containing arsenic are implanted with an energy of about 10 KeV to 100 KeV. The dose is about 5E14 atoms / cm2 to 5E16 atoms / cm2. Using the above steps, a high-efficiency, high-integration transistor structure with embedded contacts can be formed for use in processes such as static memory. In addition to the connection formed by the buried contact, subsequent processes can be added to form a comprehensive conductor connection. First, a dielectric layer 38 can be formed on the substrate 10. As shown in the eighth circle, in this example, a dielectric layer such as borophospho dream glass (13〇1 > 0 卩 11〇3 卩 11〇3 丨 1 丨0 Wang 16; 6 ~ 8〇), the dream glass canopy can be formed by general chemical vapor deposition, or TEOS (tetra-ethyl-ortho-silicate) as the reaction gas II chemical vapor deposition process , And adding a gas containing boron or phosphorus to deposit boro-phosphosilicate glass (BP-TEOS) formed by TEOS. Next, a thermal process is performed to make the surface of the dielectric layer 38 have better flatness due to thermal flow, and simultaneously diffuse and activate the ions in the third doped region 36 to make the buried contact region 22 A good connection is formed between the junction areas 3¾ and 38, and the connection between other areas is formed through the interconnection 24b, which can effectively avoid the problem of trench defects in the traditional process and improve the component yield of the process. Next, a metallization process is performed to form the connection lines 40, and multiple metallization processes may be performed to form more layers of connection lines. The present invention is described above with a preferred embodiment, and is only used to help understand the implementation of the present invention, not to limit the spirit of the present invention. Familiar with this paper standard is applicable to the Chinese Standard for Household Standards (CNS) A4 (210X297 mm) ----- ^ --------- ίτ ------ c (Please read the notes on the back before filling this page) A7 B7 V. Description of the invention () Domain After comprehending the spirit of the present invention, the artist can make minor modifications and equivalent changes without departing from the spirit of the present invention. The scope of patent protection shall depend on the scope of the attached patent application and its equivalent fields. . -------- ^ Installation ------ Order ------ ο (Please read the notes on the back before filling out this page) Printed by this paper Standards: Chinese National Standard (CNS) A4 (210X297 mm)