TWI742251B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI742251B
TWI742251B TW107107268A TW107107268A TWI742251B TW I742251 B TWI742251 B TW I742251B TW 107107268 A TW107107268 A TW 107107268A TW 107107268 A TW107107268 A TW 107107268A TW I742251 B TWI742251 B TW I742251B
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Taiwan
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semiconductor device
film
opening
aluminum alloy
alloy wiring
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TW107107268A
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TW201836077A (zh
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三室陽一
加藤伸二郎
塩浦哲郎
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日商艾普凌科有限公司
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Abstract

半導體裝置100包括：基板101；積層體103，設置於基板的其中一個主面101a側，並包含鋁合金配線102與包圍其的絕緣膜107；以及矽氮化膜104，覆蓋積層體103，且於所述矽氮化膜及所述絕緣膜中，於與所述鋁合金配線102的接合部分重合的位置設置有開口部105，於鋁合金配線的表面中自開口部105露出的部分附著有包括含有矽與氮的反濺鍍殘渣的堆積物，並形成皮膜106。本發明提供一種半導體裝置，其能夠抑制鋁合金配線中作為焊墊而露出的部分藉由水分而被腐蝕（電流腐蝕）。

Description

半導體裝置及其製造方法
本發明是有關於一種半導體裝置及其製造方法。
形成於半導體晶圓上的積體電路(Integrated Circuit，IC)是藉由刀片切割(blade dicing)進行單片化(晶圓化)而被使用。關於通常的刀片切割，為了將切割過程中的刀片冷卻，並且將因切割而產生的切削屑去除，一面對刀片及其周邊噴附水(一般而言為比電阻得到管理的純水)一面進行刀片切割。
若此時所噴附的水附著於包含鋁合金(鋁與銅等的合金)的焊墊(bonding pad)，則於所述水分與鋁合金之間發生電流腐蝕(Galvanic corrosion)。其結果，於焊墊中產生鋁的空穴，與進行打線接合(wire bonding)時的焊線側的金屬(金、銀、銅)的接觸面積減少，打線接合強度變差。
於使用鋁合金的焊墊的表面，於接觸大氣的時間點形成有氧化鋁膜，但於切割時間變長的小晶圓的情況下，難以藉由所述厚度充分地防止電流腐蝕。氧化鋁膜可進行熱處理而變厚，但變厚了的氧化鋁膜於打線接合時未藉由超音波完全破壞而殘留於墊片上，故產生未進行接合的問題。
另外，於濕度高的環境下的長期可靠性試驗(溫度濕度 偏壓試驗(Temperature Humidity Bias Test，THB))中，存在如下問題：到達被供給有正電位的焊墊的水分使形成於墊片周圍的包含TiN的抗反射膜(TiN膜)腐蝕。原因在於，氧化鋁膜僅形成於鋁合金的表面，因此無法將TiN膜的表面覆蓋。為了實現可靠性高的IC製品，期望一種相對於進行切割或長期可靠性試驗時所產生的水分，防止鋁合金、作為抗反射膜的TiN膜露出的技術。
[現有技術文獻]
[專利文獻]
[專利文獻1]日本專利特開2012-174951號公報
本發明是鑒於所述狀況而成者，目的在於提供一種半導體裝置及其製造方法，所述半導體裝置能夠抑制鋁合金配線中作為焊墊而露出的部分藉由水分而被腐蝕(電流腐蝕)。
為了解決所述課題，本發明採用以下手段。
(1)本發明的一態樣的半導體裝置包括：基板；積層體，設置於基板的其中一個主面側，並包含鋁合金配線與包圍其的絕緣膜；以及矽氮化膜，覆蓋所述積層體，且於所述矽氮化膜及所述絕緣膜中，於與所述鋁合金配線的墊片部分重合的位置設置有實質上具有相同大小的開口部，於自所述開口部露出的墊片部分的表面附著有包括含有矽與氮的反濺鍍殘渣的堆積物，並形 成皮膜。
(2)於所述(1)所述的半導體裝置中，較佳為，矽以50%以上且70以下、氮以5%以上且25%以下的比例分別包含於所述皮膜中。
(3)於所述(1)或(2)中任一項所述的半導體裝置中，較佳為，所述皮膜進而包含氧。
(4)於所述(1)至(3)中任一項所述的半導體裝置中，較佳為，所述皮膜亦形成於所述開口部的內壁。
(5)於所述(1)至(4)中任一項所述的半導體裝置中，亦可於所述鋁合金配線的表面中、自所述開口部露出的部分的周圍形成有氮化鈦膜。
(6)於所述(1)至(5)中任一項所述的半導體裝置中，較佳為，所述皮膜的厚度為100Å以上且200Å以下。
(7)本發明的一態樣的半導體裝置的製造方法為如所述(1)至(6)中任一項所述的半導體裝置的製造方法，其包括以下步驟：於所述開口部形成之後，對所述矽氮化膜進行利用惰性氣體的電漿處理。
(8)於所述(7)所述的半導體裝置的製造方法中，較佳為，作為所述惰性氣體，使用氬氣。
(9)於所述(7)或(8)中任一項所述的半導體裝置的製造方法中，較佳為，將所述電漿處理的時間設為30秒以上且120秒以下。
於本發明的半導體裝置中，於鋁合金配線中、作為焊墊而露出的部分附著有包括含有矽與氮的反濺鍍殘渣的堆積物，並形成皮膜。所述皮膜作為具有耐水分性的保護膜起作用，因此，可抑制例如由如刀片切割時所噴附般的水分引起的腐蝕(電流腐蝕)。因而，於本發明的半導體裝置中，能夠防止因腐蝕而於鋁合金配線中發生缺損，且可提升對鋁合金配線進行接合時的接合強度。
100、200、300:半導體裝置
101、201、301:基板
101a、201a、301a:基板的其中一個主面
102、202、302:鋁合金配線
102A、202A、302A:墊片部分
102a、202a、302a:墊片部分的表面
103、203、303:積層體
104、204、304:矽氮化膜
104a:矽氮化膜的表面
105、205、305:開口部
105a、205a:開口部的內壁
106、206、309:皮膜
107、207、307:絕緣膜
107A、207A、307A:矽氧化膜
208:氮化鈦膜
D:惰性氣體
圖1是本發明的第一實施形態的半導體裝置的剖面圖。
圖2是對本發明的第一實施形態的半導體裝置的製造方法中的主要步驟進行說明的圖。
圖3是本發明的第二實施形態的半導體裝置的剖面圖。
圖4是表示本發明的實施例1的半導體裝置中的墊片表面部分的組成分析結果的圖表。
圖5是本發明的比較例1的半導體裝置的剖面圖。
圖6是表示本發明的比較例1的半導體裝置中的墊片表面部分的組成分析結果的圖表。
圖7是針對本發明的實施例1的半導體裝置中，電漿處理時間與形成於墊片上的膜的厚度之間的關係進行表示的圖表。
圖8是表示本發明的實施例1、比較例1的半導體裝置中， 切割時間與墊片表面的變色程度之間的關係的圖表。
圖9(a)~圖9(c)是表示本發明的實施例1的半導體裝置中，切割時間與墊片的表面狀態之間的關係的圖像。
圖10(a)~圖10(c)是表示本發明的比較例1的半導體裝置中，切割時間與墊片的表面狀態之間的關係的圖像。
圖11是表示本發明的實施例1、比較例1的半導體裝置中，切割時間與剪切強度之間的關係的圖表。
以下，一面適當參照圖一面對本發明進行詳細說明。為了容易理解本發明的特徵，以下說明中所使用的圖式存在為了方便而將成為特徵的部分放大顯示的情況，各構成要素的尺寸比例等有時與實際不同。另外，以下說明中所例示的材料、尺寸等為一例，本發明並不限定於該些，能夠於發揮本發明的效果的範圍內適當進行變更並實施。
<第一實施形態>
圖1是本發明的第一實施形態的半導體裝置100的剖面圖。半導體裝置100包括：矽等基板101；積層體103，設置於基板101的其中一個主面101a側，並包含鋁合金(鋁與銅等的合金)配線102與包圍其的絕緣膜(層間膜、層間絕緣膜)107；以及矽氮化膜104，覆蓋積層體103。
圖1中，作為包含於積層體103中的配線(層)，僅明示了位於最上層的鋁合金配線102，但除此以外，視用途亦可包含 具有各種形狀且含有各種材料的配線。另外，積層體103中除配線以外，亦可包含具有與用途相對應的各種功能的層。
絕緣膜107形成於構成積層體103的各層彼此之間、各層與基板101之間。作為絕緣膜107的具體例，可列舉：包含SiO2、原矽酸四乙酯(Tetraethyl orthosilicate，TEOS(Si(OC2H5)4))等材料的氧化膜、氧氮化膜、旋塗玻璃(spin on glass，SOG)等。
矽氮化膜104為藉由化學氣相沈積(Chemical Vapor Deposition，CVD)法而形成的膜，且分別以約40%、約50%、約10%的比例包含矽、氮、氫。矽氮化膜104的厚度較佳為7000Å以上且15000Å以下。
於位於鋁合金配線102之上的矽氮化膜104及絕緣膜107中，於與包含鋁合金配線102的墊片部分102A的成為打線焊墊的部分重合的位置，設置有實質上以相同大小被開口的開口部(墊片開口部)105。
於鋁合金配線102的表面中、自開口部105露出的墊片部分102A的表面102a上附著(再附著)有包括含有矽與氮作為主要成分的反濺鍍殘渣的堆積物，並形成包含所述堆積物的皮膜106。皮膜106可藉由對矽氮化膜104進行利用惰性氣體的電漿處理而形成。藉由使惰性氣體的電漿與矽氮化膜104碰撞而矽氮化膜104被反濺鍍並成為蝕刻去除物。皮膜106為藉由自矽氮化膜104產生的作為蝕刻去除物的反濺鍍殘渣再附著於鋁合金配線102的表面102a而進行堆積並形成者。皮膜106的耐水分性優異。
較佳為，矽以50%以上且70以下、氮以5%以上且25%以下的比例分別包含於皮膜106中。
皮膜106亦可進而以15%以上且35%以下的比例包含氧。所述氧主要源於藉由使大氣接觸鋁合金配線102的表面的露出部分102a而形成於此處的氧化鋁(Al2O3)膜。
若皮膜106不僅形成於鋁合金配線102的表面的露出部分102a，如圖1所示般，亦形成於開口部105的內壁，則可防止水分浸入至鋁合金配線102與絕緣膜107的界面，故更佳。
再者，就防止水分自該界面浸入的觀點而言，皮膜106只要覆蓋於所述界面上，即覆蓋開口部105的內壁105a的下端部周邊即可，亦可不形成至上端部為止。
鋁合金配線102中，形成於墊片部分102A的表面102a上的皮膜106的厚度較佳為100Å以上且200Å以下。藉由將皮膜106的厚度設為100Å以上，可幾乎完全防止水浸入至鋁合金配線102中。另外，若皮膜106的厚度為200Å以下，則可藉由超音波而容易地破壞，故可相對於鋁合金配線102而將焊線金屬良好地接合，且可確保高接合良率、可靠性。
如以上所說明般，於本實施形態的半導體裝置100中，於鋁合金配線102中、作為焊墊而露出的部分附著有包括含有矽與氮的反濺鍍殘渣的堆積物，並形成皮膜106。所述皮膜106作為具有耐水性的保護膜起作用，故可抑制例如由如刀片切割時所噴附般的水引起的腐蝕(電流腐蝕)。因而，於本實施形態的半導體 裝置100中，能夠防止因腐蝕而於鋁合金配線102中發生缺損，且可提升對鋁合金配線102進行接合時的接合強度。
[半導體裝置的製造方法]
對半導體裝置100的製造方法進行說明。
首先，於矽等基板101的其中一個主面101a上形成具有所需結構的積層體103。關於構成積層體103的各層，可藉由適當反覆進行利用CVD法、濺鍍法等公知方法的成膜、及利用光微影法的圖案化而形成。繼而，藉由電漿CVD法而於積層體103上形成矽氮化膜104。
繼而，以鋁合金配線102的表面中、進行打線接合的墊片部分102A的表面102a露出的方式，於在此時間點所形成的絕緣膜107及矽氮化膜104上形成實質上以相同大小被開口的開口部(墊片開口部)105。
繼而，藉由反應性離子蝕刻(Reactive Ion Etching，RIE)法對矽氮化膜104進行電漿處理(電漿蝕刻)。具體而言，對導入反應室內的惰性氣體D進行電漿化，並如圖2所示般使其碰撞矽氮化膜104的表面104a，對表面104a的一部分進行蝕刻。因所述蝕刻而產生的去除物再附著於所露出的鋁合金配線102的墊片部分(焊墊)102A的表面102a、及開口部105的內壁(墊片側壁)105a，藉此形成皮膜106。
作為惰性氣體D，可使用氬氣(Ar)、氙氣(Xe)等。
此處電漿處理的時間較佳為設為30秒以上且120秒以 下。藉由將電漿處理的時間設為所述範圍，可形成具有所述較佳厚度的皮膜106。
電漿處理過程中的反應室內的壓力較佳為設為600mTorr左右。
<第二實施形態>
[半導體裝置的構成]
圖3是本發明的第二實施形態的半導體裝置200的剖面圖。半導體裝置200中，於矽等基板201的其中一個主面201a上設置積層體203，該積層體203包含鋁合金(鋁和銅等合金)配線202與包圍其的絕緣膜(層間膜、層間絕緣膜)207，並具有覆蓋該積層體203上的矽氮化膜204。半導體裝置200中，於包含鋁合金配線202的墊片部分202A的表面202a中、自開口部205露出的部分的周圍形成有氮化鈦(TiN)膜208。所述氮化鈦膜208的厚度較佳為25nm以上且60nm以下。關於除了形成有氮化鈦膜208這一點以外的構成，與第一實施形態的半導體裝置100的構成相同，可獲得與半導體裝置100同等的效果。
於半導體裝置200中，不僅於自開口部205露出的鋁合金配線202的表面，亦於開口部205的內壁205a附著有堆積物並形成皮膜206，氮化鈦膜208的自開口部205的露出部分藉由所述皮膜206覆蓋。
氮化鈦膜208是作為對圖案化時的光的反射進行抑制的抗反射膜起作用者，亦被用於現有結構的半導體裝置中。然而， 現有結構的半導體裝置中的氮化鈦膜於為了打線接合用途而設置的開口部的內壁露出，故存在於長期可靠性試驗(THB)等濕度高的環境下，水分附著並腐蝕的問題。相對於此，本實施形態的半導體裝置200中具有氮化鈦膜208並未露出的結構，故可避免該腐蝕的問題。
[半導體裝置的製造方法]
半導體裝置200的製造方法與第一實施形態的半導體裝置100的製造方法的不同之處在於具有如下步驟：藉由CVD法等公知的方法於位於最上層的鋁合金配線202之上形成氮化鈦膜208。再者，於半導體裝置200的製造方法中，當進行形成矽氮化膜204之後的墊片開口時，於開口部205的位置，亦將主要由矽氮化膜207A形成的絕緣膜207及矽氮化膜204，以及氮化鈦膜208一併去除。關於形成、加工氮化鈦膜208的步驟以外的各步驟，與第一實施形態的半導體裝置100的製造方法中的各步驟相同。
[實施例]
以下，藉由實施例來進一步明確本發明的效果。再者，本發明並不限定於以下實施例，可於不變更其主旨的範圍內適當進行變更並實施。
[墊片表面部分的組成分析]
(實施例1)
作為本發明的實施例1，使用第一實施形態的半導體裝置100的樣品進行墊片表面部分的厚度方向上的組成分析。
於最上層的鋁合金配線102之上，分別以2000Å、7000Å的厚度依序形成矽氧化膜(SiO2)107A、矽氮化膜(SiN)104，並進行墊片開口。將針對墊片開口後的矽氮化膜104的電漿處理時間設為60秒，將電漿處理過程中的反應室內的壓力設為600mTorr左右。
圖4是表示組成分析的結果的圖表。圖表的橫軸藉由奈米單位來表示自電漿處理後的開口部105露出的、自墊片區域的最表面起的深度。圖表的縱軸藉由百分率來表示深度方向上的各元素的含有率的分佈。
於自墊片區域的最表面起沿深度方向約10nm的範圍內，觀察到以高比例含有Si元素、N元素、O元素的表面異常層。所述表面異常層相當於形成於鋁合金配線102之上的皮膜106。再者，表面異常層所含有的C、F是對應於實施環境而產生的不可避免的雜質，不會對本發明造成影響。
(比較例1)
作為本發明的比較例1，使用如圖5所示般的現有結構的半導體裝置300的樣品，進行墊片區域的自最表面起的深度方向上的組成分析。
半導體裝置300中，於矽等基板301的其中一個主面301a上設置積層體303，該積層體303包含鋁合金(鋁和銅等合金)配線302與包圍其的絕緣膜(層間膜、層間絕緣膜)307，並具有覆蓋該積層體303上的矽氮化膜304。
於位於鋁合金配線302之上的矽氮化膜304及絕緣膜307中，於與包含鋁合金配線302的墊片部分302A的成為打線焊墊的部分重合的位置，設置有實質上以相同大小被開口的開口部(墊片開口部)305。
與實施例1同樣地，於最上層的鋁合金配線302之上，分別以2000Å、7000Å的厚度依序形成SiO2膜307A、SiN膜304，並進行墊片開口。但是，並未對墊片開口後的SiN膜304進行電漿處理。自開口部305的墊片部分302A的表面上形成推定為氧化鋁(Al2O3)的皮膜309。
圖6是表示組成分析的結果的圖表。圖表的橫軸、縱軸與圖4相同。可知於自電漿處理後的墊片區域的最表面起沿深度方向約6.3nm的範圍內，形成有包含氧化鋁(Al2O3)的氧化膜。所述氧化膜是藉由使大氣接觸鋁合金配線302的表面的露出部分302a而形成於此處的自然氧化膜。
[電漿處理時間與形成於墊片表面的膜之間的關係]
使用實施例1的樣品來調查墊片開口後的電漿處理時間與電漿處理後的墊片表面狀態之間的關係。
圖7是針對電漿處理時間與形成於墊片上的膜(皮膜)的厚度之間的關係進行表示的圖表。圖表的橫軸藉由秒單位來表示電漿處理時間。圖表的縱軸藉由奈米單位來表示形成於墊片上的皮膜的厚度。由圖表得知，形成於墊片上的皮膜是藉由進行電漿處理而形成的膜，其厚度與電漿處理時間成比例地發生變化。
[切割時間與墊片表面狀態之間的關係]
於實施例1、比較例1的樣品的規定位置進行刀片切割之後，觀察墊片表面的狀態。圖8是表示切割時間與伴隨切割的墊片表面的變色程度之間的關係的圖表。圖表的橫軸藉由分鐘單位來表示切割時間。圖表的縱軸藉由百分率來表示墊片表面的變色程度。
於實施例1的樣品(以菱形點表示)中，墊片表面的變色程度維持0[%]，據此可知，電流腐蝕的發生得到了抑制。相對於此，於比較例1的樣品(以方形點表示)中可知，隨著延長切割時間，變色程度增大。
針對實施例1的樣品，關於將切割時間設為55分鐘、85分鐘、140分鐘的情況，分別於圖9(a)~圖9(c)中示出墊片的表面狀態。墊片的表面狀態於圖9(a)~圖9(c)的任一圖中均為良好，未觀察到依存於切割時間的變化。由該些結果考慮到，於實施例1的樣品中，即便進行刀片切割，亦不會發生由電流腐蝕引起的鋁合金配線的缺損，從而可維持接合強度。
針對比較例1的樣品，關於將切割時間設為55分鐘、85分鐘、140分鐘的情況，分別於圖10(a)~圖10(c)中示出墊片的表面狀態。若與圖9(a)~圖9(c)比較，則墊片的表面於圖10(a)~圖10(c)的任一圖中均變色，越延長切割時間，變色的程度越增大。由該些結果考慮到，於比較例1的樣品中，伴隨切割而於墊片表面發生電流腐蝕，且隨著切割時間變長而進一步發生腐蝕，故無法避免由鋁合金配線的缺損引起的接合強度 的降低。
[切割時間與剪切強度之間的關係]
於實施例1、比較例1的樣品的規定位置進行刀片切割之後，對墊片部分進行打線接合。圖11是針對刀片切割時間與打線接合部分的剪切強度(接合強度)之間的關係進行表示的圖表。圖表的橫軸藉由分鐘單位來表示切割時間，圖表的縱軸藉由克力單位來表示剪切強度。
實施例1的樣品維持固定的剪切強度。相對於此，比較例1的樣品隨著切割時間變長而剪切強度降低。由該些結果可知，基於圖8~圖10(圖10(a)~圖10(c))的結果的所述推斷是正確的。
100‧‧‧半導體裝置
101‧‧‧基板
101a‧‧‧基板的其中一個主面
102‧‧‧鋁合金配線
102A‧‧‧墊片部分
102a‧‧‧墊片部分的表面
103‧‧‧積層體
104‧‧‧矽氮化膜
105‧‧‧開口部
106‧‧‧皮膜
107‧‧‧絕緣膜
107A‧‧‧矽氧化膜

Claims (13)

  1. 一種半導體裝置，其特徵在於包括： 基板； 積層體，設置於基板的其中一個主面側，並包含鋁合金配線與包圍其的絕緣膜；以及 矽氮化膜，覆蓋所述積層體，且 於所述矽氮化膜及所述絕緣膜中，於與所述鋁合金配線的墊片部分重合的位置設置有實質上具有相同大小的開口部， 於自所述開口部露出的所述墊片部分的表面附著有包括含有矽與氮的反濺鍍殘渣的堆積物，並形成皮膜。
  2. 如申請專利範圍第1項所述的半導體裝置，其中，矽以50%以上且70以下、氮以5%以上且25%以下的比例分別包含於所述皮膜中。
  3. 如申請專利範圍第1項所述的半導體裝置，其中，所述皮膜進而包含氧。
  4. 如申請專利範圍第2項所述的半導體裝置，其中，所述皮膜進而包含氧。
  5. 如申請專利範圍第1項所述的半導體裝置，其中，所述皮膜亦形成於所述開口部的內壁。
  6. 如申請專利範圍第2項所述的半導體裝置，其中，所述皮膜亦形成於所述開口部的內壁。
  7. 如申請專利範圍第3項所述的半導體裝置，其中，所述皮膜亦形成於所述開口部的內壁。
  8. 如申請專利範圍第4項所述的半導體裝置，其中，所述皮膜亦形成於所述開口部的內壁。
  9. 如申請專利範圍第1項至第8項中任一項所述的半導體裝置，其中，於所述鋁合金配線的表面中、自所述開口部露出的部分的周圍形成有氮化鈦膜。
  10. 如申請專利範圍第1項至第8項中任一項所述的半導體裝置，其中，所述皮膜的厚度為100 Å以上且200 Å以下。
  11. 一種半導體裝置的製造方法，其為如申請專利範圍第1項至第8項中任一項所述的半導體裝置的製造方法，所述半導體裝置的製造方法的特徵在於包括以下步驟： 於所述開口部形成之後，對所述矽氮化膜進行利用惰性氣體的電漿處理。
  12. 如申請專利範圍第11項所述的半導體裝置的製造方法，其中，所述惰性氣體為氬氣。
  13. 如申請專利範圍第11項所述的半導體裝置的製造方法，其中，將所述電漿處理的時間設為30秒以上且120秒以下。
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