CN108573947A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

Info

Publication number
CN108573947A
CN108573947A CN201810178281.8A CN201810178281A CN108573947A CN 108573947 A CN108573947 A CN 108573947A CN 201810178281 A CN201810178281 A CN 201810178281A CN 108573947 A CN108573947 A CN 108573947A
Authority
CN
China
Prior art keywords
semiconductor device
film
aluminium alloy
opening portion
overlay film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
CN201810178281.8A
Other languages
English (en)
Inventor
三室阳
三室阳一
加藤伸二郎
盐浦哲郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Publication of CN108573947A publication Critical patent/CN108573947A/zh
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/022—Protective coating, i.e. protective bond-through coating
    • H01L2224/02215—Material of the protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/03019—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for protecting parts during the process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/0382—Applying permanent coating, e.g. in-situ coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/0382—Applying permanent coating, e.g. in-situ coating
    • H01L2224/03826—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0391—Forming a passivation layer after forming the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45139—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8536—Bonding interfaces of the semiconductor or solid state body
    • H01L2224/85375—Bonding interfaces of the semiconductor or solid state body having an external coating, e.g. protective bond-through coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Optics & Photonics (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

本发明提供半导体装置，半导体装置(100)具有：基板(101)；层叠体(103)，其设置在基板的一个主面(101a)侧且包含铝合金布线(102)和包围该铝合金布线(102)绝缘膜(107)；和覆盖层叠体(103)的氮化硅膜(104)，在上述氮化硅膜和上述绝缘膜上，在与上述铝合金布线(102)的焊接部分重叠的位置设置有开口部(105)，在铝合金布线的表面中的从开口部(105)露出的部分附着包含含有硅和氮的反溅射残渣的堆积物而形成有覆膜(106)。该半导体装置能够防止铝合金布线中的作为焊盘露出的部分由于水分而发生腐蚀(电化腐蚀)。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置及其制造方法。
背景技术
形成在半导体晶片上的集成电路(IC)通过刀具切割进行单片化(芯片化)而使用。对于通常的刀具切割而言，为了对切割中的刀具进行冷却，并且除去由于切割而产生的切削屑，一边对刀具及其周边喷吹水(通常为控制了电阻率的纯水)一边进行刀具切割。
若此时喷吹的水附着在包含铝合金(铝与铜等的合金)的焊盘上，则在该水分与铝合金之间产生电化腐蚀。其结果是，在焊盘上产生铝的空孔，进行引线接合时的与引线侧的金属(金、银、铜)的接触面积变少，引线接合强度劣化。
在使用有铝合金的焊盘的表面，在与大气接触的时刻形成有氧化铝膜，但在切割时间变长的小芯片的情况下，因其厚度而难以充分防止电化腐蚀。氧化铝膜虽然能够进行热处理来增厚，但增厚了的氧化铝膜在引线接合时无法利用超声波彻底破坏而残留在焊盘上，因此产生无法进行焊接的问题。
另外，在湿度高的环境下的长期可靠性试验(THB)中，存在到达至供给了正电位的焊盘的水分使得在焊盘的周围形成的包含TiN的防反射膜(TiN膜)被腐蚀的问题。这是因为，氧化铝膜仅在铝合金的表面生成，因此无法覆盖TiN膜的表面。为了实现可靠性高的IC制品，期望防止铝合金、作为防反射膜的TiN膜相对于切割或进行长期可靠性试验时产生的水分露出的技术。
现有技术文献
专利文献
专利文献1：日本特开2012-174951号公报
发明内容
发明所要解决的课题
本发明是鉴于上述情况而完成的，其目的在于提供一种半导体装置及其制造方法，其能够抑制铝合金布线中的作为焊盘露出的部分由于水分而发生腐蚀(电化腐蚀)。
用于解决课题的手段
为了解决上述课题，本发明采用下述方法。
(1)本发明的一个方式的半导体装置具有：基板；层叠体，其设置在基板的一个主面侧且包含铝合金布线和包围该铝合金布线的绝缘膜；和覆盖上述层叠体的氮化硅膜，在上述氮化硅膜和上述绝缘膜中，在与上述铝合金布线的焊盘部分重叠的位置设置有具有实质上相同尺寸的开口部，在从上述开口部露出的焊盘部分的表面上附着包含含有硅和氮的反溅射残渣的堆积物，形成覆膜。
(2)在上述(1)所述的半导体装置中，优选在上述覆膜中分别地以50％以上70％以下的比例含有硅、以5％以上25％以下的比例含有氮。
(3)在上述(1)或(2)中任一项所述的半导体装置中，优选上述覆膜进一步含有氧。
(4)在上述(1)～(3)中任一项所述的半导体装置中，优选上述覆膜还形成在上述开口部的内壁。
(5)在上述(1)～(4)中任一项所述的半导体装置中，也可以在上述铝合金布线的表面中的从上述开口部露出的部分的周围形成有氮化钛膜。
(6)在上述(1)～(5)中任一项所述的半导体装置中，优选上述覆膜的厚度为以上以下。
(7)本发明的一个方式的半导体装置的制造方法为上述(1)～(6)中任一项所述的半导体装置的制造方法，在形成上述开口部之后，具有对上述氮化硅膜进行使用非活性气体的等离子体处理的工序。
(8)在上述(7)所述的半导体装置的制造方法中，优选使用氩气作为上述非活性气体。
(9)在上述(7)或(8)中任一项所述的半导体装置的制造方法中，优选将上述等离子体处理的时间设为30秒以上120秒以下。
发明效果
在本发明的半导体装置中，在铝合金布线中的作为焊盘露出的部分附着包含含有硅和氮的反溅射残渣的堆积物，形成覆膜。该覆膜作为具有耐水性的保护膜发挥功能，能够抑制例如在刀具切割时喷吹那样的水分所导致的腐蚀(电化腐蚀)。因此，在本发明的半导体装置中，能够防止由于腐蚀而在铝合金布线上产生缺损，能够提高在铝合金布线进行焊接时的焊接强度。
附图说明
图1是本发明的第一实施方式的半导体装置的截面图。
图2是对本发明的第一实施方式的半导体装置的制造方法中的主要工序进行说明的图。
图3是本发明的第二实施方式的半导体装置的截面图。
图4是示出本发明的实施例1的半导体装置中的焊盘表面部分的组成分析结果的曲线图。
图5是本发明的比较例1的半导体装置的截面图。
图6是示出本发明的比较例1的半导体装置中的焊盘表面部分的组成分析结果的曲线图。
图7是示出对于本发明的实施例1的半导体装置而言等离子体处理时间与形成在焊盘上的膜的厚度的关系的曲线图。
图8是示出对于本发明的实施例1、比较例1的半导体装置而言切割时间与焊盘表面的变色程度的关系的曲线图。
图9的(a)～(c)是示出对于本发明的实施例1的半导体装置而言切割时间与焊盘的表面状态的关系的图像。
图10的(a)～(c)是示出对于本发明的比较例1的半导体装置而言切割时间与焊盘的表面状态的关系的图像。
图11是示出对于本发明的实施例1、比较例1的半导体装置而言切割时间与抗剪强度(シェア強度)的关系的曲线图。
具体实施方式
以下，适当参照附图对本发明进行详细的说明。对于以下的说明中所用的附图，为了容易明白本发明的特征，有时方便起见将成为特征的部分放大示出，有时各构成要件的尺寸比例等与实际不同。另外，在以下的说明中例示的材料、尺寸等为一例，本发明并不限于这些，可以在发挥本发明的效果的范围内适当进行变更并实施。
<第一实施方式>
[半导体装置的构成]
图1是本发明的第一实施方式的半导体装置100的截面图。半导体装置100具有：硅等的基板101；层叠体103，其设置在基板101的一个主面侧101a且包含铝合金(铝与铜等的合金)布线102和包围该铝合金布线102的绝缘膜(层间膜、层间绝缘膜)107；和覆盖层叠体103的氮化硅膜104。
在图1中，作为层叠体103所含的布线(层)，仅明确示出位于最上层的铝合金布线102，但除此之外，也可以根据用途包含具有各种形状、由各种材料构成的布线。另外，除了布线以外，层叠体103还可以包含具有与用途相应的各种功能的层。
绝缘膜107形成在构成层叠体103的各层彼此之间、各层与基板101之间。作为绝缘膜107的具体例，可以举出包含SiO2、TEOS(正硅酸四乙酯(Si(OC2H5)4))等材料的氧化膜、氮氧化膜、SOG等。
氮化硅膜104是通过CVD法形成的膜，分别以约40％、约50％、约10％的比例含有硅、氮、氢。氮化硅膜104的厚度优选为以上以下。
在位于铝合金布线102之上的氮化硅膜104和绝缘膜107上，在与包含铝合金布线102的焊盘部分102A的成为引线焊盘的部分重叠的位置，设置有实质上开口为相同尺寸的开口部(焊盘开口部)105。
在铝合金布线102的表面中的从开口部105露出的焊盘部分102A的表面102a上附着(再附着)包含含有硅和氮作为主要成分的反溅射残渣的堆积物，形成包含该堆积物的覆膜106。覆膜106可以通过对氮化硅膜104进行基于非活性气体的等离子体处理来形成。通过非活性气体的等离子体碰撞氮化硅膜104，氮化硅膜104发生反溅射，成为蚀刻除去物。从氮化硅膜104产生的蚀刻除去物即反溅射残渣再附着于铝合金布线102的表面102a，从而堆积而形成覆膜106。覆膜106的耐水性优异。
优选在覆膜106中分别地以50％以上70％以下的比例含有硅、以5％以上25％以下的比例含有氮。
覆膜106可以进一步以15％以上35％以下的比例含有氧。该氧主要源自因大气与铝合金布线102的表面的露出部分102a接触而形成于此处的氧化铝(Al2O3)膜。
若覆膜106不仅形成在铝合金布线102的表面的露出部分102a，而且如图1所示那样还形成在开口部105的内壁，则能够防止水分渗入铝合金布线102与绝缘膜107的界面，因此是更优选的。
需要说明的是，从防止水分从该界面渗入的观点出发，覆膜106覆盖该界面上、即开口部105的内壁105a的下端部周边即可，可以不形成至上端部。
形成在铝合金布线102中的焊盘部分102A的表面102a的覆膜106的厚度优选为以上以下。通过使覆膜106的厚度为以上，能够几乎完全防止水渗入至铝合金布线102。另外，若覆膜106的厚度为以下，则能够利用超声波容易地破坏，因此能够对铝合金布线102良好地焊接引线金属，从而能够确保高的焊接成品率、可靠性。
如以上说明那样，在本实施方式的半导体装置100中，在铝合金布线102中的作为焊盘露出的部分附着包含含有硅和氮的反溅射残渣的堆积物，形成覆膜106。该覆膜106作为具有耐水性的保护膜发挥功能，因此能够抑制例如在刀具切割时喷吹那样的水所导致的腐蚀(电化腐蚀)。因此，在本实施方式的半导体装置100中，能够防止由于腐蚀而在铝合金布线102产生缺损，能够提高在铝合金布线102上进行焊接时的焊接强度。
[半导体装置的制造方法]
对半导体装置100的制造方法进行说明。
首先，在硅等的基板101的一个主面101a形成具有所期望的结构的层叠体103。对于构成层叠体103的各层，可以通过适当地反复进行基于CVD法、溅射法等公知方法的成膜以及基于光刻法的图案化来形成。接着，利用等离子体CVD法在层叠体103上形成氮化硅膜104。
接着，在该时刻所形成的绝缘膜107和氮化硅膜104上形成开口为实质上相同尺寸的开口部(焊盘开口部)105，以使铝合金布线102的表面102a中的进行引线接合的焊盘部分102A的表面露出。
接着，利用反应性离子蚀刻(RIE)法对氮化硅膜104进行等离子体处理(等离子体蚀刻)。具体而言，对导入至反应室内的非活性气体D进行等离子体化，并如图2所示那样使其碰撞氮化硅膜104的表面104a，从而对表面104a的一部分进行蚀刻。通过该蚀刻而产生的除去物再附着于露出的铝合金布线102的焊盘部分(焊盘)102A的表面102a以及开口部105的内壁(焊盘侧壁)105a，从而形成覆膜106。
作为非活性气体D，可以使用氩(Ar)、氙(Xe)等。
此处的等离子体处理的时间优选为30秒以上120秒以下。通过使等离子体处理的时间为该范围，能够形成具有上述优选厚度的覆膜106。
等离子体处理中的反应室内的压力优选为600mTorr左右。
<第二实施方式>
[半导体装置的构成]
图3是本发明的第二实施方式的半导体装置200的截面图。在半导体装置200中，在包含铝合金布线202的焊盘部分202A的表面202a中的从开口部205露出的部分的周围形成有氮化钛(TiN)膜208。该氮化钛膜208的厚度优选为25nm以上60nm以下。对于除了形成有氮化钛膜208这点以外的构成，与第一实施方式的半导体装置100的构成是同样的，能够得到与半导体装置100同等的效果。
在半导体装置200中，不仅在从开口部205露出的铝合金布线202的表面附着堆积物而形成覆膜206，而且在开口部205的内壁205a也附着堆积物而形成覆膜206，从而氮化钛膜208的从开口部205露出的部分被该覆膜206覆盖。
氮化钛膜208作为抑制图案化时的光的反射的防反射膜发挥功能，在现有结构的半导体装置中也使用氮化钛膜。但是，现有结构的半导体装置中的氮化钛膜在用于引线接合而设置的开口部的内壁上露出，因此在长期可靠性试验(THB)等湿度高的环境下，存在水分附着而发生腐蚀的问题。与此相对，在本实施方式的半导体装置200中，具有氮化钛膜208不露出的结构，因此能够避免该腐蚀的问题。
[半导体装置的制造方法]
半导体装置200的制造方法具有在位于最上层的铝合金布线202上利用CVD法等公知的方法形成氮化钛膜208的工序，这点与第一实施方式的半导体装置100的制造方法不同。需要说明的是，在半导体装置200的制造方法中，在进行形成了氮化硅膜204之后的焊盘开口时，在开口部205的位置将氮化钛膜208与绝缘膜207和氮化硅膜204一起除去。对于形成、加工氮化钛膜208的工序以外的各工序，与第一实施方式的半导体装置100的制造方法中的各工序是同样的。
实施例
以下，通过实施例使本发明的效果更明确。需要说明的是，本发明并不限于以下的实施例，可以在不变更其要点的范围内适当变更并实施。
[焊盘表面部分的组成分析]
(实施例1)
作为本发明的实施例1，使用第一实施方式的半导体装置100的样品，进行焊盘表面部分的厚度方向上的组成分析。
在最上层的铝合金布线102上分别以的厚度依次形成氧化硅膜(SiO2)107A、氮化硅膜(SiN)104，并进行焊盘开口。将对于焊盘开口后的氮化硅膜104的等离子体处理时间设为60秒，将等离子体处理中的反应室内的压力设为600mTorr左右。
图4是示出组成分析的结果的曲线图。曲线图的横轴以纳米为单位示出自等离子体处理后的从开口部105露出的焊盘区域的最外表面起的深度。曲线图的纵轴以百分数示出深度方向上的各元素的含量的分布。
自焊盘区域的最外表面起，在深度方向上约10nm的范围内发现以高的比例含有Si、N、O元素的表面异常层。该表面异常层相当于形成在铝合金布线102上的覆膜106。需要说明的是，表面异常层所含的C、F是与实施环境相应地产生的不可避免的杂质，不会给本发明带来影响。
(比较例1)
作为本发明的比较例1，使用图5所示那样的现有结构的半导体装置300的样品，进行自焊盘区域的最外表面起的深度方向上的组成分析。
与实施例1同样地，在最上层的铝合金布线302上分别以的厚度依次形成SiO2膜307A、SiN膜304，并进行焊盘开口。其中，不进行对于焊盘开口后的SiN膜304的等离子体处理。
图6是示出组成分析的结果的曲线图。对于曲线图的横轴、纵轴，与图4是同样的。可知自等离子体处理后的焊盘区域的最外表面起在深度方向上约6.3nm的范围内形成有包含氧化铝(Al2O3)的氧化膜。该氧化膜是大气与铝合金布线302的表面的露出部分302a接触而形成于此的自然氧化膜。
[等离子体处理时间与形成在焊盘表面的膜的关系]
使用实施例1的样品，研究焊盘开口后的等离子体处理时间与等离子体处理后的焊盘表面状态的关系。
图7是示出等离子体处理时间与形成在焊盘上的膜(覆膜)的厚度的关系的曲线图。曲线图的横轴以秒为单位示出等离子体处理时间。曲线图的纵轴以纳米为单位示出形成在焊盘上的覆膜的厚度。由曲线图可知，形成在焊盘上的覆膜是通过进行等离子体处理而形成的膜，其厚度与等离子体处理时间成比例地变化。
[切割时间与焊盘表面状态的关系]
在实施例1、比较例1的样品的规定的位置进行刀具切割，然后观察焊盘表面的状态。图8是示出切割时间与伴随切割的焊盘表面的变色程度的关系的曲线图。曲线图的横轴以分钟为单位示出切割时间。曲线图的纵轴以百分数示出焊盘表面的变色程度。
在实施例1的样品(以菱形图例表示)中，无论切割时间如何，焊盘表面的变色程度一直保持为0[％]，因此可知能够抑制产生电化腐蚀。与此相对，在比较例1的样品(以方块图例表示)中，可知随着切割时间增长，变色程度变大。
对于实施例1的样品，将切割时间为55分钟、85分钟、140分钟的情况下的焊盘的表面状态分别示于图9的(a)～(c)。焊盘的表面状态在图9的(a)～(c)的任一个中均良好，未发现依赖切割时间的变化。由这些结果认为，在实施例1的样品中，即使进行刀具切割，也不产生电化腐蚀所导致的铝合金布线的缺损，能够维持焊接强度。
对于比较例1的样品，将切割时间为55分钟、85分钟、140分钟的情况下的焊盘的表面状态分别示于图10的(a)～(c)。与图9的(a)～(c)进行比较，焊盘的表面在图10的(a)～(c)的任一个中均发生变色，随着切割时间增长，变色的程度增大。由这些结果认为，在比较例1的样品中，伴随切割在焊盘表面产生电化腐蚀，随着切割时间增长，腐蚀进一步加剧，因此无法避免由于铝合金布线的缺损所导致的焊接强度的降低。
[切割时间与抗剪强度的关系]
在实施例1、比较例1的样品的规定的位置进行刀具切割，然后对焊盘部分进行引线接合。图11是示出刀具切割时间与引线接合部分的抗剪强度(焊接强度)的关系的曲线图。曲线图的横轴以分钟为单位示出切割时间，曲线图的纵轴以克重为单位示出抗剪强度。
实施例1的样品无论切割时间如何均维持一定的抗剪强度。与此相对，比较例1的样品随着切割时间增长，抗剪强度降低。由这些结果可知，基于图8～10的结果的上述推定是正确的。
符号说明
100、200、300…半导体装置
101、201、301…基板
101a、201a、301a…基板的一个主面
102、202、302…铝合金布线
102A、202A、302A…焊盘部分
102a、202a、302a…焊盘部分的表面
103、203、303…层叠体
104、204、304…氮化硅膜
104a、204a…氮化硅膜的表面
105、205、305…开口部
105a、205a…开口部的内壁
106、206…覆膜
107、207、307…绝缘膜
107A、207A、307A…氧化硅膜
208…氮化钛膜
D…非活性气体

Claims (13)

1.一种半导体装置，其特征在于，其具有：
基板；
层叠体，其设置在基板的一个主面侧且包含铝合金布线和包围该铝合金布线的绝缘膜；和
覆盖所述层叠体的氮化硅膜，
在所述氮化硅膜和所述绝缘膜中，在与所述铝合金布线的焊盘部分重叠的位置设置有具有实质上相同尺寸的开口部，
在从所述开口部露出的所述焊盘部分的表面上附着包含含有硅和氮的反溅射残渣的堆积物，形成覆膜。
2.如权利要求1所述的半导体装置，其特征在于，在所述覆膜中，分别地以50％以上70％以下的比例含有硅、以5％以上25％以下的比例含有氮。
3.如权利要求1所述的半导体装置，其特征在于，所述覆膜进一步含有氧。
4.如权利要求2所述的半导体装置，其特征在于，所述覆膜进一步含有氧。
5.如权利要求1所述的半导体装置，其特征在于，所述覆膜还形成在所述开口部的内壁。
6.如权利要求2所述的半导体装置，其特征在于，所述覆膜还形成在所述开口部的内壁。
7.如权利要求3所述的半导体装置，其特征在于，所述覆膜还形成在所述开口部的内壁。
8.如权利要求4所述的半导体装置，其特征在于，所述覆膜还形成在所述开口部的内壁。
9.如权利要求1～8中任一项所述的半导体装置，其特征在于，在所述铝合金布线的表面中的从所述开口部露出的部分的周围形成有氮化钛膜。
10.如权利要求1～8中任一项所述的半导体装置，其特征在于，所述覆膜的厚度为以上以下。
11.一种半导体装置的制造方法，其为权利要求1～8中任一项所述的半导体装置的制造方法，其特征在于，
在形成所述开口部之后，具有对所述氮化硅膜进行使用非活性气体的等离子体处理的工序。
12.如权利要求11所述的半导体装置的制造方法，其特征在于，使用氩气作为所述非活性气体。
13.如权利要求11所述的半导体装置的制造方法，其特征在于，将所述等离子体处理的时间设为30秒以上120秒以下。
CN201810178281.8A 2017-03-07 2018-03-05 半导体装置及其制造方法 Withdrawn CN108573947A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017-043156 2017-03-07
JP2017043156A JP6793575B2 (ja) 2017-03-07 2017-03-07 半導体装置とその製造方法

Publications (1)

Publication Number Publication Date
CN108573947A true CN108573947A (zh) 2018-09-25

Family

ID=63445661

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810178281.8A Withdrawn CN108573947A (zh) 2017-03-07 2018-03-05 半导体装置及其制造方法

Country Status (4)

Country Link
US (1) US10586776B2 (zh)
JP (1) JP6793575B2 (zh)
CN (1) CN108573947A (zh)
TW (1) TWI742251B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111599822A (zh) * 2020-05-28 2020-08-28 Tcl华星光电技术有限公司 阵列基板、显示装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10483108B2 (en) 2017-04-28 2019-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070238304A1 (en) * 2006-04-11 2007-10-11 Jui-Hung Wu Method of etching passivation layer
CN101821754A (zh) * 2007-10-10 2010-09-01 蔻维尔公司 高可靠性监视和/或识别标签/器件及其制造和使用方法
CN102651373A (zh) * 2011-02-23 2012-08-29 索尼公司 半导体器件的制造方法、半导体器件和电子装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001196413A (ja) * 2000-01-12 2001-07-19 Mitsubishi Electric Corp 半導体装置、該半導体装置の製造方法、ｃｍｐ装置、及びｃｍｐ方法
JP2003142521A (ja) * 2001-11-01 2003-05-16 Nec Electronics Corp 半導体装置およびその製造方法
JP2006303452A (ja) * 2005-03-25 2006-11-02 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP6368850B2 (ja) * 2015-03-02 2018-08-01 株式会社日立国際電気 クリーニング方法、半導体装置の製造方法、基板処理装置およびプログラム

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070238304A1 (en) * 2006-04-11 2007-10-11 Jui-Hung Wu Method of etching passivation layer
CN101821754A (zh) * 2007-10-10 2010-09-01 蔻维尔公司 高可靠性监视和/或识别标签/器件及其制造和使用方法
CN102651373A (zh) * 2011-02-23 2012-08-29 索尼公司 半导体器件的制造方法、半导体器件和电子装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111599822A (zh) * 2020-05-28 2020-08-28 Tcl华星光电技术有限公司 阵列基板、显示装置

Also Published As

Publication number Publication date
JP6793575B2 (ja) 2020-12-02
JP2018148090A (ja) 2018-09-20
TW201836077A (zh) 2018-10-01
US20180261562A1 (en) 2018-09-13
TWI742251B (zh) 2021-10-11
US10586776B2 (en) 2020-03-10

Similar Documents

Publication Publication Date Title
US6362087B1 (en) Method for fabricating a microelectronic fabrication having formed therein a redistribution structure
US7329607B2 (en) Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby
US6184060B1 (en) Integrated circuits and methods for their fabrication
JP4373866B2 (ja) 半導体装置の製造方法
US20050266672A1 (en) Wire-bonding method for chips with copper interconnects by introducing a thin layer
CN1989604B (zh) 功能元件及其制造方法、以及功能元件装配结构体
US6593222B2 (en) Method to improve the reliability of thermosonic gold to aluminum wire bonds
US20100184285A1 (en) Method to prevent corrosion of bond pad structure
JP2005093486A (ja) 半導体装置の製造方法及び半導体装置
CN100505254C (zh) 半导体器件及其制作方法
US20100267204A1 (en) Package structure for integrated circuit device and method of the same
CN108573947A (zh) 半导体装置及其制造方法
JP3974039B2 (ja) 表面を自己保護したＣｕレーザーヒューズ
US10109524B2 (en) Recessing of liner and conductor for via formation
CN101640179B (zh) 焊垫结构的制作方法
US6355576B1 (en) Method for cleaning integrated circuit bonding pads
EP2312619A1 (en) Method for manufacturing semiconductor device
US5833758A (en) Method for cleaning semiconductor wafers to improve dice to substrate solderability
JP2007103593A (ja) 半導体装置及びその製造方法
EP1423870A2 (en) Process for charged particle beam micro-machining of copper
US6580072B1 (en) Method for performing failure analysis on copper metallization
JP2000068269A (ja) 半導体装置および半導体装置の製造方法
JP2021048339A (ja) 半導体装置及び半導体装置の製造方法
US7163884B2 (en) Semiconductor device and fabrication method thereof
JPH06314690A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
CB02 Change of applicant information

Address after: Chiba County, Japan

Applicant after: ABLIC Inc.

Address before: Chiba County, Japan

Applicant before: DynaFine Semiconductor Co.,Ltd.

CB02 Change of applicant information
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WW01 Invention patent application withdrawn after publication

Application publication date: 20180925

WW01 Invention patent application withdrawn after publication