TWI728226B - 半導體裝置及在膜層上形成系統級模組封裝之方法 - Google Patents

半導體裝置及在膜層上形成系統級模組封裝之方法 Download PDF

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TWI728226B
TWI728226B TW107102626A TW107102626A TWI728226B TW I728226 B TWI728226 B TW I728226B TW 107102626 A TW107102626 A TW 107102626A TW 107102626 A TW107102626 A TW 107102626A TW I728226 B TWI728226 B TW I728226B
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layer
substrate
film layer
semiconductor die
penetrable
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TW107102626A
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TW201903916A (zh
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金五漢
金京煥
白蕓在
李勳擇
尹仁相
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新加坡商星科金朋有限公司
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Abstract

本發明提供一種有半導體晶粒或構件的半導體裝置，包含一整合式被動裝置(IPD)，被設置在一可穿透膜層的貼附區上方，該半導體晶粒或構件的一部分被埋置在該可穿透膜層中。一導體層被形成在該貼附區裡面的該膜層的一部分上方以及該貼附區外面的該膜層的一部分上方。一囊封劑被沉積在該膜層、導體層、以及半導體晶粒或構件的上方。該導體層延伸在該囊封劑外面。一絕緣材料被設置在該半導體晶粒或構件下方。一屏蔽層被形成在該囊封劑上方。該屏蔽層被電連接至該導體層。該可穿透膜層被移除。被設置在該膜層上方且被該囊封劑與屏蔽層遮蓋的半導體晶粒或構件形成一沒有基板的系統級模組封裝。

Description

半導體裝置及在膜層上形成系統級模組封裝之方法
本發明大體上和半導體裝置有關，且更明確地說，關於一種半導體裝置及在膜層上形成系統級模組封裝之方法。
在現代的電子產品中經常發現半導體裝置。半導體裝置實施各式各樣的功能，例如，訊號處理、高速計算、傳送與接收電磁訊號、控制電子裝置、將太陽光轉換成電能、以及產生電視顯示器的視覺影像。在通訊領域、電力轉換領域、網路領域、電腦領域、娛樂領域、以及消費性產品領域中皆會發現半導體裝置。在軍事應用、航空、自動車、工業控制器、以及辦公室設備中同樣會發現半導體裝置。
半導體裝置，尤其是在諸如射頻(Radio Frequency，RF)無線通訊的高頻應用中，經常含有一或更多個整合式被動裝置(Integrated Passive Device，IPD)用以實施必要的電氣功能。該些IPD易受到電磁干擾(ElectroMagnetic Interference，EMI)、射頻干擾(Radio Frequency Interference，RFI)、諧波失真、或是其它裝置間干擾(例如，電容性、電感性、或是電導性耦合，亦稱為串訊，其會干擾它們的操作)的影響。數位電路的高速切換也會產生干擾。
多個半導體晶粒和離散式IPD會被整合於一系統級模組封裝之中，以便在小空間中達到較高密度並且擴充電氣功能。該些半導體晶粒和離散 式IPD被鑲嵌至一基板，用以達到結構性支撐和電互連的目的。一囊封劑被設置在該半導體晶粒、該些離散式IPD、以及基板上方。一屏蔽層被形成在該囊封劑上方，用以隔離敏感電路。該系統級模組封裝基板通常被鑲嵌且被電氣連接至下一個整合層中的電路板。該基板會限制設計彈性，增加該系統級模組封裝的輪廓或厚度，並且提高製造成本。
根據本發明之一個態樣，其提供一種製造半導體裝置的方法，其包括：提供一可穿透膜層；設置一半導體晶粒或構件在該可穿透膜層的一貼附區上方，該半導體晶粒或構件的一部分被埋置在該可穿透膜層中；形成一導體層在該可穿透膜層的上方；沉積一囊封劑在該可穿透膜層、導體層、以及半導體晶粒或構件的上方；形成一屏蔽層在該囊封劑的上方；以及移除該可穿透膜層。
根據本發明之另一個態樣，其提供一種製造半導體裝置的方法，其包括：提供一可穿透層；設置一電氣構件在該可穿透層的一貼附區上方，該電氣構件的一部分被埋置在該可穿透層中；沉積一囊封劑在該可穿透層以及電氣構件的上方；以及形成一屏蔽層在該囊封劑的上方。
根據本發明之另一個態樣，其提供一種半導體裝置，其包括：一基板；一電氣構件，被設置在該基板的一貼附區上方；一囊封劑，被沉積在該基板和電氣構件上方；以及一屏蔽層，被形成在該囊封劑上方。
100‧‧‧半導體晶圓
102‧‧‧基板材料
104‧‧‧半導體晶粒或構件
106‧‧‧切割道
108‧‧‧背表面或非主動表面
110‧‧‧主動表面
112‧‧‧導電層
114‧‧‧凸塊
118‧‧‧鋸片或雷射切割工具
120‧‧‧載板或暫時性基板
122‧‧‧介面層或雙面膠帶
124‧‧‧可穿透膜層
126‧‧‧重組晶圓
130‧‧‧電子構件
136‧‧‧電氣互連線
140a‧‧‧構件貼附區
140b‧‧‧構件貼附區
140c‧‧‧構件貼附區
140d‧‧‧構件貼附區
142‧‧‧導電層
144‧‧‧構件貼附區之間的膜層區域
146‧‧‧囊封劑或模製化合物
148‧‧‧鋸片或雷射切割工具
150‧‧‧系統級模組封裝
154‧‧‧屏蔽層
156‧‧‧囊封劑主要表面
158‧‧‧囊封劑側表面
160‧‧‧軌跡線
166‧‧‧囊封劑或模製化合物
168‧‧‧重組晶圓
169‧‧‧鋸片或雷射切割工具
170‧‧‧系統級模組封裝
174‧‧‧屏蔽層
176‧‧‧囊封劑主要表面
178‧‧‧囊封劑側表面
179‧‧‧導體層側表面
190‧‧‧系統級模組封裝
192‧‧‧底層填充或絕緣材料
200‧‧‧電子構件
202‧‧‧晶片載體基板或PCB
204‧‧‧導體訊號線路
206‧‧‧焊線封裝
208‧‧‧覆晶
210‧‧‧球柵陣列(BGA)
212‧‧‧凸塊晶片載體(BCC)
216‧‧‧平台格柵陣列(LGA)
218‧‧‧多晶片模組(MCM)
220‧‧‧方形扁平無導線封裝(QFN)
222‧‧‧方形扁平封裝
224‧‧‧嵌入式晶圓級球柵陣列(eWLB)
226‧‧‧晶圓級晶片規模封裝(WLCSP)
圖1a至1c所示的係具有由切割道分離之複數個半導體晶粒的半導體晶圓； 圖2a至2o所示的係形成系統級模組封裝的製程，在一可穿透膜層上方具有一屏蔽層；圖3a至3b所示的係圖2a至2o中被形成在一可穿透膜層上方的系統級模組封裝；圖4a至4c所示的係形成系統級模組封裝的另一製程，在一可穿透膜層上方具有一屏蔽層；圖5所示的係圖4a至4c中被形成在一可穿透膜層上方的系統級模組封裝；圖6所示的係在該些電氣構件下方有底層填充材料的系統級模組封裝的另一實施例；以及圖7圖解一印刷電路板(Printed Circuit Board，PCB)，有不同類型的封裝被鑲嵌至該PCB的表面。
在下面的說明中參考圖式於一或更多個實施例中說明本發明，於該些圖式中，相同的符號代表相同或類似的元件。雖然本文以達成本發明之目的的最佳模式來說明本發明；不過，熟習本技術的人士便明白，本發明希望涵蓋受到下面揭示內容及圖式支持的隨附申請專利範圍及其等效範圍所定義的本發明的精神與範疇內可以併入的替代例、修正例、以及等效例。本文中所使用的「半導體晶粒」一詞兼具單數和複數形式，且據此，能夠表示單一半導體裝置以及多個半導體裝置兩者。
半導體裝置通常使用兩種複雜的製程來製造：前端製造以及後端製造。前端製造涉及在一半導體晶圓的表面上形成複數個晶粒。該晶圓上的每一個晶粒含有主動式電構件和被動式電構件，它們被電氣連接而形成有功能的電路。主動式電構件(例如，電晶體和二極體)能夠控制電流的流動。被動式電構 件(例如，電容器、電感器、以及電阻器)創造用以實施電路功能所需要的電壓和電流之間的關係。
後端製造係指將已完成的晶圓切割或單體化裁切成獨特的半導體晶粒並且封裝該半導體晶粒以便提供結構性支撐、電氣互連、以及環境隔離。為單體化裁切半導體晶粒，該晶圓會沿著晶圓中被稱為切割道(saw street)或切割線(scribe)的非功能性區域被劃線並且折斷。該晶圓會利用雷射切割工具或鋸片被單體化裁切。經過單體化裁切之後，獨特的半導體晶粒會被鑲嵌至包含接針或接觸墊的封裝基板，以便和其它系統構件進行互連。被形成在該半導體晶粒上方的接觸墊接著會被連接至該封裝裡面的接觸墊。該些電氣連接線可利用導體層、凸塊、短柱凸塊、導體膏、或是焊線來製成。一囊封劑或是其它模製材料會被沉積在該封裝的上方，用以提供物理性支撐和電氣隔離。接著，已完成的封裝便會被插入一電氣系統之中並且讓其它系統構件可取用該半導體裝置的功能。
圖1a顯示一具有基礎基板材料102(例如，矽、鍺、磷化鋁、砷化鋁、砷化鎵、氮化鎵、磷化銦、碳化矽、或是用於結構性支撐的其它本體材料)的半導體晶圓100。複數個半導體晶粒或構件104會被形成在晶圓100上，藉由非主動的晶粒間晶圓區域或切割道106來分離。切割道106提供切割區，以便將半導體晶圓100單體化裁切成獨特的半導體晶粒104。於其中一實施例中，半導體晶圓100的寬度或直徑為100至450毫米(mm)。
圖1b所示的係半導體晶圓100的一部分的剖視圖。每一個半導體晶粒104有一背表面或非主動表面108以及含有類比電路或數位電路的主動表面110，該些類比電路或數位電路會被施行為根據該晶粒的電氣設計與功能被形成在該晶粒裡面及電氣互連的主動裝置、被動裝置、導體層、以及介電層。舉例來說，該電路可以包含被形成在主動表面110裡面的一或更多個電晶體、二極 體、以及其它電路元件，用以施行類比電路或數位電路，例如，數位訊號處理器(Digital Signal Processor，DSP)、特定應用積體電路(Application Specific Integrated Circuit，ASIC)、記憶體、或是其它訊號處理電路。半導體晶粒104可以還含有用於RF訊號處理的IPD，例如，電感器、電容器、以及電阻器。
一導電層112使用PVD、CVD、電解質電鍍、無電極電鍍製程、或是其它合宜的金屬沉積製程被形成在主動表面110的上方。導體層112能夠係由下面所製成的一或更多層：鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、或是其它合宜的導體材料。導體層112的操作如同被電氣連接至主動表面110上之電路的接觸墊。
一導電凸塊材料會利用下面製程被沉積在導體層112上方：蒸發製程、電解電鍍製程、無電極電鍍製程、丸滴製程、或是網印製程。該凸塊材料能夠係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及它們的組合，其會有一非必要的助熔溶液。舉例來說，該凸塊材料能夠是Sn/Pb共熔合金、高鉛焊料、或是無鉛焊料。該凸塊材料會利用合宜的附著或焊接製程被焊接至導體層112。於其中一實施例中，該凸塊材料會藉由將該材料加熱至其熔點以上而被回焊，用以形成球體或凸塊114。於其中一實施例中，凸塊114係被形成在具有一濕潤層、屏障層、以及黏著層的凸塊下層金屬(Under Bump Metallization，UBM)的上方。凸塊114亦能夠被壓縮焊接或熱壓縮焊接至導體層112。凸塊114代表能夠被形成在導體層112上方的其中一種類型互連結構。該互連結構亦能夠使用焊線、導體膏、短柱凸塊、微凸塊、或是其它電氣互連線。
在圖1c中，半導體晶圓100會利用鋸片或雷射切割工具118被單體化裁切成半導體晶粒104。獨特的半導體晶粒104會經過檢查並和電氣測試，以便找出單體化裁切後的KGD(已知良好晶粒)。
圖2a至2o圖解在可穿透膜層上方形成系統級模組封裝的製程。圖 2a所示的係一載板或暫時性基板120的一部分的剖視圖，該載板或暫時性基板120含有犧牲性基礎材料，例如，矽、聚合物、氧化鈹、玻璃、或是用於達到結構性支撐之目的的其它合宜低成本剛性材料。載板120能夠根據半導體封裝的設計或功能而為圓形或矩形。一介面層或雙面膠帶122被形成在載板120上方成為一暫時性膠黏膜層、蝕刻阻止層、或是熱脫模層。於其中一實施例中，介面層122包含聚醯亞胺或聚丙烯酸系膜。
一可穿透膜層124利用PVD、CVD、印刷、旋塗、噴塗、狹縫塗佈、滾塗、層疊、或是燒結被形成在載板120上方。於其中一實施例中，膜層124係聚合物、環氧樹脂、基於丙烯酸的B階材料、或是具有可穿透特性的其它類似材料。膜層124的厚度為125微米(μm)。或者，膜層124能夠為由下面所製成的一或更多層：二氧化矽(SiO2)、氮化矽(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、三氧化二鋁(Al2O3)、聚亞醯胺、環苯丁烯(BCB)、聚苯并噁唑纖維(PBO)、或是具有類似絕緣特性和結構特性的其它材料。膜層124的操作如同用以附接電子構件的暫時性可穿透基板。
在圖2b中，圖1c中的半導體晶粒104利用拾放操作被定位在可穿透膜層124上方並且被貼附至可穿透膜層124，主動表面110和凸塊114朝向該膜層。同樣地，離散式電子構件130亦被定位在可穿透膜層124上方並且被貼附至可穿透膜層124。於其中一實施例中，離散式電子構件130為半導體裝置或IPD，例如，電阻器、電容器、以及電感器。凸塊、導電膏、或是其它電氣互連線136為離散式電子構件130提供電氣互連。一部分的半導體晶粒104，舉例來說，凸塊114，以及一部分的離散式電子構件130，舉例來說，電氣互連線136，被埋置在膜層124中。或者，半導體晶粒104的主動表面110上的導電層112以及離散式電子構件130的連接終端穿透至膜層124之中。膜層124具有低黏性，允許凸塊114、電氣互連線136、以及半導體晶粒104和離散式電子構件130的連接終端穿 透至該膜層之中。
圖2c所示的係沿著圖2d的直線2c至2c貫穿取得之被貼附至可穿透膜層124的半導體晶粒104和離散式電子構件130而成為重組晶圓126的剖視圖。於其中一實施例中，僅有離散式電子構件130被貼附至可穿透膜層124。
圖2d所示的係在重組晶圓126的構件貼附區140中被貼附至膜層124的半導體晶粒104和離散式電子構件130的多個實例的平面圖。第一群半導體晶粒104和離散式電子構件130被設置在構件貼附區140a中，第二群半導體晶粒104和離散式電子構件130被設置在構件貼附區140b中，第三群半導體晶粒104和離散式電子構件130被設置在構件貼附區140c中，以及第四群半導體晶粒104和離散式電子構件130被設置在構件貼附區140d中。
於另一實施例中，半導體晶粒104利用拾放操作被定位在載板120的介面層122上方並且被貼附至介面層122，主動表面110朝向該膜層，參見圖2e。同樣地，離散式電子構件130亦被定位在介面層122上方並且被貼附至介面層122。半導體晶粒104的一表面和離散式電子構件130的一表面接觸介面層122。於又一實施例中，不含凸塊114的半導體晶粒104以及不含電氣互連線136的離散式電子構件130被設置在可穿透膜層124上，也就是，半導體晶粒104的一表面和離散式電子構件130的一表面接觸該可穿透膜層，如圖2f中所示，回到圖2c，一導電層142會使用PVD、CVD、電解質電鍍、無電極電鍍製程、或是其它合宜的金屬沉積製程被形成在一部分構件貼附區140a至140d上方以及膜層124的該些構件貼附區之間的一部分區域144上方，如圖2g中所示。導體層142能夠係由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導體材料。導體層142被排列在構件貼附區140a至140d的角邊處。該些導體層部分142能夠相依於半導體晶粒104和離散式電子構件130的設計與功能而被電氣隔離或是為共電。圖2h所示的係導體層142的平面圖，其覆蓋 一部分構件貼附區140a至140d並且重疊置在該些構件貼附區之間的膜層124的一部分區域144。
圖2i圖解的係被形成在構件貼附區140a至140d的角邊和圍繞每一側的多個導體層部分142的另一實施例。該些獨特的導體層部分142能夠相依於半導體晶粒104和離散式電子構件130的設計與功能而被電氣隔離或是為共電。圖2j圖解以圓形形狀被形成在構件貼附區140a至140d的角邊的導體層142的另一實施例。
在圖2k中，一囊封劑或模製化合物146會利用焊膏印刷(paste printing)塗敷機、壓縮模製(compressive molding)塗敷機、轉印模製(transfer molding)塗敷機、液體囊封劑模製塗敷機、真空層疊塗敷機、旋塗塗敷機、或是其它合宜的塗敷機被沉積在半導體晶粒104、離散式電子構件130、膜層124、以及一部分的導體層142的上方。囊封劑146能夠為聚合物合成材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯、或是具有適當填充劑的聚合物。囊封劑146係非導體、提供結構性支撐、並且為該半導體裝置提供環境保護，避免受到外部元素與污染物的破壞。於其中一實施例中，囊封劑146覆蓋半導體晶粒104和離散式電子構件130的頂端表面和側表面以及該半導體晶粒和離散式電子構件與膜層124之間的頂端表面和側表面。圖2l顯示一囊封劑146的平面圖，其覆蓋重組晶圓126上的構件貼附區140a至140d以及一部分的導體層142。
在圖2m中，重組晶圓126會利用鋸片或雷射切割工具148被單體化裁切貫穿區域144，成為多個獨特的系統級模組封裝150。圖2n顯示系統級模組封裝150，舉例來說，含有被設置在構件貼附區140a中的第一群半導體晶粒104和離散式電子構件130。一部分的導體層142橫向延伸在囊封劑146外面，因為該導體層重疊該些構件貼附區140a至140b之間的膜層124的一部分區域144。
半導體晶粒104和離散式電子構件130可能含有易受到EMI、 RFI、諧波失真、以及裝置間干擾影響的IPD。舉例來說，半導體晶粒104和離散式電子構件130內含有的IPD提供高頻應用所需要的電氣特徵，例如，諧振器、高通濾波器、低通濾波器、帶通濾波器、對稱性高Q值諧振變壓器、以及調諧電容器。
為降低EMI和RFI的效應，屏蔽層154被形成在囊封劑146的主要表面156和側表面158上方，如圖2o中所示。屏蔽層154能夠係由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導體材料。或者，屏蔽層154亦能夠為羰基鐵、不鏽鋼、鎳銀合金、低碳鋼、矽鐵鋼、金屬箔、導體樹脂、碳黑、鋁片、以及能夠降低EMI、RFI、以及其它裝置間干擾的其它金屬和合成物。屏蔽層154被電氣連接至導體層142成為系統級模組封裝150的一外部接地點，用以減少EMI和RFI對半導體晶粒104和離散式電子構件130的影響。
暫時性載板120、介面層122、以及可穿透膜層124會藉由化學性蝕刻、機械性剝除、CMP、機械性研磨、熱烘烤、紫外(UV)光、雷射掃描、或是濕式脫除被移除，以便露出半導體晶粒104的凸塊114以及離散式電子構件130的電氣互連線136或是該半導體晶粒與離散式電子構件的其它連接終端。載板120、介面層122、以及可穿透膜層124會在圖2m中單體化裁切之前先被移除。
圖3a圖解以屏蔽層154覆蓋囊封劑146的主要表面156和側表面158的系統級模組封裝150。屏蔽層154電氣接觸導體層142成為一外部接地點，用以減少EMI和RFI對系統級模組封裝150的影響。半導體晶粒104和離散式電子構件130剛開始被貼附至膜層124，凸塊114和電氣互連線136被埋置在該膜層裡面。半導體晶粒104和離散式電子構件130被囊封劑146覆蓋。當膜層124被移除時，半導體晶粒104和離散式電子構件130繼續受到系統級模組封裝150裡面的囊封劑146支撐，沒有基板。凸塊114和電氣互連線136會在移除載板120、介面層122、以及膜層124之後被形成。如果半導體晶粒104的一表面和離散式電子構件 130的一表面被設置在介面層122或可穿透膜層124上的話，參見圖2e和2f，凸塊114和電氣互連線136會在形成屏蔽層154之後被形成，或者在移除載板120、介面層122、以及膜層124之後被形成。
圖3b顯示系統級模組封裝150的仰視圖，凸塊114和電氣互連線136從囊封劑146處露出，以便達成外部電氣互連。或者，半導體晶粒104和離散式電子構件130的連接終端從囊封劑146處露出，以便達成外部電氣互連。軌跡線160被形成在囊封劑146上方並且在導體層142和凸塊114和電氣互連線136之間提供電氣連接。在可移除膜層124上方形成系統級模組封裝150的過程，沒有基板，會提供較高的設計彈性、較低的輪廓、減少缺陷和失效、並且降低製造成本。
於接續圖2g的另一實施例中，一囊封劑或模製化合物166會利用焊膏印刷塗敷機、壓縮模製塗敷機、轉印模製塗敷機、液體囊封劑模製塗敷機、真空層疊塗敷機、旋塗塗敷機、或是其它合宜的塗敷機被沉積在半導體晶粒104、離散式電子構件130、膜層124、以及一部分的導體層142的上方，如圖4a中所示。囊封劑166能夠為聚合物合成材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯、或是具有適當填充劑的聚合物。囊封劑166係非導體、提供結構性支撐、並且為該半導體裝置提供環境保護，避免受到外部元素與污染物的破壞。於其中一實施例中，囊封劑166覆蓋半導體晶粒104和離散式電子構件130的頂端表面和側表面以及該半導體晶粒和離散式電子構件與膜層124之間的頂端表面和側表面。
在圖4b中，重組晶圓168會利用鋸片或雷射切割工具169被單體化裁切貫穿區域144，成為多個獨特的系統級模組封裝170。
半導體晶粒104和離散式電子構件130可能含有易受到EMI、RFI、諧波失真、以及裝置間干擾影響的IPD。舉例來說，半導體晶粒104和離散 式電子構件130內含有的IPD提供高頻應用所需要的電氣特徵，例如，諧振器、高通濾波器、低通濾波器、帶通濾波器、對稱性高Q值諧振變壓器、以及調諧電容器。
為降低EMI和RFI的效應，屏蔽層174被形成在囊封劑166的主要表面176和側表面178上方以及系統級模組封裝170的導體層142的側表面179上方，如圖4c中所示。屏蔽層174能夠係由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導體材料。或者，屏蔽層174亦能夠為羰基鐵、不鏽鋼、鎳銀合金、低碳鋼、矽鐵鋼、金屬箔、導體樹脂、碳黑、鋁片、以及能夠降低EMI、RFI、以及其它裝置間干擾的其它金屬和合成物。屏蔽層174被電氣連接至導體層142成為系統級模組封裝170的一外部接地點，用以減少EMI和RFI對半導體晶粒104和離散式電子構件130的影響。
暫時性載板120和介面層122會藉由化學性蝕刻、機械性剝除、CMP、機械性研磨、熱烘烤、紫外(UV)光、雷射掃描、或是濕式脫除被移除，以便露出半導體晶粒104的凸塊114以及離散式電子構件130的電氣互連線136或是該半導體晶粒與離散式電子構件的其它連接終端。載板120、介面層122、以及可穿透膜層124會在圖4b中單體化裁切之前先被移除。
圖5圖解以屏蔽層174覆蓋囊封劑166的主要表面176和側表面178以及導體層142的側表面179的系統級模組封裝170。屏蔽層174電氣接觸導體層142成為一外部接地點，用以減少EMI和RFI對系統級模組封裝170的影響。半導體晶粒104和離散式電子構件130剛開始被貼附至膜層124，凸塊114和電氣互連線136被埋置在該膜層裡面。半導體晶粒104和離散式電子構件130被囊封劑166覆蓋。當膜層124被移除時，半導體晶粒104和離散式電子構件130繼續受到系統級模組封裝170裡面的囊封劑166支撐，沒有基板。凸塊114和電氣互連線136會在移除載板120、介面層122、以及膜層124之後被形成。如果半導體晶粒104的 一表面和離散式電子構件130的一表面被設置在介面層122或可穿透膜層124上的話，參見圖2e和2f，凸塊114和電氣互連線136會在形成屏蔽層174之後被形成，或者在移除載板120、介面層122、以及膜層124之後被形成。
圖6圖解系統級模組封裝190的另一實施例，類似於圖5，底層填充或絕緣材料192(例如，環氧樹脂)被沉積圍繞半導體晶粒104的凸塊114並且圍繞離散式電子構件130的電氣互連線136。
圖7圖解具有一晶片載體基板或PCB 202的電子構件200，在PCB 202的一表面上鑲嵌複數個半導體封裝，包含系統級模組封裝150和170。電子裝置200會有單一種類型半導體封裝，或是多種類型的半導體封裝，端視應用而定。
電子裝置200能夠係單機型系統，其使用該些半導體封裝來實施一或更多項電氣功能。或者，電子裝置200亦能夠係一較大型系統中的子構件。舉例來說，電子裝置200能夠係平板、蜂巢式電話、數位相機、通訊系統、或是其它電子裝置的一部分。或者，電子裝置200能夠係圖形卡、網路介面卡、或是能夠被插入電腦之中的其它訊號處理卡。該半導體封裝能夠包含：微處理器、記憶體、ASIC、邏輯電路、類比電路、RF電路、離散式裝置、或是其它半導體晶粒或電氣構件。產品要被市場接受，微型化以及減輕重量相當重要。半導體裝置之間的距離可能要縮減，以便達到更高密度的目的。
在圖7中，PCB 202提供一種通用基板，用以達到結構性支撐以及電氣互連被鑲嵌在該PCB上的半導體封裝的目的。多條導體訊號線路204會利用下面製程被形成在PCB 202的一表面上方或是多層裡面：蒸發製程、電解電鍍製程、無電極電鍍製程、網印製程、或是其它合宜的金屬沉積製程。訊號線路204在該些半導體封裝、被鑲嵌的構件、以及其它外部系統構件中的每一者之間提供電氣通訊。線路204亦提供連接至每一個該些半導體封裝的電力連接線及接地連接線。
於某些實施例中，一半導體裝置會有兩個封裝層。第一層封裝係一種用於以機械方式及電氣方式將該半導體晶粒附接至一中間基板的技術。第二層封裝則涉及以機械方式及電氣方式將該中間基板附接至該PCB。於其它實施例中，一半導體裝置可以僅有該第一層封裝，其中，該晶粒以機械方式及電氣方式直接被鑲嵌至該PCB。
為達解釋的目的，圖中在PCB 202上顯示數種類型的第一層封裝，其包含焊線封裝206以及覆晶208。除此之外，圖中還顯示被鑲嵌在PCB 202上的數種類型第二層封裝，其包含：球柵陣列(Ball Grid Array，BGA)210；凸塊晶片載體(Bump Chip Carrier，BCC)212；平台格柵陣列(Land Grid Array，LGA)216；多晶片模組(Multi-Chip Module，MCM)218；方形扁平無導線封裝(Quad Flat Non-leaded package，QFN)220；方形扁平封裝222；嵌入式晶圓級球柵陣列(embedded Wafer Level Ball grid array，eWLB)224；以及晶圓級晶片規模封裝(Wafer Level Chip Scale Package，WLCSP)226。於其中一實施例中，eWLB 224係一扇出型晶圓級封裝(Fan-out Wafer Level Package，Fo-WLP)，而WLCSP 226係一扇入型晶圓級封裝(Fan-in Wafer Level Package，Fi-WLP)。端視系統需求而定，由被配置成具有第一層封裝樣式和第二層封裝樣式之任何組合的半導體封裝和其它電子組件所組成的任何組合皆能夠被連接至PCB 202。於某些實施例中，電子裝置200包含單一附接半導體封裝；不過，其它實施例則會需要多個互連封裝。藉由在單一基板上方組合一或更多個半導體封裝，製造商便能夠將事先製造的構件併入電子裝置和系統之中。因為該些半導體封裝包含精密的功能，所以，電子裝置能夠使用較便宜的構件以及有效率的製程來製造。所產生的裝置比較不可能失效而且製造價格較低廉，從而降低消費者的成本。
本文雖然已經詳細解釋本發明的一或更多個實施例；不過，熟習的技術人士便會明白可以對該些實施例進行修正與改變，其並不會脫離下面申 請專利範圍中所提出之本發明的範疇。
104‧‧‧半導體晶粒或構件
108‧‧‧背表面或非主動表面
110‧‧‧主動表面
112‧‧‧導電層
114‧‧‧凸塊
130‧‧‧電子構件
136‧‧‧電氣互連線
142‧‧‧導電層
150‧‧‧系統級模組封裝
154‧‧‧屏蔽層
156‧‧‧囊封劑主要表面
158‧‧‧囊封劑側表面

Claims (14)

  1. 一種製造半導體裝置的方法，其包括：提供一可穿透膜層；設置一半導體晶粒或構件到該可穿透膜層的一貼附區上，該半導體晶粒或構件的一導電部分被埋置在該可穿透膜層之中；形成一導體層以接觸該可穿透膜層，其中該導體層在該可穿透膜層的該貼附區之中且在該半導體晶粒下方而延伸於該可穿透膜層的第一部分上方以接觸該半導體晶粒的導電部分，並且該導體層進一步在該可穿透膜層的第二部分上方之該可穿透膜層的貼附區之外側；沉積一囊封劑在該可穿透膜層、導體層、以及半導體晶粒或構件的上方；形成一電磁屏蔽層在該囊封劑的頂表面和側表面上，而該電磁屏蔽層在該囊封劑的該側表面上延伸以接觸該導體層；以及在形成該電磁屏蔽層之後，移除該可穿透膜層以曝露該半導體晶粒或構件的該導電部分。
  2. 根據申請專利範圍第1項的方法，其中被埋置在該可穿透膜層之中的該半導體晶粒或構件的該導電部分包括多個凸塊。
  3. 根據申請專利範圍第1項的方法，其中，該導體層延伸在該囊封劑外面。
  4. 根據申請專利範圍第1項的方法，其中，該電磁屏蔽層被電氣連接至該導體層。
  5. 根據申請專利範圍第1項的方法，其進一步包含設置一絕緣材料於該半導體晶粒或構件的下方。
  6. 根據申請專利範圍第1項的方法，其中，該半導體晶粒或構件包含一整合式被動裝置。
  7. 一種製造半導體裝置的方法，其包括：提供一可穿透基板；設置一電氣構件到該可穿透基板的一貼附區上，該電氣構件的導電部分被埋置在該可穿透基板中；形成導體層以接觸該可穿透基板，其中該導體層在該可穿透基板的該貼附區之中且在該電氣構件下方而延伸於該可穿透基板的第一部分上方以接觸該電氣構件的該導電部分，並且該導體層進一步在該可穿透基板的第二部分上方之該可穿透基板的貼附區之外側；在設置該電氣構件到該可穿透基板的該貼附區上之後，沉積一囊封劑在該可穿透基板以及電氣構件的上方；形成一電磁屏蔽層在該囊封劑的上方，其中該電磁屏蔽層接觸該導體層；以及在形成該屏蔽層之後，移除該可穿透基板以曝露該電氣構件的該導電部分。
  8. 根據申請專利範圍第7項的方法，其中該電磁屏蔽層是電性連接到該導體層。
  9. 根據申請專利範圍第7項的方法，其進一步包含設置一絕緣材料於該電氣構件下方。
  10. 根據申請專利範圍第7項的方法，其中，該電氣構件包括整合式被動裝置。
  11. 一種製造半導體裝置的方法，其包括：提供一基板；設置一電氣構件到該基板的一貼附區上，而該電氣構件的導電部分被埋置到該基板之中；在該基板上方形成導體層，其中該導體層在該基板的該貼附區之中且在該 電氣構件下方而延伸於該基板的第一部分上方以接觸該電氣構件的該導電部分，並且該導體層進一步在該基板的第二部分上方之該基板的貼附區之外側；在設置該電氣構件到該基板的該貼附區上之後，沉積一囊封劑於該基板和電氣構件上方；形成一屏蔽層於該囊封劑上方，其中該屏蔽層接觸該導體層；以及在形成該屏蔽層之後，移除該基板以曝露該電氣構件的該導電部分。
  12. 根據申請專利範圍第11項的方法，其中，被埋置在該基板之中的該電氣構件的該導電部分包括多個凸塊。
  13. 根據申請專利範圍第11項的方法，其中，該屏蔽層被電氣連接至該導體層。
  14. 根據申請專利範圍第11項的方法，其進一步包含一絕緣材料，被設置在該電氣構件的下方。
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US20180269195A1 (en) 2018-09-20
US11309193B2 (en) 2022-04-19
KR20210019472A (ko) 2021-02-22
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US10804119B2 (en) 2020-10-13
US20200402817A1 (en) 2020-12-24
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KR20230107754A (ko) 2023-07-18

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