TWI716203B - 半導體結構及其製造方法 - Google Patents

半導體結構及其製造方法 Download PDF

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TWI716203B
TWI716203B TW108142627A TW108142627A TWI716203B TW I716203 B TWI716203 B TW I716203B TW 108142627 A TW108142627 A TW 108142627A TW 108142627 A TW108142627 A TW 108142627A TW I716203 B TWI716203 B TW I716203B
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wafer
dielectric layer
landing pad
chip
bonding
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TW202116130A (zh
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丘世仰
羅翊仁
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南亞科技股份有限公司
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Abstract

一種半導體結構包括第一晶片、第二晶片及第一導電通孔。第一晶片包括第一介電層和嵌入在第一介電層中的第一著陸墊。第二晶片包括第二介電層和嵌入在第二介電層中的第二著陸墊。第一晶片設置在第二晶片上。第二著陸墊具有通孔。第一導電通孔從第一著陸墊延伸向第二著陸墊,並穿過第二著陸墊的通孔。

Description

半導體結構及其製造方法
本揭示內容關於一種半導體結構及其製造方法。更具體地,本揭示內容關於一種包括貫穿著陸墊的通孔的導電通孔的半導體結構及其製造方法。
半導體工業的主要趨勢之一是最小化半導體裝置的尺寸。在諸如多晶片封裝的半導體裝置封裝中,對微型化的需求特別高。例如,多晶片封裝包括積體電路和用塑料樹脂或陶瓷材料密封的精細圖案印刷電路。最小化封裝中包括的積體電路的尺寸是封裝技術人員的主要目標之一。
本揭示內容提供一種半導體結構,包括第一晶片、第二晶片及第一導電通孔。第一晶片包括第一介電層和嵌入在第一介電層中的第一著陸墊。第二晶片包括第二介電層和嵌入在第二介電層中的第二著陸墊。第一晶片設置在第二晶片上。第二著陸墊具有通孔。第一導電通孔從第一著陸 墊延伸向第二著陸墊,並穿過第二著陸墊的通孔。
在一些實施方式中,第一導電通孔藉由第二介電層與第二著陸墊分離。
在一些實施方式中,第一晶片是從晶片。
在一些實施方式中,第二晶片是從晶片。
在一些實施方式中,半導體結構還包括設置在第二晶片下方的第三晶片,其中第三晶片包括在第三晶片的下表面上的第一凸塊,第一導電通孔延伸穿過第三晶片以與第一凸塊連接。
在一些實施方式中,第三晶片是主晶片。
在一些實施方式中,半導體結構還包括第二導電通孔,第二導電通孔從第二著陸墊延伸進入第三晶片,其中第三晶片還包括在第三晶片的下表面上的第二凸塊,並且第二導電通孔與第二凸塊連接。
在一些實施方式中,第三晶片包括第三介電層和第一接合層,並且第一接合層設置在第三介電層和第二晶片之間。
在一些實施方式中,第二晶片還包括第二接合層,第二接合層設置在第二介電層與第一接合層之間。
在一些實施方式中,第一晶片還包括設置在第一介電層和第二晶片之間的第一接合層。
在一些實施方式中,第二晶片還包括設置在第二介電層和第一晶片之間的一第二接合層。
本揭示內容提供一種用於製造半導體結構的方法。方法包括以下步驟。接合第一晶片與第二晶片,其中第一晶片設置在第二晶片上,第一晶片包括第一介電層和嵌入在第一介電層中的第一著陸墊。第二晶片包括第二介電層和嵌入在第二介電層中的第二著陸墊。第二著陸墊具有通孔,第二介電層的一部份填滿於第二著陸墊的通孔。形成第一孔穿過第一晶片及第二晶片的第二介電層的部分,以暴露第一著陸墊。形成第一導電通孔於第一孔中。
在一些實施方式中,在形成第一孔之前,方法還包括將第三晶片與第二晶片接合,其中第三晶片設置在第二晶片下方,其中形成第一孔包括形成第一孔穿過第三晶片。
在一些實施方式中,形成第二孔穿過第二晶片及第三晶片以暴露第二著陸墊。形成第二導電通孔於第二孔中。
在一些實施方式中,藉由一直接接合製程接合第三晶片與第二晶片。
在一些實施方式中,方法還包括形成第一凸塊於第三晶片的下表面上,其中第一凸塊與第一導電通孔連接。
在一些實施方式中,在將第一晶片與第二晶片接合之前,方法還包括形成第二晶片。形成第二晶片包括以下步驟。在第三介電層上形成導電層。對導電層進行圖案化 以形成具有通孔的第二著陸墊。形成第四介電層以覆蓋第二著陸墊和第三介電層。
在一些實施方式中,形成第四介電層包括以下步驟。形成第五介電層以覆蓋第二著陸墊和第三介電層。去除第五介電層的一部分以暴露出第二著陸墊的上表面。形成第六介電層以覆蓋第二著陸墊及第五介電層。
在一些實施方式中,藉由直接接合製程接合第一晶片與第二晶片。
在一些實施方式中,第一晶片包括第一接合層,第二晶片包括第二接合層,接合第一晶片與第二晶片包括接合第一晶片的第一接合層及第二晶片的第二接合層。
應該理解的是,前述的一般性描述和下列具體說明僅僅是示例性和解釋性的,並旨在提供所要求的本發明的進一步說明。
100:半導體結構
110:第一晶片
110a:第一介電層
110b:第一著陸墊
110c:接合層
120:第二晶片
120a:第二介電層
120b:第二著陸墊
120c:接合層
120d:接合層
120e:第二著陸墊
130:第三晶片
130a:第三介電層
130b:接合層
200:半導體結構
710:載體
720:離型膜
740:介電層
810:導電層
1000、1200:介電層
h:通孔
H1:第一孔
H2:第二孔
B1:第一凸塊
B2:第二凸塊
S1:下表面
V1:第一導電通孔
V2:第二導電通孔
本揭示內容上述和其他態樣、特徵及其他優點參照說明書內容並配合附加圖式得到更清楚的瞭解,其中:第1A圖是示意性示出根據本揭示內容的一些實施例的半導體結構的截面圖。
第1B圖是示意性地示出根據本揭示內容的一些實施例的沿線A-A'的第1A圖中的半導體結構的截面圖。
第2圖是示意性地示出本揭示內容的比較例的半導體結構的截面圖。
第3-6圖是根據本揭示內容的一些實施例的用於在各個階段製造半導體結構的方法的截面圖。
第7-13圖是根據本揭示內容的一些實施例的用於在各個階段製造晶片的方法的截面圖。
為了使本揭示內容之敘述更加詳盡與完備,可參照所附之圖式及以下所述各種實施例,圖式中相同之號碼代表相同或相似之元件。
以下將以圖式揭露本發明之複數個實施方式,為明確說明起見,許多實務上的細節將在以下敘述中一併說明。然而,應瞭解到,這些實務上的細節不應用以限制本發明。也就是說,在本發明部分實施方式中,這些實務上的細節是非必要的。此外,為簡化圖式起見,一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。
本揭示內容提供了一種半導體結構。第1A圖是示意性示出根據本揭示內容的一些實施例的半導體結構100的截面圖。半導體結構100包括第一晶片110、第二晶片120、第三晶片130、第一導電通孔V1、第二導電通孔V2、第一凸塊B1,以及第二凸塊B2。第一晶片110設置在第二晶片120上。第三晶片130設置在第二晶片120下。第 一晶片110包括第一介電層110a及嵌入在第一介電層110a中的第一著陸墊110b。第二晶片120包括第二介電層120a及嵌入在第二介電層120a中的第二著陸墊120b。第三晶片130包括第三介電層130a。第一凸塊B1及第二凸塊B2設置在第三晶片130的下表面S1上。第一導電通孔V1從第一著陸墊110b延伸向第二著陸墊120b,且穿過第二著陸墊120b的通孔h。例如,通孔h的直徑可以小於20μm。並且,第一導電通孔V1延伸穿過第三晶片130以與第一凸塊B1連接。此外,第二導電通孔V2從第二著陸墊120b延伸到第三晶片130中,以與第三晶片130的下表面S1上的第二凸塊B2連接。
在一些實施例中,第一導電通孔V1、第二導電通孔V2、第一著陸墊110b和第二著陸墊120b分別包括銅、金、鎢或其合金。在一些實施例中,第一介電層110a、第二介電層120a和第三介電層130a分別包括二氧化矽(SiO2)、氮化矽(SiN)、氧化矽-氧氮化矽-氧化矽(ONO)或其組合。
在一些實施例中,第一晶片110是從晶片。在一些實施例中,第二晶片120是從晶片。在一些實施例中,第三晶片130是主晶片。信號可以經由第一導電通孔V1從第三晶片130傳輸到第一晶片110,並且可以經由第二導電通孔V2從第三晶片130傳輸到第二晶片120。
在一些實施例中,第一晶片110與第二晶片120 直接接合。在一些實施例中,第一晶片110藉由氧化物熔融接合與第二晶片120接合。在一些實施例中,如第1A圖所示,第一晶片110包括設置在第一介電層110a與第二晶片120之間的接合層110c。第一晶片110藉由接合層110c與第二晶片120接合。在一些實施例中,如第1A圖所示,第二晶片120包括設置在第二介電層120a與第一晶片110之間的接合層120c。第一晶片110藉由接合層120c接合至第二晶片120。在一些實施例中,接合層110c和接合層120c是氧化物層。在一些其他實施例中,第一介電層110a與第二介電層120a直接接觸。
在一些實施例中,第二晶片120與第三晶片130直接接合。在一些實施例中,第二晶片120藉由氧化物熔融結合與第三晶片130接合。在一些實施例中,如第1A圖所示,第三晶片130包括設置在第三介電層130a與第二晶片120之間的接合層130b。第二晶片120藉由接合層130b接合至第三晶片130。在一些實施例中,如第1A圖所示,第二晶片120包括設置在第二介電層120a與接合層130b之間的接合層120d。第二晶片120藉由接合層120d接合至第三晶片130。在一些實施例中,接合層120d和接合層130b是氧化物層。在一些其他實施例中,第二介電層120a與第三介電層130a直接接觸。
第1B圖是示意性地示出根據本揭示內容的一些實施例的沿線A-A'的第1A圖中的半導體結構100的截面 圖。請同時參照第1A和1B圖,在第二介電層120a中的第二著陸墊120b具有通孔h。第一導電通孔V1從第一著陸墊110b延伸向第二著陸墊120b,並穿過第二著陸墊120b的通孔h。第一導電通孔V1藉由第二介電層120a與第二著陸墊120b分開和絕緣。詳細來說,第二介電層120a的一部份環繞第一導電通孔V1,且第二著陸墊120b環繞第二介電層120a的該部分。
第2圖是示意性地示出本揭示內容的比較例的半導體結構200的截面圖。請同時參考第1A和2圖。在第1A圖中,第一導電通孔V1穿過第二著陸墊120b的通孔h。但是,在第2圖中,第二著陸墊120e沒有任何通孔,因此第一導電通孔V1必須設置在第二著陸墊120b旁邊。通常,著陸墊會佔據較大的空間。例如,著陸墊的寬度可以大於50μm。與半導體結構100相比,半導體結構200需要更多的空間來設置第一導電通孔V1、第二導電通孔V2、第一接合墊110b和第二著陸墊120b。因此,本揭示內容的半導體結構100可以有效地利用空間,並且有利於縮小半導體結構100的尺寸。
本揭示內容提供了一種用於製造半導體結構的方法。第3-6圖是根據本揭示內容的一些實施例的用於在各個階段製造半導體結構的方法的截面圖。
如第3圖所示,第一晶片110與第二晶片120接合,第二晶片120與第三晶片130接合。第一晶片110設置 在第二晶片120上。第三晶片130設置在第二晶片120下。第一晶片110包括第一介電層110a和嵌入在第一介電層110a中的第一著陸墊110b中。第二晶片120包括第二介電層120a和嵌入在第二介電層120a中第二著陸墊120b中。第二著陸墊120b具有通孔h。第二介電層120a的一部份填在第二著陸墊120b的通孔h中。
在一些實施例中,第一晶片110藉由直接接合製程與第二晶片120接合。在一些實施例中,第一晶片110藉由氧化物熔融接合與第二晶片120接合。在一些實施例中,第一晶片110包括接合層110c,第二晶片120包括接合層120c。藉由將第一晶片110的接合層110c和第二晶片120的接合層120c接合,將第一晶片110與第二晶片120接合。在一些其他實施例中,藉由直接接合第一介電層110a及第二介電層120a將第一晶片110與第二晶片120接合。
在一些實施例中,第二晶片120藉由直接接合製程與第三晶片130接合。在一些實施例中,第二晶片120藉由氧化物熔融接合與第三晶片130接合。在一些實施例中,第二晶片120包括接合層120d,並且第三晶片130包括接合層130b。藉由將第二晶片120的接合層120d和第三晶片130的接合層130b接合,將第二晶片120與第三晶片130接合。在一些其他實施例中,藉由直接接合第二介電層120a及第三介電層130a,將第二晶片120與第三晶片130接合。
如第4圖所示,形成第一孔H1穿過第一晶片 110、第二晶片120及第三晶片130以暴露第一著陸墊110b。形成第二孔H2穿過第二晶片120及第三晶片130以暴露第二著陸墊120b。更具體地,形成第一孔H1穿過第二介電層120a的一部份,此部分填充在第二著陸墊120b的通孔h中。
如第5圖所示,在第一孔H1中形成第一導電通孔V1,並且在第二孔H2中形成第二導電通孔V2。
如第6圖所示,第一凸塊B1形成在第三晶片130的下表面S1上以與第一導電通孔V1連接,並且第二凸塊B2形成在第三晶片130的下表面S1上以與第二導電通孔V2連接以形成半導體結構100。本揭示內容的半導體結構100可以有效地利用空間,並且有利於縮小半導體結構100的尺寸。
本揭示內容提供了一種用於製造晶片的方法。在一些實施例中,第3圖中所示的第二晶片120是由如第7-13圖所示的步驟製造的。第7-13圖是根據本揭示內容的一些實施例的用於在各個階段製造晶片的方法的截面圖。
如第7圖所示,接收載體710、離型膜720、接合層120d和介電層740。在一些實施例中,接合層120d是氧化物層。如第8圖所示,在介電層740上形成導電層810。如第9圖所示,圖案化導電層810以形成具有通孔h的第二著陸墊120b,並暴露介電層740的上表面。
接下來,如第12圖所示,形成介電層以覆蓋著 陸墊和介電層740並填充通孔h。在一些實施例中,介電層藉由如第10-12圖中描述的步驟形成。如第10圖所示,形成介電層1000以覆蓋第二著陸墊120b和介電層740。介電層1000的厚度大於第二著陸墊120b的厚度。在一些實施例中,介電層1000的上表面是不平坦的。隨後,如第11圖所示,去除介電層1000的一部分以暴露第二著陸墊120b的上表面。在一些實施例中,介電層1000的該部分藉由化學機械研磨製程去除。接下來,如第12圖所示,形成介電層1200以覆蓋第二著陸墊120b和介電層1000。
如第13圖所示,在介電層1200上形成接合層120c。因此,與第3圖所示第二晶片120類似的晶片形成於載體710及離型膜720上。在一些實施例中,接合層120c是氧化物層。
儘管已經參考某些實施方式相當詳細地描述了本發明,但是亦可能有其他實施方式。因此,所附申請專利範圍的精神和範圍不應限於此處包含的實施方式的描述。
對於所屬技術領域人員來說,顯而易見的是,在不脫離本發明的範圍或精神的情況下,可以對本發明的結構進行各種修改和變化。鑑於前述內容,本發明意圖涵蓋落入所附權利要求範圍內的本發明的修改和變化。
100‧‧‧半導體結構
110‧‧‧第一晶片
110a‧‧‧第一介電層
110b‧‧‧第一著陸墊
110c‧‧‧接合層
120‧‧‧第二晶片
120a‧‧‧第二介電層
120b‧‧‧第二著陸墊
120c‧‧‧接合層
120d‧‧‧接合層
130‧‧‧第三晶片
130a‧‧‧第三介電層
130b‧‧‧接合層
h‧‧‧通孔
B1‧‧‧第一凸塊
B2‧‧‧第二凸塊
S1‧‧‧下表面
V1‧‧‧第一導電通孔
V2‧‧‧第二導電通孔

Claims (20)

  1. 一種半導體結構,包括:一第一晶片,包括一第一介電層和嵌入在該第一介電層中的一第一著陸墊;一第二晶片,包括一第二介電層和嵌入在該第二介電層中的一第二著陸墊,其中該第一晶片設置在該第二晶片上,並且該第二著陸墊具有一通孔;以及一第一導電通孔,從該第一著陸墊延伸向該第二著陸墊,並穿過該第二著陸墊的該通孔。
  2. 如請求項1所述的半導體結構,其中該第二介電層的一部分環繞該第一導電通孔,該第一導電通孔藉由該部分的該第二介電層與該第二著陸墊分離。
  3. 如請求項1所述的半導體結構,其中該第一晶片是從晶片。
  4. 如請求項1所述的半導體結構,其中該第二晶片是從晶片。
  5. 如請求項1所述的半導體結構,還包括設置在該第二晶片下方的一第三晶片,其中該第三晶片包括在該第三晶片的一下表面上的一第一凸塊,該第一導電通孔延伸穿過該第三晶片以與該第一凸塊連接。
  6. 如請求項5所述的半導體結構,其中該第三晶片是主晶片。
  7. 如請求項5所述的半導體結構,還包括一第二導電通孔,該第二導電通孔從該第二著陸墊延伸進入該第三晶片,其中該第三晶片還包括在該第三晶片的一下表面上的一第二凸塊,並且該第二導電通孔與該第二凸塊連接。
  8. 如請求項5所述的半導體結構,其中該第三晶片包括一第三介電層和一第一接合層,並且該第一接合層設置在該第三介電層和該第二晶片之間。
  9. 如請求項8所述的半導體結構,其中該第二晶片還包括一第二接合層,該第二接合層設置在該第二介電層與該第一接合層之間。
  10. 如請求項1所述的半導體結構,其中該第一晶片還包括設置在該第一介電層和該第二晶片之間的一第一接合層。
  11. 如請求項10所述的半導體結構,其中該第二晶片還包括設置在該第二介電層和該第一晶片之間的 一第二接合層。
  12. 一種用於製造半導體結構的方法,該方法包括:接合一第一晶片與一第二晶片,其中該第一晶片設置在該第二晶片上,該第一晶片包括一第一介電層和嵌入在該第一介電層中的一第一著陸墊,該第二晶片包括一第二介電層和嵌入在該第二介電層中的一第二著陸墊,該第二著陸墊具有一通孔,該第二介電層的一部份填滿於該第二著陸墊的該通孔;形成一第一孔穿過該第一晶片及該第二晶片的該第二介電層的該部分,以暴露該第一著陸墊;以及形成一第一導電通孔於該第一孔中。
  13. 如請求項12所述的方法,在形成該第一孔之前,還包括將一第三晶片與該第二晶片接合,其中該第三晶片設置在該第二晶片下方,其中形成該第一孔包括形成該第一孔穿過該第三晶片。
  14. 如請求項13所述的方法,還包括:形成一第二孔穿過該第二晶片及該第三晶片以暴露該第二著陸墊;以及形成一第二導電通孔於該第二孔中。
  15. 如請求項13所述的方法,其中藉由一直接接合製程接合該第三晶片與該第二晶片。
  16. 如請求項13所述的方法,還包括形成一第一凸塊於該第三晶片的一下表面上,其中該第一凸塊與該第一導電通孔連接。
  17. 如請求項12所述的方法,在將該第一晶片與該第二晶片接合之前,還包括形成該第二晶片,其中形成該第二晶片包括:在一第三介電層上形成一導電層;對該導電層進行圖案化以形成具有該通孔的該第二著陸墊;以及形成一第四介電層以覆蓋該第二著陸墊和該第三介電層。
  18. 如請求項17所述的方法,其中形成該第四介電層包括:形成一第五介電層以覆蓋該第二著陸墊和該第三介電層;去除該第五介電層的一部分以暴露出該第二著陸墊的一上表面;以及形成一第六介電層以覆蓋該第二著陸墊及該第五介電層。
  19. 如請求項12所述的方法,其中藉由一直接接合製程接合該第一晶片與該第二晶片。
  20. 如請求項12所述的方法,其中該第一晶片包括一第一接合層,該第二晶片包括一第二接合層,接合該第一晶片與該第二晶片包括接合該第一晶片的該第一接合層及該第二晶片的該第二接合層。
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