TWI713470B - 具有焊線的功率覆蓋結構及其製造方法 - Google Patents

具有焊線的功率覆蓋結構及其製造方法 Download PDF

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TWI713470B
TWI713470B TW104133047A TW104133047A TWI713470B TW I713470 B TWI713470 B TW I713470B TW 104133047 A TW104133047 A TW 104133047A TW 104133047 A TW104133047 A TW 104133047A TW I713470 B TWI713470 B TW I713470B
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power
dielectric layer
semiconductor device
layer
contact pad
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TW104133047A
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Chinese (zh)
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TW201626468A (zh
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艾倫 格達
保羅 麥克尼爾
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美商通用電機股份有限公司
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    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/144—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations comprising foils
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    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
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    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H10W20/057—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by selectively depositing, e.g. by using selective CVD or plating
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    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
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    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
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    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
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    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
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    • H10W72/019—Manufacture or treatment of bond pads
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
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    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
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    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H10W72/5473—Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
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    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5525—Materials of bond wires comprising metals or metalloids, e.g. silver comprising copper [Cu]
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    • H10W72/874—On different surfaces
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    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
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    • H10W90/00—Package configurations
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    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
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    • H10W90/00—Package configurations
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    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
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    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
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    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
TW104133047A 2014-10-13 2015-10-07 具有焊線的功率覆蓋結構及其製造方法 TWI713470B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/512,562 US9613843B2 (en) 2014-10-13 2014-10-13 Power overlay structure having wirebonds and method of manufacturing same
US14/512,562 2014-10-13

Publications (2)

Publication Number Publication Date
TW201626468A TW201626468A (zh) 2016-07-16
TWI713470B true TWI713470B (zh) 2020-12-21

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Country Link
US (2) US9613843B2 (https=)
EP (1) EP3010038A3 (https=)
JP (3) JP2016082230A (https=)
KR (1) KR102419302B1 (https=)
CN (3) CN105514077B (https=)
TW (1) TWI713470B (https=)

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JP7472435B2 (ja) 2019-05-13 2024-04-23 富士電機株式会社 半導体モジュールの製造方法
CN111162015A (zh) * 2019-12-20 2020-05-15 珠海格力电器股份有限公司 一种智能功率模块及封装方法
US11776870B2 (en) * 2020-01-16 2023-10-03 Semiconductor Components Industries, Llc Direct bonded copper substrates fabricated using silver sintering
US11398445B2 (en) 2020-05-29 2022-07-26 General Electric Company Mechanical punched via formation in electronics package and electronics package formed thereby
DE112020007480T5 (de) * 2020-08-03 2023-05-17 Mitsubishi Electric Corporation Halbleitereinheit, herstellungsverfahren für dieselbe und leistungswandler
EP4012753A1 (en) * 2020-12-08 2022-06-15 Hitachi Energy Switzerland AG Semiconductor device, semiconductor module and manufacturing method
CN112910285B (zh) * 2021-01-05 2022-06-14 深圳市富鑫产业科技有限公司 一种逆变器电力系统及其制造方法
US11848244B2 (en) * 2021-09-30 2023-12-19 Texas Instruments Incorporated Leaded wafer chip scale packages
WO2026009326A1 (ja) * 2024-07-02 2026-01-08 三菱電機株式会社 半導体装置及び電力変換装置

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