TWI708283B - 形成有犧牲間隔件之奈米片場效電晶體 - Google Patents

形成有犧牲間隔件之奈米片場效電晶體 Download PDF

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TWI708283B
TWI708283B TW108125638A TW108125638A TWI708283B TW I708283 B TWI708283 B TW I708283B TW 108125638 A TW108125638 A TW 108125638A TW 108125638 A TW108125638 A TW 108125638A TW I708283 B TWI708283 B TW I708283B
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sidewall spacer
dielectric material
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gate structure
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朱利安 弗羅吉爾
謝瑞龍
丹尼爾 恰尼莫蓋姆
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美商格芯（美國）集成電路科技有限公司
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Abstract

本發明提供一種用於場效電晶體的結構和形成用於場效電晶體的結構的方法。層堆疊包括與犧牲層交替地配置的奈米片通道層。形成第一和第二閘極結構延伸跨越該層堆疊並且被第一間隙分離。第一和第二側壁間隔件是形成在該層堆疊上方並且在該第一間隙內分別地相鄰該第一和第二閘極結構，並且接著蝕刻該層堆疊，以形成被第二間隙分離的第一和第二本體特徵。相對於該奈米片通道層凹化該犧牲層，以在該第一和第二本體特徵中定義凹口，並且接著移除該第一和第二側壁間隔件。在移除該第一和第二側壁間隔件後，共形層沉積在該第二間隙中填充該凹口，以定義內間隔件。

Description

形成有犧牲間隔件之奈米片場效電晶體
本發明是關於半導體裝置製作和積體電路，並且特別地是關於用於場效電晶體的結構和形成用於場效電晶體的結構的方法。
用於場效電晶體的裝置結構大致上包括源極、汲極、以及閘極電極，其經組構以切換形成在配置在源極與汲極之間的半導體層中的通道中的載子流動。半導體層和平面型場效電晶體的通道是配置在基板的頂表面之下，其中，閘極電極被支撐在基板上。當超過指定臨界電壓的控制電壓被施加至閘極電極時，通道中的載子的水平流動產生裝置輸出電流。
奈米片場效電晶體經發展成一種非平面型場效電晶體的類型，其可允許積體電路中的封裝密度的額外增加。奈米片場效電晶體包括配置成層堆疊的多個奈米片通道層和連接至奈米片通道層的末端的源極/汲極區域。奈米片通道層最初配置在層堆疊中，層堆疊具有犧牲層，其含有與奈米片通道層交替之材料(例如，矽-鍺)，並且可相對於構成奈米片通道層的材料(例如，矽)被選擇性蝕刻。蝕刻並移除犧牲層，以為了釋放奈米片通道層並提供空間用於形成閘極堆疊的區段。閘極堆疊的區段可以閘極全圍繞配置(gate-all-around arrangement)圍繞個別奈米片通道層的所有側 面。當超過指定臨界電壓的控制電壓施加至閘極堆疊時，奈米片通道層中的載子的水平流動產生裝置輸出電流。
在形成源極/汲極區域和閘極堆疊前，凹化犧牲層以形成凹穴(divot)或凹口在層堆疊中。以介電材料填充凹口以定義最終會將閘極堆疊與源極/汲極區域隔離的內間隔件。傳統上，沉積在凹口內側夾止(pinche off)的共形層以形成內間隔件。實施介電回蝕刻(etch back)以從奈米片通道層的末端移除共形層的過剩介電材料，其是需要用於源極/汲極區域的後續磊晶生長。當奈米片場效電晶體的閘極堆疊的間隔(pitch)向下縮減時，沉積的共形層可夾止並且堵塞奈米片通道層的相鄰層堆疊上的閘極堆疊之間的窄化的空間。如果此空間被堵塞，則無法可靠地形成內間隔件。
在本發明的實施例中，提供用來形成場效電晶體的方法。該方法包括磊晶地生長層堆疊，該層堆疊包括複數個奈米片通道層和與該複數個奈米片通道層交替地配置的複數個犧牲層。形成延伸跨越該層堆疊並且被第一間隙分離的第一和第二閘極結構。該方法進一步包括在該層堆疊上方並且在該第一間隙內分別與該第一閘極結構和該第二閘極結構相鄰地形成第一側壁間隔件和第二側壁間隔件。在形成該第一側壁間隔件和該第二側壁間隔件後，蝕刻該層堆疊，以形成第一本體特徵和與該第一本體特徵以第二間隙分離的第二本體特徵。該方法進一步包括相對於該複數個奈米片通道層凹化該複數個犧牲層以定義複數個凹口在該第一本體特徵和該第二本體特徵中。在凹化該複數個犧牲層後，移除該第一側壁間隔件和該第二側壁間隔件。該方法進一步包括在移除該第一側壁間隔件和該第二側 壁間隔件後，在該第二間隙沉積填充該複數個凹口的共形層以定義複數個內間隔件。
在本發明的實施例中，提供用來形成場效電晶體的方法。該方法包括：形成層堆疊，該層堆疊包括複數個奈米片通道層和與該奈米片通道層交替地配置的複數個犧牲層；形成延伸跨越該層堆疊的閘極結構；以及形成相鄰該閘極結構的側壁間隔件。在形成該第一側壁間隔件後，蝕刻該層堆疊以形成本體特徵。該方法進一步包括相對於該奈米片通道層凹化該犧牲層以定義複數個凹口在該本體特徵中。在凹化該犧牲層後，移除該第一側壁間隔件，並且在該本體特徵和該閘極結構上方沉積填充該凹口的共形層以定義複數個內間隔件。
在本發明的實施例中，提供用於場效電晶體的結構。該結構包括配置在層堆疊中的複數個奈米片通道層、連接至該奈米片通道層的源極/汲極區域、以及包括分別地圍繞該奈米片通道層的複數個區段的閘極結構。該結構進一步包括配置為相鄰該閘極結構的第一側壁間隔件、以及配置為相鄰該閘極結構的第二側壁間隔件。該第二側壁間隔件是配置在堆疊配置中的該第一側壁間隔件上方。該第一側壁間隔件係由第一低k介電材料組成，而該第二側壁間隔件係由與該第一低k介電材料的成分不同的第二低k介電材料組成。
10‧‧‧奈米片通道層
12、14‧‧‧犧牲層
13‧‧‧淺溝槽隔離區域
15‧‧‧圖案化層堆疊、層堆疊
16‧‧‧基板
18、20‧‧‧犧牲閘極結構
21‧‧‧硬遮罩蓋件
22‧‧‧共形介電襯裡、介電襯裡
22a、22b‧‧‧介電層
23‧‧‧間隙
24‧‧‧共形介電層、介電層
24a‧‧‧介電層
26‧‧‧雙層側壁間隔件
28、30‧‧‧本體特徵
29‧‧‧間隙
32‧‧‧凹口
34、38‧‧‧共形層
36‧‧‧蝕刻遮罩
40‧‧‧上側壁間隔件、側壁間隔件
42‧‧‧下側壁間隔件、側壁間隔件
44‧‧‧內間隔件
46‧‧‧源極/汲極區域
48‧‧‧間隙填充層
52‧‧‧閘極結構
52a‧‧‧區段
54‧‧‧場效電晶體
56‧‧‧自對準接觸蓋件
併入至此說明書中並且構成此說明書的一部分的圖式例示本發明的各種實施例，並且與上方給出的一般性描述和下方給出的詳細描述一起用作解釋本發明的實施例。
第1圖是依據本發明的實施例的處理方法的初始製作階段的裝置結構的頂視圖。
第2圖是大致上沿著第1圖的線2-2取用的剖面視圖。
第3-13圖是接續第2圖的處理方法的連續性製作階段的裝置結構的剖面視圖。
參考第1、2圖並且依據本發明的實施例，奈米片通道層10、犧牲層12和犧牲層14是配置在基板16上的圖案化層堆疊15中。基板16可由半導體材料組成，例如單晶矽。淺溝槽隔離區域13可配置在圖案化層堆疊15周圍。奈米片通道層10和犧牲層12、14可藉由磊晶生長程序形成在基板16上，在磊晶生長程序期間，經由變化供應至沉積工具的反應物而交替成分。奈米片通道層10和犧牲層12、14在生長後可使用微影和蝕刻程序加以圖案化，以形成層堆疊15。層堆疊15中的奈米片通道層10和犧牲層12的數目可與所繪示之代表實施例中的數目不同，並且特別地，可經由添加成對的奈米片通道層10和犧牲層12至層堆疊15而大於代表實施例中的數目。
奈米片通道層10是由半導體材料組成，而犧牲層12是由經選擇為被相對於奈米片通道層10的半導體材料選擇性移除的半導體材料組成。犧牲層14是由經選擇為被相對於奈米片通道層10和犧牲層12兩者的半導體材料選擇性移除的半導體材料組成。如本文中所使用的，指示材料移除程序(例如，蝕刻)的術語「選擇性」是指在適當的蝕刻劑選擇下， 目標材料的材料移除速率(也就是，蝕刻速率)是大於暴露至材料移除程序的至少另一種材料的移除速率。
在實施例中，構成奈米片通道層10的半導體材料可為矽(Si)，構成犧牲層12的半導體材料可為矽-鍺(SiGe)(其因為鍺含量而以高於矽的速率蝕刻)，而構成犧牲層14的半導體材料可為矽-鍺(SiGe)(其因為較高的鍺含量而以高於犧牲層12的速率蝕刻)。在實施例中，犧牲層12的鍺含量的範圍可從15原子百分比(15at.%)至35原子百分比(35at.%)，而犧牲層14的鍺含量的範圍可從50原子百分比(50at.%)至75原子百分比(75at.%)。
形成犧牲閘極結構18、20與圖案化層堆疊15重疊並且環繞圖案化層堆疊15。本文中所使用的術語「犧牲閘極結構」是指用於接著形成的閘極結構的占位(placeholder)結構。犧牲閘極結構18、20具有沿著層堆疊15的長度的間隔配置，並且橫向於層堆疊15排列。特別地，犧牲閘極結構18、20被間隙23間隔開。
犧牲閘極結構18、20可包括一薄層及一厚層，該薄層相鄰層堆疊15而配置且含有例如矽二氧化物，該厚層在薄層上方且含有例如非結晶矽。犧牲閘極結構18、20使用硬遮罩以反應式離子蝕刻(RIE)從這些構成層予以圖案化。犧牲閘極結構18、20可沿著它們的長度切割，以定義個別場效電晶體的位置及/或犧牲閘極結構18、20可與類似於層堆疊15的額外層堆疊重疊。犧牲閘極結構18、20被配置在它們個別的頂表面上的硬遮罩蓋件21覆蓋。硬遮罩蓋件21可包括一或多個介電材料(例如矽二氧化物在矽氮化物上的分層組合)，並且可為用來形成犧牲閘極結構18、20的微影和蝕刻程序的硬遮罩的殘餘物。
參考第3圖，其中，相同元件符號是指第2圖中的相同特徵，並且，在處理方法的後續製作階段處，藉由對奈米片通道層10和犧牲層12的有選擇性的蝕刻程序移除犧牲層14。在移除犧牲層14後，共形介電襯裡22和共形介電層24接續形成在犧牲閘極結構18、20和它們的硬遮罩蓋件21上，並連同形成在犧牲閘極結構18、20之間的最上面的犧牲層12的表面上。在實施例中，介電襯裡22可由藉由原子層沉積(ALD)所沉積的矽二氧化物(SiO2)組成，而介電層24可由藉由原子層沉積所沉積的矽-硼-碳氮化物(SiBCN)組成。
介電襯裡22的介電材料也形成於藉由移除犧牲層14所產生的凹洞內以在犧牲層12上作為介電層22a以及在基板16上作為介電層22b。介電層25的介電材料也形成為介電層24a以填充凹洞內的介電層22a、22b之間的剩餘空間。
參考第4圖，其中，相同元件符號是指第3圖中的相同特徵，並且，在處理方法的後續製作階段處，藉由以方向性蝕刻程序(例如反應式離子蝕刻)蝕刻介電襯裡22和介電層24以在犧牲閘極結構18、20的側壁處形成雙層(bilayer)側壁間隔件26。介電襯裡22提供雙層側壁間隔件26的L-形狀的組成成分，並且介電層24提供雙層側壁間隔件26的最外側組成成分。犧牲閘極結構18、20之間的間隙23藉由形成雙層側壁間隔件26而窄化。
圖案化奈米片通道層10和犧牲層12以形成本體特徵28、30，其各包括圖案化的奈米片通道層10和犧牲層12的層堆疊15的一者。可藉由自對準蝕刻程序形成本體特徵28、30，在自對準蝕刻程序中，個別的犧牲閘極結構18、20和雙層側壁間隔件26有效地運作為蝕刻遮罩。自對準蝕刻程序，其可為反應式離子蝕刻程序，可利用一個或更多個蝕刻化 學劑以蝕刻奈米片通道層10和犧牲層12，並且可停止在介電層22a上。本體特徵28、30於圖案化完成後，藉由間隙29而彼此分離。由於自對準，間隙29等於或實質地等於間隙23。
參考第5圖，其中，相同元件符號是指第4圖中的相同特徵，並且，在處理方法的後續製作階段處，以乾或溼等向性蝕刻程序(其相對於構成奈米片通道層10的半導體材料有選擇性地蝕刻構成犧牲層12的半導體材料)相對於奈米片通道層10側向地凹化犧牲層12。由於奈米片通道層10因為等向性蝕刻程序的蝕刻選擇性而沒有被側向地蝕刻，故犧牲層12的側向凹化在本體特徵28、30的側壁中產生凹口32。在實施例中，可使用水(H2O)、過氧化氫(H2O2)和氫氧化胺(NH4OH)的混合物，側向地凹化犧牲層12(也就是，溼SC1清潔法)。
參考第6圖，其中，相同元件符號是指第5圖中的相同特徵，並且，在處理方法的後續製作階段處，以一個或更多個蝕刻程序移除雙層側壁間隔件26，以暴露犧牲閘極結構18、20的側壁。介電層22a在移除雙層側壁間隔件26的介電層24的蝕刻程序期間，遮蓋和保護介電層24a的下覆部分。介電層22a藉由移除介電層24所暴露的部分接著藉由移除雙層側壁間隔件26的介電襯裡22的蝕刻程序而被移除。雙層側壁間隔件26(其是犧牲的)的移除與內間隔件是形成在凹口32中，而側壁間隔件定位至相鄰犧牲閘極結構18、20的傳統程序流程形成對比。雙層側壁間隔件26的移除增加犧牲閘極結構18、20之間的間隙29的寬度。
參考第7圖，其中，相同元件符號是指第6圖中的相同特徵，並且，在處理方法的後續製作階段處，由低k介電材料(例如碳摻雜的矽氧化物(SiCO))組成的共形層34藉由原子層沉積沉積，並且填充本體特徵28、30之間的間隙29。低k介電材料藉由小於矽二氧化物的介電常數 (其是大約3.9)的相對電容率或介電常數加以特性化。共形層34藉由夾止(pinch-off)填充本體特徵28、30的側壁中的凹口32。共形層34也覆蓋犧牲閘極結構18、20及它們的硬遮罩蓋件21。先前對於雙層側壁間隔件26的移除有效地加寬犧牲閘極結構18、20之間的間隙23，以促進本體特徵28、30之間的間隙29的改進填充，並且於沉積共形層34期間防止間隙23內側的夾止。
鋪設蝕刻遮罩36並以蝕刻程序凹化蝕刻遮罩36。蝕刻遮罩36可包括來自被鋪設為旋塗(spin-on)硬遮罩的有機平坦化層(OPL)的材料。凹化的蝕刻遮罩36的高度是犧牲閘極結構18、20的高度的一部分(fraction)。
參考第8圖，其中，相同元件符號是指第7圖中的相同特徵，並且，在處理方法的後續製作階段處，使用蝕刻程序以去角化共形層34至凹化的蝕刻遮罩36的高度。蝕刻程序可藉由溼化學蝕刻或乾反應式離子蝕刻實施。蝕刻程序完成後，可藉由，舉例來說，使用基於氧的電漿的灰化(ashing)來移除蝕刻遮罩36。
參考第9圖，其中，相同元件符號是指第8圖中的相同特徵，並且，在處理方法的後續製作階段處，藉由原子層沉積沉積由低k介電材料(例如矽-硼-碳氮化物(SiBCN))所組成的共形層38。共形層38覆蓋犧牲閘極結構18、20及它們的硬遮罩蓋件21中被共形層34的去角化所暴露的部分，並且覆蓋存留在本體特徵28、30之間的間隙29中的共形層34。共形層38的介電材料被選擇為相對於共形層34的介電材料具有蝕刻選擇性。
參考第10圖，其中，相同元件符號是指第9圖中的相同特徵，並且，在處理方法的後續製作階段處，藉由以方向性蝕刻程序(例如非 等向性反應式離子蝕刻程序)蝕刻共形層38，以在犧牲閘極結構18、20的側壁處形成上側壁間隔件40。蝕刻程序對共形層34的介電材料選擇性移除共形層38的介電材料。
參考第11圖，其中，相同元件符號是指第10圖中的相同特徵，並且，在處理方法的後續製作階段處，藉由以方向性蝕刻程序(例如非等向性反應式離子蝕刻程序)蝕刻共形層34，以在犧牲閘極結構18、20的側壁處形成下側壁間隔件42。蝕刻程序對共形層38的介電材料選擇性移除共形層34的介電材料，並且上側壁間隔件40有效地提供用於下側壁間隔件42的自對準形成的蝕刻遮罩。上側壁間隔件40是配置在相鄰犧牲閘極結構18、20的側壁的下側壁間隔件42上方，而上側壁間隔件40是堆疊在下側壁間隔件42上方(也就是，放置在下側壁間隔件42的頂部上)。由於它們的介電材料之間的蝕刻選擇性，因此，上側壁間隔件40沒有被形成下側壁間隔件42的蝕刻程序下拉(pulled down)至顯著程度。附加的是，形成上側壁間隔件40和下側壁間隔件42不需要傳統的溼化學蝕刻。
蝕刻程序也在本體特徵28、30的側壁中的凹口中形成內間隔件44。內間隔件44的形成晚於傳統程序流程發生，並且內間隔件44是由低k介電材料、而不是由矽氮化物或矽氧化物組成。
參考第12圖，其中，相同元件符號是指第11圖中的相同特徵，並且，在處理方法的後續製作階段處，在相鄰本體特徵28、30的各者的側表面處形成源極/汲極區域46。如本文中所使用的，術語「源極/汲極區域」是指可作用為場效電晶體的源極或汲極的半導體材料的摻雜區域。源極/汲極區域46是直接地與奈米片通道層10連接，並且藉由內間隔件44與犧牲層12實體隔離。
可藉由磊晶生長程序形成源極/汲極區域46，在磊晶生長程序中，單結晶半導體材料從由奈米片通道層10所提供的生長種子(growth seed)側向地生長。源極/汲極區域46的單結晶半導體材料與奈米片通道層10的單結晶半導體材料具有磊晶關係。構成源極/汲極區域46的半導體材料可被重度地摻雜以具有p-類型導電性或n-類型導電性，視場效電晶體的類型而定。在實施例中，可藉由選擇性磊晶生長(SEG)程序形成源極/汲極區域46，在選擇性磊晶生長程序中，半導體材料成核化以用於在單結晶表面(例如該奈米片通道層10)上磊晶生長，但不成核化用於從絕緣體表面磊晶生長。
參考第13圖，其中，相同元件符號是指第12圖中的相同特徵，並且，在處理方法的後續製作階段處，沉積並平坦化間隙填充層48，以填充源極/汲極區域46上方的犧牲閘極結構18、20與半導體之間的空間。間隙填充層48可由介電材料(例如矽二氧化物(SiO2))組成，其藉由化學氣相沉積(CVD)沉積，並可藉由化學機械研磨(CMP)平坦化。平坦化移除硬遮罩蓋件21以顯露犧牲閘極結構18、20並縮短犧牲閘極結構18、20和上側壁間隔件40的高度。
以一個或更多個蝕刻程序移除犧牲閘極結構18、20。接著以蝕刻程序對奈米片通道層10和內間隔件44的材料選擇性移除犧牲層12的材料以移除犧牲層12。蝕刻程序可為，舉例來說，溼SC1清潔法或乾氣相鹽酸(HCl)蝕刻。犧牲層12的移除釋放奈米片通道層10並且打開圍繞本體特徵28、30的各者的奈米片通道層10的空間。內間隔件44和間隙填充層48作用成遮罩源極/汲極區域46而不受到移除犧牲層12的蝕刻程序。奈米片通道層10錨定在內間隔件44之間的相對末端處。
在取代閘極程序中，在藉由犧牲閘極結構18、20和犧牲層12的移除所打開的空間中形成閘極結構52，以完成場效電晶體54的形成。閘極結構52可包括覆蓋奈米片通道層10的介面層、由介電材料(例如高k介電質)所組成的閘極介電層、以及由一個或更多個阻障金屬層及/或功函數金屬層(例如鈦鋁碳化物(TiAlC)或鈦氮化物(TiN))所組成的金屬閘極電極、以及由例如鎢(W)的導體所組成的金屬閘極填充層。介面層和閘極介電層是配置在閘極電極與奈米片通道層10的外表面之間。
由介電材料(例如矽氮化物(Si3N4))所組成的自對準接觸(SAC)蓋件56形成在上側壁間隔件40之間的空間中以及在閘極結構52的各者上方。可移除間隙填充層48，並且可形成溝槽矽化物接觸(未顯示)在延伸以接觸源極/汲極區域46的打開空間中。接著使用中段(MOL)和後段(BEOL)處理以形成耦接至場效電晶體54的互連結構。
場效電晶體54的奈米片通道層10是配置在直立堆疊中，並且各個閘極結構52的區段52a是位在由移除的犧牲層12所先前占據的空間中。各個閘極結構52的區段52a可以閘極全圍繞配置圍繞奈米片通道層10的外表面。奈米片通道層10作用成用於在場效電晶體54的運作期間所形成的載子流動的通道。
在不同實施例中，堆疊配置中的上側壁間隔件40和下側壁間隔件42的介電材料可對調，以使上側壁間隔件40是由碳摻雜的矽氧化物(SiCO)組成，而下側壁間隔件42是由矽-硼-碳氮化物(SiBCN)組成。上側壁間隔件40和下側壁間隔件42的介電材料可加以變化，只要維持介電材料之間的蝕刻選擇性即可。舉例來說，介電材料的一者可為基於氧化物的低k介電材料(例如，碳摻雜的矽氧化物)，而介電材料的另一者可為基於氮化物的低k介電材料(例如，矽-硼-碳氮化物)。對於側壁間隔件40、 42的介電材料的成分(也就是，共形介電層34、38)的改變將導致對於形成介電層22a、22b、24a的介電材料的成分的附隨改變。
內間隔件44是由低k介電材料組成，其可在場效電晶體54的運作期間，有效地減少閘極結構52與溝槽矽化物接觸和源極/汲極區域46之間的電容。內間隔件44與下側壁間隔件42是由相同介電材料組成，並且改變提供下側壁間隔件42的介電材料也將改變構成內間隔件44的介電材料，因為各者是從相同共形層34形成。
如上方所描述的方法是用來製作積體電路晶片。生成的積體電路晶片可由製作者以生晶圓形式(例如，成具有多個未封裝晶片的單一晶圓)分佈成裸晶粒、或以封裝形式分佈。在後者的案例中，晶片是安裝在單一晶片封裝件(例如，具有固定至主機板的引線的塑膠承載件、或其它高階承載件)中、或在多晶片封裝件(例如，具有表面互連和埋置互連的一者或兩者的陶瓷承載件)中。在任何案例中，晶片可整合至其它晶片、分離的電路元件、及/或其它訊號處理裝置，以作為中間產品或終端產品的部件。
本文中的對於由約略的文字，例如「大約」、「約略地」和「實質地」，所修飾的術語並沒有限制至所指定的精確數值。約略的文字可對應於用來測量數值的儀器的精確性，並且可指示陳述的數值的+/-10%，除非另外視儀器的精確性而定。
本文中指示的術語「直立」、「水平」、「側面的」等是藉由範例、而非藉由限制的方式作出，以建立參考的框架。術語「水平」和「側面」是定義為與半導體基板的頂表面平行的平面，不論其實際三維空間轉向。術語「直立」和「正交」是指與「水平」方向垂直的方向。例如「上方」和「下方」的術語是用來指示元件或結構相對於彼此及/或相對於半導體基板的頂表面的定位，而非相對的高度。
特徵「連接」或「耦接」至另一個元件可直接地連接或耦接至其它元件、或者可存在一個或更多個中介元件。如果沒有存在中介元件，則特徵可「直接地連接」或「直接地耦接」至另一個元件。如果存在至少一個中介元件，則特徵可「間接地連接」或「間接地耦接」至另一個元件。
本發明的各種實施例的描述已經為了例示的目的呈現，而不意圖窮盡或限制至所揭露的實施例。許多修飾和變化對於本領域中的熟習技術者將是明顯的，而不致於偏離描述的實施例的範疇和精神。本文所使用的技術用語經選擇為最佳解釋實施例的原理、針對市場中所發現的技術的實際應用或技術改進、或致能本領域中的其他通常技術者了解本文所揭露的實施例。
10:奈米片通道層
16:基板
18、20:犧牲閘極結構
22a、22b:介電層
24a:介電層
40:上側壁間隔件、側壁間隔件
42:下側壁間隔件、側壁間隔件
44:內間隔件
46:源極/汲極區域
48:間隙填充層
52:閘極結構
52a:區段
54:場效電晶體
56:自對準接觸蓋件

Claims (20)

  1. 一種用於形成場效電晶體的方法，該方法包含：磊晶地生長層堆疊，該層堆疊包括複數個奈米片通道層和與該複數個奈米片通道層交替地配置的複數個犧牲層；形成延伸跨越該層堆疊並且以第一間隙分離的第一閘極結構和第二閘極結構；在該層堆疊上方並在該第一間隙內分別與該第一閘極結構和該第二閘極結構相鄰地形成第一側壁間隔件和第二側壁間隔件以使該第一間隙窄化；在形成該第一側壁間隔件和該第二側壁間隔件後，蝕刻該層堆疊，以形成第一本體特徵和與該第一本體特徵以第二間隙分離的第二本體特徵；相對於該複數個奈米片通道層凹化該複數個犧牲層，以在該第一本體特徵和該第二本體特徵中定義複數個凹口；在凹化該複數個犧牲層後，移除該第一側壁間隔件和該第二側壁間隔件；以及在移除該第一側壁間隔件和該第二側壁間隔件後，在該第二間隙中沉積填充該複數個凹口的第一共形層，以定義複數個內間隔件。
  2. 如申請專利範圍第1項所述之方法，進一步包含：去角化該第一間隙內的該第一共形層，以部分地暴露該第一閘極結構和該第二閘極結構。
  3. 如申請專利範圍第2項所述之方法，進一步包含：在去角化該第一共形層後，在該第一間隙中的該第一共形層上方和在該第一間隙中的該第一閘極結構和該第二閘極結構上方沉積第二共形層。
  4. 如申請專利範圍第3項所述之方法，進一步包含： 以第一蝕刻程序蝕刻該第二共形層，以形成相鄰該第一閘極結構的第三側壁間隔件的第一區段和相鄰該第二閘極結構的第四側壁間隔件的第一區段。
  5. 如申請專利範圍第4項所述之方法，進一步包含：在以該第一蝕刻程序蝕刻該第二共形層後，以第二蝕刻程序蝕刻該第一共形層，以形成相鄰該第一閘極結構的該第三側壁間隔件的第二區段和相鄰該第二閘極結構的該第四側壁間隔件的第二區段，其中，該第三側壁間隔件的該第一區段是配置在該第三側壁間隔件的該第二區段上方，而該第四側壁間隔件的該第一區段是配置在該第四側壁間隔件的該第二區段上方。
  6. 如申請專利範圍第5項所述之方法，其中，該第一蝕刻程序對該第一共形層選擇性蝕刻該第二共形層，而該第二蝕刻程序對該第二共形層選擇性蝕刻該第一共形層。
  7. 如申請專利範圍第2項所述之方法，其中，該第一共形層係由第一低k介電材料組成，而該第二共形層係由具有與該第一低k介電材料的成分不同的第二低k介電材料組成。
  8. 如申請專利範圍第1項所述之方法，其中，該第一側壁間隔件和該第二側壁間隔件是從第一介電材料和與該第一介電材料的成分不同的第二介電材料形成，並且進一步包含：形成凹洞在該層堆疊之下；以及以由該第一介電材料組成的第一介電層、由該第一介電材料組成的第二介電層、以及由該第二介電材料組成並且配置在該第一介電層與該第二介電層之間的直立方向中的第三介電層填充該凹洞。
  9. 如申請專利範圍第8項所述之方法，其中，移除該第一側壁間隔件和該第二側壁間隔件包含：移除該第一側壁間隔件和該第二側壁間隔件的該第一介電材料，以暴露該第一側壁間隔件和該第二側壁間隔件的該第二介電材料；以及在移除該第一介電材料後，移除該第一側壁間隔件和該第二側壁間隔件的該第二介電材料，其中，該第一介電層是配置在該第二介電層與該層堆疊之間，而該第一介電層於移除該第一側壁間隔件和該第二側壁間隔件的該第一介電材料時覆蓋該第三介電層。
  10. 一種用於形成場效電晶體的方法，該方法包含：形成層堆疊，該層堆疊包括複數個奈米片通道層和與該複數個奈米片通道層交替地配置的複數個犧牲層；形成延伸跨越該層堆疊的閘極結構；形成相鄰該閘極結構的第一側壁間隔件；在形成該第一側壁間隔件後，蝕刻該層堆疊以形成本體特徵；相對於該複數個奈米片通道層凹化該複數個犧牲層以在該本體特徵中定義複數個凹口；在凹化該複數個犧牲層後，移除該第一側壁間隔件；以及沉積填充該複數個凹口的第一共形層以定義複數個內間隔件；其中，該第一共形層是沉積在該本體特徵和該閘極結構上方。
  11. 如申請專利範圍第10項所述之方法，進一步包含：去角化該第一共形層以部分地暴露該閘極結構；以及沉積第二共形層在該第一共形層和該閘極結構上方。
  12. 如申請專利範圍第11項所述之方法，進一步包含： 以第一蝕刻程序蝕刻該第二共形層以形成相鄰該閘極結構的第二側壁間隔件的第一區段。
  13. 如申請專利範圍第12項所述之方法，進一步包含：以第二蝕刻程序蝕刻該第一共形層以形成該第二側壁間隔件的第二區段，其中，該第二側壁間隔件的該第一區段是配置在該第二側壁間隔件的該第二區段上方。
  14. 如申請專利範圍第13項所述之方法，其中，該第一蝕刻程序對該第一共形層選擇性蝕刻該第二共形層，而該第二蝕刻程序對該第二共形層選擇性蝕刻該第一共形層。
  15. 如申請專利範圍第11項所述之方法，其中，該第一共形層係由第一低k介電材料組成，而該第二共形層係由具有與該第一低k介電材料的成分不同的第二低k介電材料組成。
  16. 如申請專利範圍第10項所述之方法，其中，該第一側壁間隔件是從第一介電材料和第二介電材料形成，並且進一步包含：形成凹洞在該層堆疊之下；以及以由該第一介電材料組成的第一層、由該第一介電材料組成的第二層、以及由該第二介電材料組成並且配置在該第一層與該第二層之間的直立方向中的第三層填充該凹洞。
  17. 一種用於場效電晶體的結構，該結構包含：複數個奈米片通道層，配置在層堆疊中；源極/汲極區域，連接至該複數個奈米片通道層；閘極結構，包括分別地圍繞該複數個奈米片通道層的複數個區段；第一側壁間隔件，配置為相鄰該閘極結構之側表面；以及 第二側壁間隔件，配置為相鄰該閘極結構之側表面，該第二側壁間隔件以堆疊配置配置在該第一側壁間隔件上方，其中，該第一側壁間隔件係由第一低k介電材料組成，而該第二側壁間隔件係由與該第一低k介電材料的成分不同的第二低k介電材料組成。
  18. 如申請專利範圍第17項所述之結構，進一步包含：複數個內間隔件，配置在該層堆疊中的該複數個奈米片通道層之間，其中，該複數個內間隔件係由該第一低k介電材料組成，而該複數個內間隔件將該源極/汲極區域與該閘極結構的該複數個區段分離。
  19. 如申請專利範圍第17項所述之結構，進一步包含：第一介電層，配置在該複數個奈米片通道層之下；第二介電層，配置在該第一介電層與該複數個奈米片通道層之間；以及第三介電層，配置在該第二介電層與該第一介電層之間，其中，該第三介電層係由該第一低k介電材料組成。
  20. 如申請專利範圍第17項所述之結構，其中，該第一低k介電材料是基於氧化物的介電材料，而該第二低k介電材料是基於氮化物的介電材料。
TW108125638A 2018-08-21 2019-07-19 形成有犧牲間隔件之奈米片場效電晶體 TWI708283B (zh)

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