TWI686898B - 半導體裝置及其形成方法 - Google Patents
半導體裝置及其形成方法 Download PDFInfo
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- TWI686898B TWI686898B TW107122289A TW107122289A TWI686898B TW I686898 B TWI686898 B TW I686898B TW 107122289 A TW107122289 A TW 107122289A TW 107122289 A TW107122289 A TW 107122289A TW I686898 B TWI686898 B TW I686898B
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Abstract
一種半導體裝置的形成方法包括:將晶粒嵌置於模塑材
料中;在所述模塑材料及所述晶粒之上形成第一介電層;在所述第一介電層的背對所述晶粒的上表面之上形成導電線;以及在所述第一介電層及所述導電線之上形成第二介電層。所述方法更包括:形成延伸穿過所述第一介電層或所述第二介電層的第一溝渠開口,其中所述第一溝渠的縱向軸線平行於所述導電線的縱向軸線,且其中在所述第一溝渠開口的底部處不暴露出任何導電特徵;以及使用導電材料填充所述第一溝渠開口以形成第一接地溝渠。
Description
本發明的實施例是有關於一種半導體裝置及其形成方法。
隨著半導體技術進一步發展,已使用新的封裝技術來容置縮小的晶粒大小。舉例而言,在積體扇出型(integrated fan-out,InFO)封裝中,將晶粒嵌置於模塑材料中。在所述模塑材料及所述晶粒之上形成重佈線結構,所述重佈線結構包括形成於一或多個介電層中的導電特徵,例如導電線及通孔。所述重佈線結構的導電特徵電性耦合至所述晶粒。
本發明的一實施例提供一種半導體裝置,包括:晶粒;模塑材料,圍繞所述晶粒;第一介電層,位於所述晶粒及所述模塑材料之上,所述第一介電層具有面對所述晶粒的第一表面及與所述第一表面相對的第二表面;導電線,沿所述第一介電層的所
述第二表面;第二介電層,位於所述第一介電層及所述導電線之上,所述第二介電層具有面對所述晶粒的第三表面及與所述第三表面相對的第四表面;第一導電結構,與所述導電線的至少第一部分在側向上間隔開且平行於所述導電線的至少所述第一部分,其中所述第一導電結構被配置成電性接地或連接至電源;以及第二導電結構,與所述導電線的至少所述第一部分在側向上間隔開且平行於所述導電線的至少所述第一部分,其中所述導電線的所述第一部分位於所述第一導電結構與所述第二導電結構之間,其中所述第一導電結構的第一部分及所述第二導電結構的第一部分位於所述第一表面與所述第二表面之間或者位於所述第三表面與所述第四表面之間,且其中所述第一導電結構的所述第一部分的縱向軸線及所述第二導電結構的所述第一部分的縱向軸線平行於所述第一介電層的所述第一表面。
本發明的一實施例提供一種半導體裝置的形成方法,包括:將晶粒嵌置於模塑材料中;在所述模塑材料及所述晶粒之上形成第一介電層;在所述第一介電層的背對所述晶粒的上表面之上形成導電線;在所述第一介電層及所述導電線之上形成第二介電層;形成延伸穿過所述第一介電層或所述第二介電層的第一溝渠開口,其中所述第一溝渠的縱向軸線平行於所述導電線的縱向軸線,且其中在所述第一溝渠開口的底部處不暴露出任何導電特徵;以及使用導電材料填充所述第一溝渠開口以形成第一接地溝渠。
本發明的一實施例提供一種半導體裝置,包括:晶粒,包括在所述晶粒的正面側上位於同一介電層中的導電柱與線通孔,其中所述導電柱及所述線通孔電性耦合至所述晶粒的相應的接觸墊,且其中所述線通孔包括與所述晶粒的所述正面側平行地延伸的導電路徑;模塑材料,圍繞所述晶粒;第一介電層,位於所述模塑材料及所述晶粒之上;第一導電線,位於所述第一介電層之上;以及導電結構,延伸穿過所述第一介電層且連接至所述線通孔及所述第一導電線,其中所述導電結構的縱向軸線平行於所述晶粒的所述正面側。
100:半導體裝置
101:載具
102:黏著劑層
103:介電層
104:線通孔
105:模塑材料
105U:模塑材料的上表面
106:半導體基底
107:半導體晶粒
108:介電材料
109、109A:晶粒連接件
110:介電層
111:通孔開口
112:溝渠開口
112L:溝渠開口的縱向軸線
113:導電線/導電特徵/訊號線
113A、113B:導電線
113S:訊號線/導電線
113SL:訊號線的縱向軸線
115:導電通孔/導電特徵
115’:通孔
117:接地溝渠
117’:導電特徵
117B:接地溝渠的下部部分
117C:接地溝渠的中心軸線
117L:接地溝渠的縱向軸線
117T:接地溝渠的上部部分
118:分立區段
120:介電層
121:開口
122:開口
123:導電線/導電特徵
125:導電通孔/導電特徵
126:接地平面
127:接地溝渠
127B:底部部分
127C:接地溝渠的中心軸線
127M:接地溝渠的中間部分
127T:接地溝渠的頂部部分
128:導電通孔/導電特徵/接地通孔
128C:接地通孔的中心軸線
128L:線
128T:接地通孔的上部部分
129:導電線/導電特徵
130:介電層
131:開口
133:導電線/導電特徵
135:導電通孔/導電特徵
140:介電層
147:凸塊下金屬
149、149A:外部連接件
200、300、400、400’、500、600、600’、600”、700、800:半導體裝置
1010、1020、1030、1040、1050、1060:步驟
A-A、B-B、C-C、D-D、E-E、F-F、G-G、H-H、I-I、J-J、K-K、L-L、M-M、N-N、O-O、P-P、Q-Q、R-R、S-S、T-T、U-U:橫截面
D1:距離
D2:寬度
GND:接觸墊
H1、H2、H3、H4、H5:高度
L1、L2:長度
P1:接觸墊/電源接觸墊
P2:接觸墊
結合附圖閱讀以下詳細說明,會最佳地理解本揭露的各個態樣。應注意,根據本行業中的標準慣例,各種特徵並非按比例繪製。事實上,為論述清晰起見,可任意增大或減小各種特徵的尺寸。
圖1至圖9以及圖10A至圖10D示出根據實施例處於各種製作階段處的半導體裝置的剖視圖。
圖11A至圖11C示出根據實施例的半導體裝置的剖視圖。
圖12A至圖12C示出根據實施例的半導體裝置的剖視圖。
圖13A至圖13D示出根據實施例的半導體裝置的剖視圖。
圖14A至圖14E示出根據實施例的半導體裝置的剖視圖。
圖15A至圖15D示出根據實施例的半導體裝置的剖視圖。
圖15E及圖15F各自示出根據一些實施例的半導體裝置的剖視圖。
圖16A至圖16D示出根據實施例的半導體裝置的剖視圖。
圖17A至圖17D示出根據實施例的半導體裝置的剖視圖。
圖18示出根據一些實施例製作半導體裝置的方法的流程圖。
以下揭露內容提供用於實施本發明的不同特徵的許多不同的實施例或實例。以下闡述組件及排列的具體實例以簡化本揭露內容。當然,該些僅為實例且不旨在進行限制。舉例而言,以下說明中將第一特徵形成在第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例,且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。
另外,在本文中為便於說明,可使用例如「在...下面(beneath)」、「在...之下(below)」、「下部(lower)」、「在...之上(above)」、「上部(upper)」等空間相對關係用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對關係用語旨在除圖中所繪示的取向以外亦包括裝置在使用或操作中的不同取向。所述裝置可具有其他取向(旋轉90度或其他取向),且本文中所用的空間相對關係描述語可同樣相應地進行解釋。
本揭露的實施例論述了有關半導體裝置的形成,且更具體而言有關在半導體封裝中形成電性接地屏蔽結構用於降低或消除訊號線之間的串擾。根據一些實施例,在半導體封裝的重佈線結構中形成接地溝渠。接地溝渠設置在傳輸承載資訊的訊號的導電線的相對側上。在一些實施例中,在接地溝渠的頂部上形成接地通孔,且所述接地通孔連接至所述接地溝渠。在一些實施例中,在導電線、接地溝渠以及接地通孔(若被形成)之上形成接地平面,且所述接地平面連接至接地溝渠及接地通孔(若被形成)。接地溝渠、接地通孔(若被形成)以及接地平面(若被形成)在導電線周圍形成接地屏蔽結構(例如,被接地的導電結構)以減少導電線與鄰近導電線之間的串擾。
圖1至圖9以及圖10A至圖10D示出根據實施例處於各種製作階段處的半導體裝置100的剖視圖。在圖1中,將半導體晶粒107(亦可被稱為晶粒、晶片或積體電路(integrated circuit,IC)晶粒)附裝至載具101。載具101可由例如矽、聚合物、聚合物複合物、金屬箔、陶瓷、玻璃、環氧樹脂玻璃、氧化玻、膠帶、或其他適當的材料等材料製成用於結構性支撐。在載具101之上沈積或層壓可充當釋放層的介電層103,如在圖1所示的實例中所示。介電層103可為感光性的且在後續的載具剝離過程中可易於藉由向載具101上照射例如紫外(ultra-violet,UV)光而自載具101分離。舉例而言,介電層103可為由明尼蘇達州聖保羅市的3M公司製成的光熱轉換(light-to-heat-conversion,LTHC)塗層。
如圖1所示,經由黏著劑層102而將晶粒107附裝至介電層103,黏著劑層102可為晶粒附裝膜(die attaching film,DAF)、膠水層或其他適當的材料。在被黏附至介電層103之前,可根據可適用的製造製程對晶粒107進行處理以在晶粒107中形成積體電路。舉例而言,晶粒107包括半導體基底106,例如經摻雜或未經摻雜的矽、或絕緣體上半導體(semiconductor-on-insulator,SOI)基底的主動層。半導體基底可包含其他半導體材料,例如:鍺;包含碳化矽、砷化鎵、磷化鎵、氮化鎵、磷化銦、砷化銦及/或銻化銦的化合物半導體;包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP的合金半導體;或其組合。亦可使用其他基底,例如多層式基底或梯度基底。例如電晶體、二極體、電容器、電阻器等裝置(圖中未示出)可形成在半導體基底106中及/或形成在半導體基底106上,且可藉由互連結構(圖中未示出)進行互連,所述互連結構由例如金屬化圖案形成於半導體基底106上的一或多個介電層中以形成積體電路。
晶粒107更包括用於進行外部連接的墊(亦被稱為接觸墊,圖中未示出),例如鋁墊。所述墊位於可被稱為晶粒107的主動側或正面側的一側上。鈍化膜(圖中未示出)位於晶粒107的主動側上且位於所述墊的一些部分上。形成穿過所述鈍化膜至所述墊的開口。晶粒連接件109(例如,包含例如銅等金屬的導電柱)位於穿過鈍化膜的開口中且機械性地及電性地耦合至相應的墊。
晶粒連接件109可藉由例如鍍覆或類似製程而形成。晶粒連接件109電性耦合晶粒107的積體電路。
介電材料108位於晶粒107的主動側上,例如位於鈍化膜及晶粒連接件109上。介電材料108在側向上包封晶粒連接件109,且介電材料108在側向上與晶粒107共同終端。介電材料108可為:聚合物,例如聚苯並噁唑(polybenzoxazole,PBO)、聚醯亞胺(polyimide)、苯並環丁烯(benzocyclobutene,BCB)等;氮化物,例如氮化矽等;氧化物,例如氧化矽;磷矽酸鹽玻璃(phosphosilicate glass,PSG)、硼矽酸鹽玻璃(borosilicate glass,BSG)、硼摻雜磷矽酸鹽玻璃(boron-doped phosphosilicate glass,BPSG)等;或其組合,且可例如藉由旋轉塗佈、層壓、化學氣相沈積(chemical vapor deposition,CVD)等形成。
接下來,在圖2中,在介電層103之上形成模塑材料105以包封晶粒107。舉例而言,模塑材料105可包含環氧樹脂、有機聚合物、添加有或不添加有二氧化矽系填料或玻璃填料的聚合物、或其他材料。在一些實施例中,模塑材料105包含在施加時為凝膠型液體的液體模塑化合物(liquid molding compound,LMC)。模塑材料105在施加時亦可包含液體或固體。作為另外一種選擇,模塑材料105可包含其他絕緣及/或包封材料。在一些實施例中,模塑材料105是利用晶圓級模塑製程進行施加。模塑材料105可利用例如壓縮模塑(compressive molding)、傳遞模塑(transfer molding)或其他適當的方法進行模塑。
接下來,在一些實施例中,利用固化製程對模塑材料105進行固化。所述固化製程可包括:利用退火製程或其他加熱製程將模塑材料105加熱至預定的溫度達預定時間段。所述固化製程亦可包括紫外光曝光製程、紅外能量曝光製程、紫外光曝光製程與紅外能量曝光製程的組合、或紫外光曝光製程及紅外能量曝光製程與加熱製程的組合。作為另外一種選擇,模塑材料105可利用其他方法進行固化。在一些實施例中,不包括固化製程。
在一些實施例中,在沈積並固化(若需要)模塑材料105之後,執行例如化學機械研磨(chemical mechanical polish,CMP)等平坦化製程以移除模塑材料105的頂部部分並暴露出晶粒107的晶粒連接件109的上表面。
接下來,在圖3中,在模塑材料105及晶粒107之上形成介電層110。介電層110是由例如PBO、聚醯亞胺、BCB等聚合物形成。在其他實施例中,介電層110是由以下材料形成:氮化物,例如氮化矽;氧化物,例如氧化矽;PSG、BSG、BPSG等;或類似材料。介電層110可由例如旋轉塗佈、化學氣相沈積、層壓等或其組合等任意可接受的沈積製程形成。可執行例如化學機械研磨等平坦化製程,以達成介電層110的平坦上表面。
接下來,利用例如微影及/或蝕刻製程將介電層110圖案化以形成開口,例如通孔開口111及溝渠開口112。在圖3所示的實例中,通孔開口111暴露出晶粒連接件109。圖3中的溝渠開口112暴露出模塑材料105,且溝渠開口112的底部未暴露出任何導
電特徵(例如,導電線、通孔或晶粒連接件)。在一些實施例中,溝渠開口112的縱向軸線112L平行於模塑材料105的上表面150U,所述上表面150U平行於設置在模塑材料105之上的介電層(例如,110、120、130及140,參見圖9)的上表面。在一些實施例中,溝渠開口112的縱向軸線112L平行於在後續製程中形成的訊號線113S的縱向軸線113SL(參見圖10D)。如圖3中所示的溝渠開口112的位置僅為非限制性實例。溝渠開口112可形成於任意其他適當的區之上,例如形成於晶粒107之上(例如,形成於晶粒107正上方)。在其中溝渠開口112形成於晶粒107正上方的實施例中,溝渠開口112形成於晶粒107的不具有導電特徵(例如,圖3所示的晶粒連接件109、或圖17A所示的線通孔104)的區域之上,因此溝渠開口112的底部不暴露出任意導電特徵。該些及其他變化完全旨在被包括於本揭露的範圍內。
接下來,在圖4中,在介電層110之上及/或在介電層110中形成導電特徵,例如導電線113、導電通孔115以及接地溝渠117。所述導電特徵可由適當的導電材料(例如,銅、鈦、鎢、鋁等)形成。所述導電特徵可藉由例如以下方式形成:在介電層110之上及在開口111/112中形成晶種層、在晶種層之上形成具有所設計圖案的經圖案化的光阻、在所設計的圖案中及在晶種層之上鍍覆(例如,電鍍覆或無電鍍覆)導電材料、以及移除光阻及晶種層的上面未形成導電材料的一些部分。在其他實施例中,導電特徵是藉由例如以下減法製程而形成,即:藉由在介電層110
的上表面之上毯覆式沈積導電材料、然後對所沈積的導電材料進行圖案化及/或蝕刻。
注意,接地溝渠117是藉由以導電材料填充溝渠開口112(參見圖3)而形成。在一些實施例中,由於溝渠開口112的底部未暴露出任何導電特徵,因此無導電特徵連接至(例如,物理性地接觸)接地溝渠117的底表面。因此,在一些實施例中,接地溝渠117的底表面物理性地接觸介電材料(例如,模塑材料105)。與此相反,導電通孔115被形成為使得導電通孔115的底表面與下伏導電特徵連接(例如,物理性地接觸)。相較於可具有垂直於模塑材料105的上表面105U的縱向軸線的導電通孔115,接地溝渠117具有平行於模塑材料105的上表面105U的縱向軸線117L(亦參見圖10D)。在一些實施例中,在圖4所示的實例中,接地溝渠117經由接地溝渠117的上表面或經由接地溝渠117的設置在介電層110的上表面以上的上部部分而電性耦合至其他導電特徵(例如,導電線113A及113B)。在下文中參照圖10A至圖10D論述接地溝渠的更多細節。
接下來,在圖5中,在介電層110以及在圖4中所形成的導電特徵(例如,113、115及117)之上形成介電層120。介電層120可包含與介電層110相同或類似的材料,且可由與介電層110相同或類似的形成方法形成,因此對此不再予以贅述。可執行例如化學機械研磨等平坦化製程來達成介電層120的平坦上表面。
接下來,可例如藉由光微影及/或蝕刻製程對介電層120
進行圖案化以形成開口121及122。在一些實施例中,開口121暴露出下伏導電特徵,例如導電線113及/或導電通孔115,且開口122暴露出接地溝渠117。
接下來,在圖6中,在介電層120之上及/或在介電層120中形成導電特徵,例如導電線123/129以及導電通孔125/128。導電特徵123、129、125及128可由與導電特徵113及115相同或類似的材料形成,且可利用與導電特徵113及115相同或類似的方法形成,因此對此不再予以贅述。
在所示實施例中,導電通孔128電性地及機械性地耦合至接地溝渠117。如在圖6中所示,導電通孔128亦可藉由設置在介電層120的上表面之上的導電線129而連接在一起。在一些實施例中,位於同一接地溝渠117之上的導電通孔128沿可與接地溝渠117的縱向軸線117L重疊或平行(參見圖10C)的線設置。如以下將更詳細地論述,導電通孔128電性接地且與接地溝渠117形成電性接地屏蔽結構以降低串擾,因此導電通孔128在下文的論述中亦被稱為接地通孔128。在下文中參照圖10A至圖10D論述接地通孔128的更多細節。
接下來,在圖7中,在介電層120及導電特徵123、125、128及129上方形成介電層130,並將介電層130圖案化以形成開口131,所述開口131暴露出相應的下伏導電特徵。介電層130可包含與介電層110相同或類似的材料,且可由與介電層110相同或類似的形成方法形成,因此對此不再予以贅述。可執行例如
化學機械研磨等平坦化製程來達成介電層130的平坦上表面。
接下來,在圖8中,在介電層130之上及/或在介電層130中形成導電特徵,例如導電線133以及導電通孔135。所述導電特徵(例如,133、135)可由於導電特徵113及115相同或類似的材料形成,且可利用與導電特徵113及115相同或類似的方法形成,因此對此不再予以贅述。在一些實施例中,位於介電層130之上的導電特徵亦可包括將電性耦合至在後續處理中形成的凸塊下金屬(under-bump-metallurgy,UBM)結構的導電墊,所述導電墊電性耦合至導電特徵133/135中的一或多者。
接下來參照圖9,在介電層130及導電特徵133/135之上形成介電層140。介電層140可包含與介電層110相同或類似的材料,且可由與介電層110相同或類似的形成方法形成,因此對此不再予以贅述。可執行例如化學機械研磨等平坦化製程來達成介電層140的平坦上表面。
接下來,利用例如光微影及/或蝕刻製程在介電層140中形成開口(圖中未示出)以暴露出位於介電層130之上的導電墊。一旦已形成開口,便可形成與導電墊電性接觸的凸塊下金屬147。在實施例中,凸塊下金屬147包含三層導電材料,例如鈦層、銅層及鎳層。然而,存在適於形成凸塊下金屬147的材料及層的諸多適當的排列方式,例如鉻/鉻-銅合金/銅/金此種排列方式、鈦/鈦鎢/銅此種排列方式、或銅/鎳/金此種排列方式。可用於凸塊下金屬147的任意適當的材料或材料層完全旨在包括於本揭露的範
圍內。
凸塊下金屬147可藉由在介電層140之上、且沿穿過介電層140至導電墊的開口的內部形成每一層而形成。可利用鍍覆製程(例如,電化學鍍覆)來執行對每一層的形成,但作為另一選擇可根據所使用的材料而使用其他形成製程,例如濺鍍、蒸發或電漿增強型化學氣相沈積(PECVD)製程。一旦已形成凸塊下金屬的各層,便可執行適當的光微影及/或一或多個蝕刻製程來移除所述層的一些部分且使凸塊下金屬147具有所設計的形狀,例如圓形、八邊形、方形、或矩形形狀,但作為另外一種選擇可形成任意適當的形狀。
仍參照圖9,在凸塊下金屬147上形成外部連接件149。在實施例中,外部連接件149是接觸凸塊(例如,受控塌陷晶片連接(controlled collapse chip connection,C4)凸塊)且包含例如錫等材料或其他適當的材料,例如銀或銅。在其中外部連接件149是錫焊料凸塊的實施例中,外部連接件149可藉由經由任意適當的方法(例如,蒸發、電鍍、印刷、焊料傳遞、球置放等)首先形成錫層。一旦已在結構上形成了錫層,便執行回焊以便將材料成型為具有例如約80微米的直徑的凸塊形狀。
然而,儘管以上已將外部連接件149闡述為C4凸塊,但該些外部連接件149僅旨在為說明性的且並非旨在限制所述實施例。確切而言,作為另外一種選擇可利用任意適當類型的外部接觸件,例如微凸塊、銅柱、銅層、鎳層、無鉛(lead free,LF)
層、無電鍍鎳鈀浸金(electroless nickel electroless palladium immersion gold,ENEPIG)層、Cu/LF層、Sn/Ag層、Sn/Pb、或其組合等。可針對外部連接件149利用任意適當的外部連接件以及用於形成外部連接件的任意適當的製程,且所有此類外部連接件皆完全旨在被包括於所述實施例的範圍內。
如在圖3至圖9中所示,導電特徵(例如,導電線113/導電通孔115(參見圖4)、導電線123/導電通孔125(參見圖6)、以及導電線133/導電通孔135(參見圖8))對往返於晶粒107的訊號進行重路由或重佈線,因此被稱為重佈線層(redistribution layer,RDL)。重佈線層與相關聯的介電層(例如,110、120、130及140)一起被統稱為重佈線結構。
在圖9所示的實例中,接地溝渠117以及接地通孔128經由重佈線結構的導電線及/或導電通孔而電性耦合至一或多個外部連接件149A。在一些實施例中,外部連接件149A電性耦合至電性接地(圖中未示出),因此將接地溝渠117及接地通孔128接地。接地溝渠117以及接地通孔128亦可電性耦合至一或多個晶粒連接件109A,所述晶粒連接件109A被配置成電性接地。在一些實施例中,電性耦合至電性接地(例如,具有與電性接地相同的電壓)的接地溝渠117以及接地通孔128用於提供對電磁干擾(例如,串擾)的屏蔽。在一些實施例中,接地溝渠117以及接地通孔128電性耦合至電源(例如,具有與電源(例如,5伏特或3伏特電源,圖中未示出)相同的電壓)以提供對電磁干擾的屏蔽。
對於高頻電磁訊號(例如,電磁干擾)的解析,系統中的電性接地及電源可被視為被電性短路,且因此接地溝渠117以及接地通孔128在被耦合至電源時亦可提供對電磁干擾的屏蔽。換言之,為提供對電磁干擾的屏蔽,接地溝渠117以及接地通孔128可被直接耦合至電性接地,抑或直接耦合至電源。本文中對各種實施例的論述可使用其中接地溝渠(例如,117)及/或接地通孔(例如,128)被電性耦合(例如,直接耦合)至電性接地以提供對電磁干擾的屏蔽的實例,且應理解,接地溝渠(例如,117)及/或接地通孔(例如,128)亦可被電性耦合(例如,直接耦合)至電源以提供對電磁干擾的屏蔽。換言之,在本文中所論述的各種實施例中,與接地溝渠117及/或接地通孔128耦合以用於電磁屏蔽的電性接地或接地平面(例如,直接耦合至電性接地的銅平面)可被電源或電源平面(例如,直接耦合至電源的銅平面)替代。該些及其他變化完全旨在被包括於本揭露的範圍內。
儘管接地溝渠117及接地通孔128是以與重佈線結構相同的處理步驟形成,但接地溝渠117及接地通孔128並非用於對往返於晶粒107的承載資訊的訊號(例如,載有控制訊號及/或資料訊號的數位波形)進行路由。相反,接地溝渠117及接地通孔128形成被電性接地的導電結構,且所述被電性接地的導電結構充當屏蔽結構以降低或消除相鄰訊號線之間的串擾,如將參照圖10A至圖10D更詳細地論述。
現在參照圖10A,執行載具剝離處理以移除載具101。
在一些實施例中,將圖9所述的半導體裝置100翻轉(圖中未示出),並將外部連接件149附裝至由框架(圖中未示出)支撐的膠帶(圖中未示出)。所述膠帶可為切割膠帶,所述切割膠帶可為用於在後續處理中將半導體裝置100固定在恰當位置的黏著劑。接下來,經由剝離製程自半導體裝置100分離(剝離)載具101。所述剝離製程可利用任意適當的製程(例如,蝕刻、研磨及機械剝除)移除載具101。在一些實施例中,載具101是藉由在載具101的表面上照射雷射或紫外光而被剝離。雷射或紫外光斷開結合至載具101的介電層103的化學鍵,且然後載具101可被輕易地分離。儘管圖中未示出,但可在載具剝離製程之後執行切割處理以將形成在載具101之上的所述多個半導體裝置單體化成個別半導體裝置100。
圖10B及圖10C示出半導體裝置100分別沿橫截面A-A及B-B的剖視圖。注意,橫截面B-B是跨越接地通孔128,而橫截面A-A是位於二個相鄰的接地通孔128之間。參照圖10B,二個接地溝渠117延伸穿過介電層110。導電線113S位於介電層110的上表面之上且位於二個接地溝渠117之間。儘管在圖1至圖9以及圖10A所示的剖視圖中不可見到接地溝渠117中的一者以及導電線113S,但熟習此項技術者在閱讀圖10B至圖10D時將理解,在圖10B至圖10D中所示的特徵(例如,二個接地溝渠117以及導電線113S)是在圖1至圖9中所示的製程流程的對應處理步驟中形成。
參照圖10B,接地溝渠117具有位於介電層110的上表面之上的上部部分117T以及位於介電層110的上表面與介電層110的下表面之間的下部部分117B。在一些實施例中,由於例如用以填充溝渠開口112的沈積製程及/或溝渠開口112的大小等各種因素,上部部分117T的中心區的上表面可低於上部部分117T的周邊區的上表面(例如,較上部部分117T的周邊區的上表面更靠近模塑材料105)。接地溝渠117的被介電層110環繞的下部部分117B自介電層110的面對模塑材料105的下表面延伸至介電層110的背對模塑材料105的上表面,如在圖10B中所示。接地溝渠117的下部部分可具有錐形側壁。換言之,接地溝渠117的下部部分可具有梯形橫截面,此可能是由於由用於形成溝渠開口112的光微影及蝕刻製程導致的溝渠開口112的錐形側壁。
仍參照圖10B,導電線113S(亦被稱為訊號線)傳輸承載訊號的資訊,例如表示控制訊號或資料訊號的數位波形。舉例而言,控制訊號可包括在多個預定電壓電平之間切換的時變電壓。資料訊號可為基帶(base-band)(例如,未調變)訊號或已調變訊號(例如,調變至載波頻率)。資料訊號可載有表示語音、文本、影像、視訊等的資訊位元,且所述資訊位元可利用各種映射及調變方案(例如,幅移鍵控(amplitude shift keying,ASK)、相移鍵控(phase shift keying,PSK)、頻移鍵控(frequency shift keying,FSK)、正交調幅(quadrature amplitude modulation,QAM)等)被映射至資料符號。
隨著在半導體製造中整合密度變得愈來愈高,相鄰訊號線之間的距離變得更近。在間隔距離小的訊號線(例如,導電線113S)之間可經由各種耦合機制(例如,電容耦合、電感耦合或電導耦合)發生串擾。由於串擾,在第一訊號線上傳送的第一訊號可干擾在第二訊號線上傳送的第二訊號,藉此導致第二訊號的畸變並降低第二訊號的訊號完整性。反過來,第二訊號可干擾第一訊號並降低第一訊號的訊號完整性。在本揭露中揭露了屏蔽結構(例如,被接地且自其他附近的訊號線對訊號線進行屏蔽的導電結構)的各種實施例用於降低或消除串擾,因此改善半導體裝置的訊號完整性及效能。
仍參照圖10B,訊號線113S的高度H1小於接地溝渠117的高度H2,其中H1及H2是沿與模塑材料105的上表面垂直的方向量測。換言之,H2/H1的比率大於1。較大的高度H1有助於屏蔽訊號線113S與附近或相鄰的訊號線,因此減少串擾。
在一些實施例中,D1/D2的比率大於或等於0.1且小於或等於5(例如,0.1D1/D2 5),其中D2是訊號線113S的寬度,且D1是訊號線113S與接地溝渠117之間的距離。在一些實施例中,D1/D2的比率是由訊號線(例如,113S)的電磁(EM)場的特性確定的,以確保由接地溝渠(例如,117)提供的有效屏蔽。舉例而言,若D1/D2的比率例如因接地溝渠117太靠近訊號線113S而太小(例如,小於0.1),則訊號線113S的電磁場在接地溝渠117的位置處可太強,且可跨越接地溝渠117以不利地影響位於接地
溝渠117的與訊號線113S相對的側上的另一訊號線(圖中未示出)。另一方面,若D1/D2的比率例如因接地溝渠117遠離訊號線113S而太大(例如,大於5),則在接地溝渠117的位置處的訊號線113S的電磁場可為弱,在此種情形中可能不需要接地溝渠117。圖10B亦示出設置在介電層120的上表面上的導電線129。導電線129設置在接地溝渠117之上,並將接地通孔128(參見圖10A)連接在一起。
圖10C示出圖10A中的半導體裝置100的剖視圖,但是沿橫截面B-B的剖視圖。圖10C類似於圖10B,但具有示出於剖視圖中的接地通孔128。在圖10C所示的實例中,每一接地通孔128具有位於介電層120的上表面上的上部部分128T。接地通孔128的下部部分位於介電層120中且位於接地通孔128的上部部分128T與對應的接地溝渠117的上部部分117T之間。因此,接地通孔128以及對應的接地溝渠117被電性連接。在一些實施例中,接地通孔128與接地溝渠117的總高度H3是訊號線113S的高度H1的二倍或大於二倍(例如,二倍至五倍),其中高度H3以及高度H1是沿與模塑材料105的上表面垂直的方向量測。舉例而言,高度H1可介於約0.5微米與約10微米之間,且根據高度H1,高度H3可介於約2微米與約50微米之間。注意,如圖10C中所示,接地溝渠117的底表面接觸介電材料(例如,模塑材料105),且接地溝渠117的下部部分117B的側壁被介電層110環繞,因此無導電特徵被連接至(例如,直接接觸)接地溝渠117的底表面或
連接至接地溝渠117的下部部分117B。相反,接地溝渠117與另一導電特徵的電性連接是經由接地溝渠117的上部部分117T(例如,經由接地通孔128或經由導電線113A/113B(參見圖4))達成。換言之,在一些實施例中,接地溝渠117與另一導電特徵的電性連接僅經由接地溝渠117的上部部分117T達成。
在圖10C所示的實例中,位於右側的接地通孔128與位於右側的接地溝渠117未對齊,因此位於右側的接地通孔128的中心軸線128C未與下伏接地溝渠117的中心軸線117C對齊(例如,未與中心軸線117C位於同一條線上),但128C及117C可彼此平行且可皆垂直於模塑材料105的上表面。與此相反,位於左側的接地通孔128與位於左側的接地溝渠117垂直對齊(例如,在位於左側的接地溝渠117正上方),因此位於左側的接地通孔128的中心軸線與位於左側的接地溝渠117的中心軸線對齊(例如,與接地溝渠117的中心軸線位於同一條線上)。藉由容許接地通孔128與下伏接地溝渠117未對齊,對圖案化製程(例如,光微影製程)的準確性的要求降低,且容許較大的誤差容限,此容許進行低成本生產且亦有助於提高製造製程的良率。接地通孔128與下伏接地溝渠117的未對齊亦使得更易於圖案化出半導體裝置100的佈局。
圖10C是非限制性實例。可存在其他構型。舉例而言,位於左側及右側的接地通孔128可各自與對應的下伏接地溝渠117對齊。作為另一實例,位於左側及右側的接地通孔128可各自與
對應的下伏接地溝渠117未對齊。在圖10C所示的實例中,位於右側的接地通孔128與訊號線113S之間的側向距離(例如,沿圖10C中的水平方向量測)大於位於右側的接地溝渠117與訊號線113S之間的側向距離。換言之,位於右側的接地通孔128較下伏接地溝渠117更遠離訊號線113S。此為實例且並不旨在進行限制,且可存在其他構型。舉例而言,接地通孔128可較下伏接地溝渠117更靠近訊號線113S。作為另一實例,圖10C中所示的接地通孔128中的一者(例如,位於左側或位於右側的一者)可較下伏接地溝渠117更靠近訊號線113S,而接地通孔128中的另一者可較下伏接地溝渠117更遠離訊號線113S。該些及其他變化完全旨在被包括在本揭露的範圍內。
圖10D是圖10B中的半導體裝置100沿橫截面C-C的剖視圖。如圖10D所示,接地溝渠117的縱向軸線117L平行於訊號線113S的縱向軸線113L。因此,接地溝渠117平行於訊號線113S的至少所示部分。接地通孔128未位於橫截面C-C中,因此在圖10D中被示出為虛影。在所示實施例中,位於左側的所述多個接地通孔128的中心與下伏接地溝渠117的縱向軸線117L對齊(例如,重疊)。然而,位於右側的所述多個接地通孔128的中心位於與下伏接地溝渠117的縱向軸線117L平行但不重疊的線128L上。注意,接地溝渠117的縱向軸線117L平行於模塑材料105的上表面,如圖10D中所示。通孔(例如,通孔115/125/135以及接地通孔128)的縱向軸線可垂直於模塑材料105的上表面。
如圖10D所示,沿接地溝渠117的縱向軸線117L量測的接地溝渠117的長度L1較沿縱向軸線117L量測的接地通孔128的長度L2大數個數量級(例如,大5倍至100倍,或大於100倍),所述長度L2可與沿117L的方向量測的其他通孔(例如,115/125/135)的長度相同或類似。舉例而言,對於特定製程節點而言,通孔(例如,115)的長度可處於約5微米與約100微米之間的範圍內,接地溝渠(例如,117)的長度L1可處於約25微米與約10000微米之間的範圍內,例如200微米與5000微米之間的範圍內。
注意,電性接地屏蔽結構並非必須沿整個訊號線113S形成。相反,電性接地屏蔽結構可沿訊號線113S的易受串擾影響的一些區段(例如,在其中訊號線113S與另一相鄰訊號線之間的節距為50微米或小於50微米的位置處的區段)形成。作為另一實例,電性接地屏蔽結構可沿一些訊號線113S的載有具有稠密星象圖(dense constellation)的經數位調變的訊號(例如,64-QAM訊號、126-QAM訊號或256 QAM訊號)的一些區段形成,乃因具有稠密星象圖的訊號可對串擾具有更低的耐受性。
可對圖1至圖9以及圖10A至圖10D中所示的實施例進行修改,且所述修改完全旨在被包括在本揭露的範圍內。舉例而言,儘管在圖10A至圖10D中示出了四個介電層(例如,110、120、130及140),但在形成接地屏蔽結構時可使用多於或少於四個介電層。作為另一實例,接地溝渠117被示出為形成於圖10A
至圖10D中所示的最低的(例如,最靠近模塑材料105的)介電層110中,然而,接地溝渠117可形成於其他(例如,更高的)介電層中。此外,可形成多於一層接地溝渠。舉例而言,可在另一下伏接地溝渠117正上方形成一個接地溝渠117並將所述接地溝渠117連接至所述另一下伏接地溝渠117,藉此形成雙層式接地溝渠。此外,可在接地溝渠及/或接地通孔之上形成接地平面並將所述接地平面連接至所述接地溝渠及/或接地通孔,藉此屏蔽訊號線113S免受來自上方的干擾,因此形成包括接地平面、接地溝渠及/或接地通孔的接地屏蔽結構。以下論述說明接地屏蔽結構的不同構型的額外實施例。在以下論述中,除非另有說明,否則不同圖式中相同的數字指代由相同或類似的材料藉由相同或類似的方法形成的相同或類似的組件,因此對此不再予以贅述。
圖11A至圖11C示出根據一些實施例的半導體裝置200的剖視圖。圖11B是圖11A中所示的半導體裝置200的剖視圖,但是沿橫截面D-D的剖視圖。圖11C是圖11B中所示的半導體裝置200的剖視圖,但是沿橫截面E-E的剖視圖。相較於圖10A至圖10D中所示的半導體裝置100,半導體裝置200具有較少的介電層,且不具有接地通孔128以及連接接地通孔128的導電線129。因此,圖11A至圖11C所示的電性接地屏蔽結構僅包括接地溝渠117。
如圖11A及圖11B所示,半導體裝置200具有位於模塑材料105上方的二個介電層110及120。接地溝渠117形成在介電
層110中。訊號線113S位於介電層110上方且位於接地溝渠117之間。圖11A示出直接形成於模塑材料105上方(例如,接觸模塑材料105)且電性耦合至接地溝渠117的通孔115’。在一些實施例中,由於例如金屬密度控制等製造考量因素,接地溝渠117的長度(例如,沿圖11C中的方向117L量測)可受到某些約束,且可能未被形成至充分的長度,在此種情形中,通孔115’可被形成為靠近接地溝渠117並與接地溝渠117電性耦合。通孔115’可充當接地溝渠117的延伸以進一步增強接地溝渠117的電磁屏蔽能力。亦在圖12A、圖13A、圖14A、圖15A、圖16A及圖17A中示出了類似於通孔115’的通孔。儘管在圖11A中示出了一個通孔115’,但可形成多於一個通孔115’。該些及其他變化完全旨在被包括於本揭露的範圍內。
在各種實施例中相同或類似組件的尺寸可具有相同或類似的關係。舉例而言,在圖11B中訊號線113S的高度H1小於在圖11B中接地溝渠117的高度H2,其中H1及H2是沿與模塑材料105的上表面垂直的方向量測的。換言之,H2/H1的比率大於1。在一些實施例中,在圖11B中D1/D2的比率大於或等於0.1且小於或等於5(例如,0.1D1/D2 5),其中D2是訊號線113S的寬度,且D1是訊號線113S與接地溝渠117之間的距離。圖11C示出接地溝渠117的縱向軸線117L,縱向軸線117L平行於訊號線113S的縱向軸線113SL且平行於模塑材料105的上表面。
為簡潔起見,在各種實施例中相同或類似特徵的尺寸、
以及在各種實施例中相同或類似特徵的尺寸之間的關係(例如,較大、較小、比率)可不針對每一實施例進行贅述,而應理解,以上論述的各種特徵的尺寸及尺寸的關係可應用於以下論述的相同或類似特徵。
圖12A至圖12C示出根據一些實施例的半導體裝置300的剖視圖。圖12B是圖12A中所示的半導體裝置300的剖視圖,但是沿橫截面F-F的剖視圖。圖12C是圖12B中所示的半導體裝置300的剖視圖,但是沿橫截面G-G的剖視圖。相較於圖11A至圖11C中所示的半導體裝置200,半導體裝置300具有較多(例如,三個而非二個)介電層,且接地溝渠127形成於介電層120中而非最低的(例如,最靠近模塑材料105的)介電層110中。因此,圖12A至圖12C所示的電性接地屏蔽結構包括接地溝渠127。
如圖12B所示,接地溝渠127具有位於介電層110的上表面上的底部部分127B、位於介電層120的上表面上的頂部部分127T、以及位於介電層120中且連接底部部分127B與頂部部分127T的中間部分127M。在圖12B所示的實例中,中間部分127M窄於頂部部分127T以及底部部分128B。在圖12B中訊號線113S的高度H1小於在圖12B中接地溝渠127的高度H4,其中H1及H4是沿與模塑材料105的上表面垂直的方向量測的。
圖13A至圖13C示出根據一些實施例的半導體裝置400的剖視圖。圖13B是圖13A中所示的半導體裝置400的剖視圖,
但是沿橫截面H-H的剖視圖。圖13C是圖13B中所示的半導體裝置400的剖視圖,但是沿橫截面I-I的剖視圖。
半導體裝置400的電性接地屏蔽結構包括位於介電層110中的下部接地溝渠117以及位於介電層120中的上部接地溝渠127。因此,圖13A至圖13C所示的實施例可被視為圖11A至圖11C所示的實施例與圖12A至圖12C所示的實施例的組合。根據一些實施例,在圖13B中訊號線113S的高度H1小於包括下部接地溝渠117以及上部接地溝渠127的電性接地屏蔽結構的高度H5。具體而言,H5/H1的比率可介於約2與約8之間。
在圖13B中,上部接地溝渠127的中心軸線與下伏下部接地溝渠117的中心軸線對齊(例如,位於同一條線上)。在替代實施例中,如由圖13D所示的半導體裝置400’所示,位於右側的上部接地溝渠127的中心軸線127C未與位於右側的下部接地溝渠117的中心軸線117C對齊(例如,與中心軸線117C位於不同的線上)。在一些實施例中,位於左側及位於右側的下部接地溝渠117之間的距離不同於位於左側及位於右側的上部接地溝渠127之間的距離。儘管圖中未示出,但上部接地溝渠127(例如,位於左側及位於右側的上部接地溝渠127)可皆與相應的下伏下部接地溝渠117未對齊。該些及其他變化完全旨在被包括於本揭露的範圍內。
圖14A至圖14E示出根據一些實施例的半導體裝置500的剖視圖。圖14B及圖14C是圖14A中所示的半導體裝置500的剖視圖,但是分別沿橫截面J-J及K-K的剖視圖。圖14D及圖14E
是圖14B中所示的半導體裝置500的剖視圖,但是分別沿橫截面M-M及L-L的剖視圖。
半導體裝置500類似於圖10A至圖10D所示的半導體裝置100,但在模塑材料105上方具有三個介電層而非四個介電層。此外,半導體裝置500具有形成在介電層120的上表面上的接地平面126,所述接地平面126電性連接至接地通孔128及接地溝渠117。因此,半導體裝置500的電性接地屏蔽結構包括接地溝渠117、接地通孔128以及接地平面126。
參照圖14B及圖14C,接地溝渠117延伸穿過介電層110,且具有位於介電層110的上表面上的上部部分117T。接地通孔128形成於位於接地溝渠117之上方的介電層120中。接地平面126形成在介電層120的上表面上,且在訊號線113S以及設置在訊號線113S的相對側上的接地通孔128上方連續延伸。接地平面電性地及機械性地耦合至接地通孔128。
如圖14C所示,位於左側的接地通孔128與下伏接地溝渠117對齊(例如,設置在下伏接地溝渠117正上方)。位於右側的接地通孔128未與下伏接地溝渠117對齊。舉例而言,位於右側的接地通孔128的中心軸線128C與下伏接地溝渠117的中心軸線117C未對齊(例如,未與下伏接地溝渠117的中心軸線117C位於同一條線上)。
如圖14D所示,位於左側的所述多個接地通孔128的中心與下伏接地溝渠117的縱向軸線117L對齊(例如,重疊)。然
而,位於右側的所述多個接地通孔128的中心位於與下伏接地溝渠117的縱向軸線117L平行但不重疊的線128L上。
圖14E示出自位於左側的接地通孔128(被示出為虛影)連續延伸至位於右側的接地通孔128的接地平面126。圖14E中亦示出在位於左側的接地通孔128與位於右側的接地通孔之間的訊號線113S(被示出為虛影)。接地平面126電性連接至接地通孔128以及接地溝渠117,因此屏蔽訊號線113S免受來自上方的干擾以進一步降低串擾。
可存在各種變化且所述變化完全旨在被包括在本揭露的範圍內。在一些實施例中,位於左側及右側的接地通孔128與相應的下伏接地溝渠117對齊。在一些實施例中,位於左側及右側的接地通孔128與相應的下伏接地溝渠117未對齊。作為另一實例,訊號線113S與接地通孔128(例如,位於左側或右側的接地通孔128)之間的側向距離可大於或小於訊號線113S與位於接地通孔128下方的接地溝渠117之間的側向距離。
圖15A至圖15D示出根據一些實施例的半導體裝置600的剖視圖。圖15B是圖15A中所示的半導體裝置600的剖視圖,但是沿橫截面N-N的剖視圖。圖15C及圖15D是圖15B中所示的半導體裝置600的剖視圖,但是分別沿橫截面O-O及P-P的剖視圖。
半導體裝置600類似於圖14A至圖14E所示的半導體裝置500,但以上部接地溝渠127代替接地通孔128。為區分接地溝
渠117(形成在介電層110中)與上部接地溝渠127(形成在介電層120中),在對半導體裝置600的論述中將接地溝渠117稱為下部接地溝渠。因此,半導體裝置600的電性接地屏蔽結構包括下部接地溝渠117、上部接地溝渠127以及接地平面126。
圖15C示出平行於訊號線113S延伸的下部接地溝渠。圖15D示出在上部接地溝渠127(示出為虛影)及訊號線113S(示出為虛影)之上連續延伸的接地平面126。
在圖15B中,上部接地溝渠127被示出為與下伏下部接地溝渠117垂直對齊(例如,位於下伏下部接地溝渠117正上方)。此僅為非限制性實例。在另一實施例中,圖15E中所示的半導體裝置600’具有與半導體裝置600類似的結構,但位於右側的上部接地溝渠127與下伏下部接地溝渠117未對齊。舉例而言,位於右側的上部接地溝渠127的中心軸線127C未與下伏接地溝渠117的中心軸線117C位於同一條線上。在又一實施例中,如圖15F所示,半導體裝置600”具有與半導體裝置600類似的結構,但位於左側及位於右側的上部接地溝渠127與相應的下伏接地溝渠117未對齊。具體而言,位於右側的上部接地溝渠127的中心軸線127C較下伏接地溝渠117的中心軸線117C更遠離訊號線113,且位於左側的上部接地溝渠127的中心軸線127C較下伏接地溝渠117的中心軸線117C更靠近訊號線113。可存在各種修改且所述修改完全旨在被包括於本揭露的範圍內。
圖16A至圖16D示出根據一些實施例的半導體裝置700
的剖視圖。圖16B是圖16A中所示的半導體裝置700的剖視圖,但是沿橫截面Q-Q的剖視圖。圖16C及圖16D是圖16B中所示的半導體裝置700的剖視圖,但是分別沿橫截面S-S及R-R的剖視圖。
半導體裝置700類似於圖15A至圖15D所示的半導體裝置600,但移除了下部接地溝渠117。因此,半導體裝置700的電性接地屏蔽結構包括上部接地溝渠127及接地平面126。
如圖16B所示,上部接地溝渠127具有位於介電層120的上表面上的底部部分127B以及位於介電層120中且位於底部部分127B之上的中間部分127M。上部接地溝渠127的位於介電層120之上的一些部分與接地平面126融合,且可被視為接地平面126的一部分,因此未標注出。在圖16B所示的實例中,底部部分127B的寬度大於中間部分127M的寬度。
圖17A至圖17D示出根據一些實施例的半導體裝置800的剖視圖。圖17B是圖17A中所示的半導體裝置800的剖視圖,但是沿橫截面T-T的剖視圖。圖17C及圖17D是圖17B中所示的半導體裝置800的剖視圖,但是沿橫截面U-U的剖視圖。
參照圖17A,導電特徵117’是利用與其他實施例中(例如,圖11A至圖11C中)的接地溝渠117類似的材料及形成方法而形成於介電層110中。然而,不同於被電性接地並用作屏蔽結構(的一部分)以降低串擾的接地溝渠117,導電特徵117’電性連接至線通孔104並用以減少直流電阻,此繼而減小半導體裝置800
的IR壓降。
如圖17A至圖17C所示,線通孔104包括形成於晶粒107的介電材料108中的導電路徑(參見圖17C中的104),所述介電材料108環繞晶粒連接件109。晶粒連接件109在垂直於晶粒107的上表面的方向上路由訊號(例如,電流)且具有例如圓形、卵形、方形或矩形等橫截面(例如,在俯視圖中),而線通孔104在實質上平行於晶粒107的上表面的平面中路由訊號且具有包括導電線的一些區段的橫截面(例如,在俯視圖中)。舉例而言,圖17C示出作為連接晶粒107的多個接觸墊P1(亦可被稱為電源接觸墊)的導電線的線通孔104,所述接觸墊P1電性耦合至被表示為電源域1的晶粒107的電源。圖17C亦示出晶粒107的多個接觸墊P2,所述多個接觸墊P2電性耦合至被表示為電源域2的晶粒107的另一電源。圖17C進一步示出晶粒107的多個接觸墊GND,所述多個接觸墊GND電性耦合至電性接地。晶粒107可具有其他接觸墊,例如用於路由控制及資料訊號的接觸墊,此在圖17C中未示出。
圖17D類似於圖17C,但具有在圖17C的剖視圖中不可見的導電特徵117’,導電特徵117’被示出為虛影以說明導電特徵117’相對於線通孔104的位置。如圖17D中所示,在一些實施例中,導電特徵117’形成於線通孔104正上方,且因此與線通孔104重疊。在一些實施例中,導電特徵117’可與線通孔104完全重疊,且因此包括連接電源接觸墊P1的連續導電路徑。在其他實施例
中,導電特徵117’可被形成在線通孔104的一些區段之上,且因此包括彼此分隔開的分立區段118。在一些實施例中,導電特徵117’的縱向軸線平行於晶粒107的正面側,或平行於模塑材料105的上表面。
導電特徵117’有效地增加線通孔104的厚度及/或體積,因此減少電源接觸墊P1的直流電阻,此繼而減小晶粒107的IR壓降。在先進的半導體製程節點中,電源電壓自較高的電壓(例如,5伏特)降低至較低的電壓(例如,1.2伏特)。由於晶片的功耗可因更多的功能被整合至晶片中而保持相同或甚至增大,因此晶片的電流增大。增大的晶片電流對晶片的IR壓降提出更多嚴格的要求,乃因在較高電壓(例如,5伏特)設計中相同的直流電阻可在較低電壓(例如,1.2伏特)設計中導致不可接受的IR壓降。圖17A至圖17D所示的實施例減小電源接觸墊P1的直流電阻,因此使得先進製程節點中的晶片設計更易於滿足嚴格的IR壓降要求。
圖18示出根據一些實施例一種形成半導體裝置的方法的流程圖。應理解,圖18中所示的實施例方法僅為諸多可能的實施例方法的實例。此項技術中具有通常知識者將認識到諸多變化、替代及修改形式。舉例而言,如圖18所示的各種步驟可被添加、移除、替代、重新排列及重複。
參照圖18,在步驟1010處,將晶粒嵌置於模塑材料中。在步驟1020處,在所述模塑材料及所述晶粒之上形成第一介電
層。在步驟1030處,在所述第一介電層的背對所述晶粒的上表面之上形成導電線。在步驟1040處,在所述第一介電層及所述導電線之上形成第二介電層。在步驟1050處,形成延伸穿過所述第一介電層及所述第二介電層中的第一者的第一溝渠,其中所述第一溝渠的縱向軸線平行於所述導電線的縱向軸線。在步驟1060處,使用導電材料填充所述第一溝渠以形成第一接地溝渠。
實施例可達成一些優點。電性接地屏蔽結構可以與形成重佈線結構相同的處理步驟形成。由於所揭露實施例的簡單結構,達成了低生產成本。模擬結果已示出所揭露的實施例有效地降低串擾。舉例而言,相較於不具有本發明所揭露的特徵的設計,本發明所揭露的實施例在串擾方面自1GHz至約10GHz提供約5分貝或大於5分貝的降低。此外,在圖17A至圖17D中所揭露的實施例提供可減小晶粒107的直流電阻及IR壓降的低成本設計,此可改善晶粒107的效能並有助於滿足在先進的製程節點中對晶片設計的嚴格的IR壓降要求。
在實施例中,一種半導體裝置包括:晶粒;模塑材料,圍繞所述晶粒;第一介電層,位於所述晶粒及所述模塑材料之上,所述第一介電層具有面對所述晶粒的第一表面及與所述第一表面相對的第二表面;導電線,沿所述第一介電層的所述第二表面;以及第二介電層,位於所述第一介電層及所述導電線之上,所述第二介電層具有面對所述晶粒的第三表面及與所述第三表面相對的第四表面。所述半導體裝置更包括:第一導電結構,與所述導
電線的至少第一部分在側向上間隔開且平行於所述導電線的至少所述第一部分,其中所述第一導電結構被配置成電性接地或連接至電源;以及第二導電結構,與所述導電線的至少所述第一部分在側向上間隔開且平行於所述導電線的至少所述第一部分,其中所述導電線的所述第一部分位於所述第一導電結構與所述第二導電結構之間,其中所述第一導電結構的第一部分及所述第二導電結構的第一部分位於所述第一表面與所述第二表面之間或者位於所述第三表面與所述第四表面之間,且其中所述第一導電結構的所述第一部分的縱向軸線及所述第二導電結構的所述第一部分的縱向軸線平行於所述第一介電層的所述第一表面。在實施例中,所述導電線具有第一高度,其中所述第一導電結構及所述第二導電結構具有大於所述第一高度的第二高度,其中所述第一高度及所述第二高度是沿與所述模塑材料的上表面垂直的方向量測。在實施例中,所述第一導電結構及所述第二導電結構延伸穿過所述第一介電層及所述第二介電層。在實施例中,所述第一導電結構及所述第二導電結構中的每一者包括位於所述第一介電層中的下部接地溝渠及位於所述第二介電層中的上部接地溝渠,所述下部接地溝渠連接至所述上部接地溝渠。在實施例中,所述第一導電結構的所述下部接地溝渠與所述第二導電結構的所述下部接地溝渠之間的距離不同於所述第一導電結構的所述上部接地溝渠與所述第二導電結構的所述上部接地溝渠之間的距離。在實施例中,所述第一導電結構包括延伸穿過所述第一介電層的第一接地溝
渠,且所述第二導電結構包括延伸穿過所述第一介電層的第二接地溝渠。在實施例中,所述第一導電結構更包括位於所述第二介電層中且連接至所述第一接地溝渠的第一多個接地通孔,且所述第二導電結構更包括位於所述第二介電層中且連接至所述第二接地溝渠的第二多個接地通孔。在實施例中,所述半導體裝置更包括位於所述第二介電層的所述第四表面之上的接地平面,其中所述接地平面在所述導電線、所述第一導電結構及所述第二導電結構之上延伸,且其中所述接地平面連接至所述第一多個接地通孔及所述第二多個接地通孔。在實施例中,所述第一導電結構包括延伸穿過所述第二介電層的第一接地溝渠,且所述第二導電結構包括延伸穿過所述第二介電層的第二接地溝渠。在實施例中,所述半導體裝置更包括位於所述第二介電層的所述第四表面之上的接地平面,其中所述接地平面在所述導電線、所述第一接地溝渠及所述第二接地溝渠之上延伸,且其中所述接地平面連接至所述第一接地溝渠及所述第二接地溝渠。
在實施例中,一種半導體裝置的形成方法包括:將晶粒嵌置於模塑材料中;在所述模塑材料及所述晶粒之上形成第一介電層;在所述第一介電層的背對所述晶粒的上表面之上形成導電線;在所述第一介電層及所述導電線之上形成第二介電層;形成延伸穿過所述第一介電層或所述第二介電層的第一溝渠開口,其中所述第一溝渠的縱向軸線平行於所述導電線的縱向軸線,且其中在所述第一溝渠開口的底部處不暴露出任何導電特徵;以及使
用導電材料填充所述第一溝渠開口以形成第一接地溝渠。在實施例中,所述第一接地溝渠的底部接觸所述模塑材料。在實施例中,所述第一接地溝渠的第一高度大於所述導電線的第二高度,其中所述第一高度及所述第二高度是沿與所述第一介電層的所述上表面垂直的方向量測。在實施例中,所述第一溝渠開口延伸穿過所述第一介電層,其中所述方法更包括:形成延伸穿過所述第二介電層的第二溝渠開口,其中所述第二溝渠開口的縱向軸線平行於所述導電線的所述縱向軸線;以及使用所述導電材料填充所述第二溝渠開口以形成第二接地溝渠,所述第二接地溝渠電性地及機械性地耦合至所述第一接地溝渠。在實施例中,所述導電線與所述第一接地溝渠之間的第一側向距離不同於所述導電線與所述第二接地溝渠之間的第二側向距離。在實施例中,所述第一溝渠開口延伸穿過所述第一介電層,其中所述方法更包括在所述第二介電層中形成多個接地通孔,其中所述多個接地通孔在與所述導電線的所述縱向軸線平行的線上對齊,且其中所述多個接地通孔電性地及機械性地耦合至所述第一接地溝渠。在實施例中,所述方法更包括在所述第二介電層的上表面之上形成接地平面,其中所述接地平面在所述導電線及所述多個接地通孔之上延伸,且其中所述接地平面電性地及機械性地耦合至所述多個接地通孔。
在實施例中,一種半導體裝置包括:晶粒,包括在所述晶粒的正面側上位於同一介電層中的導電柱與線通孔,其中所述導電柱及所述線通孔電性耦合至所述晶粒的相應的接觸墊,且其
中所述線通孔包括與所述晶粒的所述正面側平行地延伸的導電路徑;模塑材料,圍繞所述晶粒;第一介電層,位於所述模塑材料及所述晶粒之上;第一導電線,位於所述第一介電層之上;以及導電結構,延伸穿過所述第一介電層且連接至所述線通孔及所述第一導電線,其中所述導電結構的縱向軸線平行於所述晶粒的所述正面側。在實施例中,所述線通孔電性耦合至所述晶粒的被配置成耦合至電源電壓的接觸墊。在實施例中,所述裝置更包括:第二導電線,位於所述第一介電層之上;以及通孔,位於所述第一介電層中,其中所述通孔連接至所述第二導電線及所述導電柱。
以上概述了若干實施例的特徵,以使熟習此項技術者可更佳地理解本揭露的各個態樣。熟習此項技術者應知,其可容易地使用本揭露作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到,該些等效構造並不背離本揭露的精神及範圍,而且他們可在不背離本揭露的精神及範圍的條件下對其作出各種改變、代替、及變更。
100:半導體裝置
101:載具
103:介電層
105:模塑材料
107:半導體晶粒
109A:晶粒連接件
110:介電層
117:接地溝渠
120:介電層
128:導電通孔/導電特徵/接地通孔
130:介電層
140:介電層
147:凸塊下金屬
149、149A:外部連接件
Claims (10)
- 一種半導體裝置,包括:晶粒;模塑材料,圍繞所述晶粒;第一介電層,位於所述晶粒及所述模塑材料之上,所述第一介電層具有面對所述晶粒的第一表面及與所述第一表面相對的第二表面;導電線,沿所述第一介電層的所述第二表面;第二介電層,位於所述第一介電層及所述導電線之上,所述第二介電層具有面對所述晶粒的第三表面及與所述第三表面相對的第四表面;第一導電結構,與所述導電線的至少第一部分在側向上間隔開且平行於所述導電線的至少所述第一部分,其中所述第一導電結構被配置成電性接地或連接至電源;以及第二導電結構,與所述導電線的至少所述第一部分在側向上間隔開且平行於所述導電線的至少所述第一部分,其中所述導電線的所述第一部分位於所述第一導電結構與所述第二導電結構之間,其中所述第一導電結構的第一部分及所述第二導電結構的第一部分位於所述第一表面與所述第二表面之間或者位於所述第三表面與所述第四表面之間,且其中所述第一導電結構的所述第一部分的縱向軸線及所述第二導電結構的所述第一部分的縱向軸線平行於所述第一介電層的所述第一表面。
- 如申請專利範圍第1項所述的半導體裝置,其中所述導電線具有第一高度,其中所述第一導電結構及所述第二導電結構具有大於所述第一高度的第二高度,其中所述第一高度及所述第二高度是沿與所述模塑材料的上表面垂直的方向量測。
- 如申請專利範圍第1項所述的半導體裝置,其中所述第一導電結構包括延伸穿過所述第一介電層的第一接地溝渠,且所述第二導電結構包括延伸穿過所述第一介電層的第二接地溝渠。
- 如申請專利範圍第1項所述的半導體裝置,其中所述第一導電結構包括延伸穿過所述第二介電層的第一接地溝渠,且所述第二導電結構包括延伸穿過所述第二介電層的第二接地溝渠。
- 如申請專利範圍第4項所述的半導體裝置,更包括位於所述第二介電層的所述第四表面之上的接地平面,其中所述接地平面在所述導電線、所述第一接地溝渠及所述第二接地溝渠之上延伸,且其中所述接地平面連接至所述第一接地溝渠及所述第二接地溝渠。
- 一種半導體裝置的形成方法,包括:將晶粒嵌置於模塑材料中;在所述模塑材料及所述晶粒之上形成第一介電層;在所述第一介電層的背對所述晶粒的上表面之上形成導電線;在所述第一介電層及所述導電線之上形成第二介電層;形成延伸穿過所述第一介電層或所述第二介電層的第一溝渠 開口,其中所述第一溝渠的縱向軸線平行於所述導電線的縱向軸線,且其中在所述第一溝渠開口的底部處不暴露出任何導電特徵;以及使用導電材料填充所述第一溝渠開口以形成第一接地溝渠。
- 如申請專利範圍第6項所述的方法,其中所述第一溝渠開口延伸穿過所述第一介電層,其中所述方法更包括:形成延伸穿過所述第二介電層的第二溝渠開口,其中所述第二溝渠開口的縱向軸線平行於所述導電線的所述縱向軸線;以及使用所述導電材料填充所述第二溝渠開口以形成第二接地溝渠,所述第二接地溝渠電性地及機械性地耦合至所述第一接地溝渠。
- 如申請專利範圍第6項所述的方法,其中所述第一溝渠開口延伸穿過所述第一介電層,其中所述方法更包括在所述第二介電層中形成多個接地通孔,其中所述多個接地通孔在與所述導電線的所述縱向軸線平行的線上對齊,且其中所述多個接地通孔電性地及機械性地耦合至所述第一接地溝渠。
- 一種半導體裝置,包括:晶粒,包括在所述晶粒的正面側上位於同一介電層中的導電柱與線通孔,其中所述導電柱及所述線通孔電性耦合至所述晶粒的相應的接觸墊,且其中所述線通孔包括與所述晶粒的所述正面側平行地延伸的導電路徑;模塑材料,圍繞所述晶粒; 第一介電層,位於所述模塑材料及所述晶粒之上;第一導電線,位於所述第一介電層之上;以及導電結構,延伸穿過所述第一介電層且連接至所述線通孔及所述第一導電線,其中所述導電結構的縱向軸線平行於所述晶粒的所述正面側。
- 如申請專利範圍第9項所述的裝置,其中所述線通孔電性耦合至所述晶粒的被配置成耦合至電源的接觸墊。
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