TWI678781B - 焊盤結構和積體電路晶粒 - Google Patents

焊盤結構和積體電路晶粒 Download PDF

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TWI678781B
TWI678781B TW107108330A TW107108330A TWI678781B TW I678781 B TWI678781 B TW I678781B TW 107108330 A TW107108330 A TW 107108330A TW 107108330 A TW107108330 A TW 107108330A TW I678781 B TWI678781 B TW I678781B
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conductive layer
pad structure
conductive
layer
patent application
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TW201901893A (zh
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陳俊良
Chun-Liang Chen
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聯發科技股份有限公司
Mediatek Inc.
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Abstract

本發明公開一種焊盤結構，形成在積體電路晶粒上，包括：第一導電層，形成在積體電路晶粒的上表面上並具有中空部分；介電層，覆蓋該第一導電層；第二導電層，形成在該介電層上並電連接到該第一導電層；以及鈍化層，覆蓋該第二導電層，並具有暴露該第二導電層以接收接合引線的開口。由於第一導電層具有中空部分，並且在第一導電層上方的第二導電層接收接合引線，第一導電層的機械應力可以得到釋放。並且當接合引線接合到第二導電層上時，第一導電層不容易發生例如破裂等損壞，從而降低了焊盤結構在引線接合期間損壞的可能。

Description

焊盤結構和積體電路晶粒
本發明涉及半導體技術領域，尤其涉及一種焊盤結構和積體電路晶粒。
常規IC（integrated circuit，積體電路）晶粒（die）包括用於接收接合引線（bonding wire）的焊盤（pad）結構。在將接合引線接合（bond）到焊盤結構期間，接合力（bonding force）可能導致焊盤結構的損壞。特別係當焊盤結構包括UTM（ultra thick metal，超厚金屬）層時，由於UTM層的機械應力，焊盤結構在引線接合期間更有可能損壞。
因此，如何降低焊盤結構在引線接合期間損壞的可能，成為本領域亟需解決的問題。
有鑑於此，本發明提供一種焊盤結構和積體電路晶粒，以降低焊盤結構在引線接合期間損壞的可能。
根據本發明的第一方面，公開一種焊盤結構，形成在積體電路晶粒上，包括： 第一導電層，形成在積體電路晶粒的上表面上並具有中空部分； 介電層，覆蓋該第一導電層； 第二導電層，形成在該介電層上並電連接到該第一導電層；以及 鈍化層，覆蓋該第二導電層，並具有暴露該第二導電層以接收接合引線的開口。
根據本發明的第二個方面，公開一種積體電路晶粒，包括： 矽基板；以及 焊盤結構，該焊盤結構為如上述的一種焊盤結構，並形成在該矽基板上。
本發明提供的焊盤結構由於第一導電層具有中空部分，並且在第一導電層上方的第二導電層接收接合引線，第一導電層的機械應力可以得到釋放。並且當接合引線接合到第二導電層上時，第一導電層不容易發生例如破裂等損壞，從而降低了焊盤結構在引線接合期間損壞的可能。
以下描述為本發明實施的較佳實施例。以下實施例僅用來例舉闡釋本發明的技術特徵，並非用來限制本發明的範疇。在通篇說明書及申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域技術人員應可理解，製造商可能會用不同的名詞來稱呼同樣的元件。本說明書及申請專利範圍並不以名稱的差異來作為區別元件的方式，而係以元件在功能上的差異來作為區別的基準。本發明的範圍應當參考後附的申請專利範圍來確定。本發明中使用的術語“元件”、“系統”和“裝置”可以係與電腦相關的實體，其中，該電腦可以係硬體、軟體、或硬體和軟體的結合。在以下描述和申請專利範圍當中所提及的術語“包含”和“包括”為開放式用語，故應解釋成“包含，但不限定於…”的意思。此外，術語“耦接”意指間接或直接的電氣連接。因此，若文中描述一個裝置耦接至另一裝置，則代表該裝置可直接電氣連接於該另一裝置，或者透過其它裝置或連接手段間接地電氣連接至該另一裝置。
對這些實施例進行了詳細的描述係為了使本領域的技術人員能夠實施這些實施例，並且應當理解，在不脫離本發明的精神和範圍情況下，可以利用其他實施例進行機械、化學、電氣和程式上的改變。因此，以下詳細描述並非係限制性的，並且本發明的實施例的範圍僅由所附申請專利範圍第限定。
下面將參考特定實施例並且參考某些附圖來描述本發明，但係本發明不限於此，並且僅由申請專利範圍限制。所描述的附圖僅係示意性的而並非限制性的。在附圖中，為了說明的目的，一些元件的尺寸可能被誇大，而不係按比例繪製。在本發明的實踐中，尺寸和相對尺寸不對應於實際尺寸。
參照第1圖、第2A圖和第2B圖，第1圖示出了根據本發明實施例的設置在基板10上的IC晶粒100的示意圖，第2A圖示出了第1圖的焊盤結構110的俯視圖，第2B圖示出了第2A圖的焊盤結構110沿著2B-2B'方向的橫截面圖。其中，第2A圖中的虛線表示在此方向上不能直接看到的部件，例如111h、115等，因此第2A圖也係視為焊盤結構110的俯視透視圖。第2B圖中的虛線部分，接合引線11表示可以使用接合引線11安裝在此處（114R）。
IC晶粒100設置在基板10上，並通過至少一根接合引線11與基板10電連接。基板10例如係印刷電路板（PCB，printed circuit board）、晶片、半導體封裝裝置等。IC晶粒100包括至少一個焊盤結構110、至少一個半導體結構120和矽基板130。半導體結構120通過焊盤結構110和接合引線11與基板10電連接。半導體結構120形成在矽基板130上並且包括例如至少一個主動部件（例如，電晶體）和/或至少一個被動部件。半導體結構120與焊盤結構110電連接。
如第2B圖所示，焊盤結構110形成在矽基板130上。焊盤結構110包括第一導電層111，介電層112，第二導電層113，鈍化層114和至少一個導電部分115。在一個實施例中，第一導電層111和導電部分115可以由例如銅製成，當然也可以由其他導電材質例如鋁、銀或金屬合金等製成。第二導電層113係這些導電層的最上層並且由例如鋁製成，當然也可以由其他導電材質例如銅、銀或金屬合金等製成。
如第2A圖和第2B圖所示，第一導電層111形成在矽基板130的上表面130u上並且具有至少一個中空部分111h。具體而言，中空部分111h可以係形成在第一導電層111上的凹槽，以將第一導電層111切割開，將第一導電層111切割為零散的、不連續的結構，使第一導電層111不再係完整的一體或一整塊。此外，第一導電層111可以直接形成在矽基板130的上表面130u上，這樣可以使第一導電層111更加穩固，當然第一導電層111也可以通過其他層例如黏合層形成在矽基板130的上表面130u上。第一導電層111具有與矽基板130的上表面130u對齊的下表面111b，本實施例中第一導電層111的下表面111b與矽基板130的上表面130u可以直接接觸並相互平齊，這樣結合後的結構更穩定。
如第2B圖所示，介電層112形成在矽基板130的上表面130u上並覆蓋第一導電層111。第二導電層113形成在介電層112的上表面112u上並且通過複數個導電部分115電連接到第一導電層111。鈍化層114形成在電介質層112上並覆蓋第二導電層113。鈍化層114具有開口114R，開口114R暴露出第二導電層113的部分1131，以接收對應的接合引線11。
由於第一導電層111具有中空部分111h，使第一導電層111不再係完整的一體或一整塊，第一導電層111的機械應力可以得到釋放。此外，當接合引線11接合到第二導電層113的部分1131時，由於第一導電層111不再係完整的一體或一整塊，第一導電層111不容易損壞，例如破裂（crack）。在一個實施例中，第一導電層111係具有大於20K Å（埃米，10-10 米）的厚度的UTM（ultra thick metal，超厚金屬）層。由於第一導電層111具有中空部分111h，因此即使第一導電層111係UTM層，當接合引線11接合到第二導電層113的部分1131時，第一導電層111也不容易損壞。
此外，中空部分111h包括第一中空部111h1，其中第一中空部111h1上下對應於開口114R。如第2A圖和第2B圖所示，第一中空部111h1具有與開口114R的俯視區域A2相等的俯視區域A1，即區域A1的面積與區域A2的面積相等，並且從俯視方向上看，區域A1與區域A2完全重疊。在另一個實施例中，第一中空部111h1的俯視區域A1小於或大於開口114R的俯視區域A2，即區域A1的面積小於或大於區域A2的面積。也就係說，在俯視圖方向，中空部分111h至少與開口114R部分重疊。開口114R可以對應於中空部分111h的位置進行設置。設有對應開口114R的下方區域的第一中空部111h1，不僅可以使第一導電層111的機械應力可以得到釋放，可以有效避免第一導電層111的損壞。此外，當接合引線11接合到從開口114R暴露的部分1131時，第一中空部111h1的區域在引線接合期間遭受到較大或最大的接合力。由於第一中空部111h1的設置，使得第一導電層111在第一中空部111h1的區域並沒有設置導電層部分，第一導電層111的機械應力得到有效地釋放，在第一中空部111h1的區域所受的接合力無法損壞到第一導電層111，因此第一導電層111不易被較大或最大的接合力所破壞。因此，本發明可以增加IC晶粒100的可靠性和/或產量。
此外，中空部分111h還包括複數個第二中空部111h2，第二中空部111h2上下對應於鈍化層114。複數個可以係兩個或更複數個。此外，介電層112可以填充第一中空部111h1和第二中空部111h2，這樣可以加強焊盤結構機械強度，在引線接合期間不易發生結構坍塌或凹陷等損壞。如第2A圖所示，每個第二中空部111h2呈沿著矽基板130的上表面130u的方向延伸的條形，然而，上述第一中空部和第二中空部的舉例並不意味著對本發明的限制。
如第2B圖所示，焊盤結構110具有至少一個通孔112h，該通孔112h從介電層112的上表面112u穿過介電層112到達第一導電層111。每個通孔112h填充有相應的導電部分115。導電部分115可以係將銅、鋁、銀或金屬合金等材質，形成于通孔112h中。導電部分115連接第一導電層111和第二導電層113，具體的說，導電部分115電連接第一導電層111和第二導電層113。
如第2A圖和第2B圖所示，每個導電部分115係沿著矽基板130的上表面130u的方向延伸的條狀。條狀彼此之間間隔開，不直接連接。本實施例中條狀之間可通過第二導電層113連接。導電部分115可以提供用於增強EM（electromagnetic，電磁）性能的足夠的面積。此外，導電部分115為施加到接合引線11的電流提供足夠的流動面積，並且因此可以防止焊盤結構110燒壞。由於導電部分115可以保持或增強EM性能，所以可以解決裂紋問題，而不犧牲EM性能。
如第2A圖所示，第一導電層111具有形成在第一導電層111的複數個拐角（corner）上的複數個倒角C1。倒角C1可以減小第一導電層111的面積，使得焊盤結構110變成緊湊的焊盤。儘管圖中未示出，但第二導電層113還具有形成在第二導電層113的複數個拐角上的複數個倒角。另外，第一導電層111的俯視區域的輪廓具有與第二導電層113相似或相同的輪廓。此外，倒角還可以減小焊盤結構所受到的機械應力，特別係在拐角處所受的應力，使得焊盤結構整體上更加穩固。
另外，如第2B圖所示，第二導電層113的至少一個外側表面（邊界）相對於第一導電層111的至少一個外側表面（邊界）凹進去。在另一個實施例中，第二導電層113的至少一個外側表面相對於第一導電層111的至少一個外側表面突出來，或者第二導電層113的至少一個外側表面與第一導電層111的至少一個外側表面對齊。也就是說，第二導電層113的外輪廓與第一導電層111的外輪廓在豎直方向上可以平齊或不平齊，而不平齊包括第二導電層113的外輪廓相對於第一導電層111的外輪廓凹進去或凸出來。
第3圖示出了根據本發明另一實施例的焊盤結構210的示意圖。焊盤結構210包括第一導電層111、介電層（圖未示）、第二導電層113、鈍化層（圖未示）以及至少一個導電部分215。在本實施例中，導電部分215包括環狀部2151和與環狀部2151連接的複數個條狀部2152。環狀部2151可以係閉環部或開環部。設置與條狀部2152連接的環狀部2151可以讓條狀部相互連接，便於佈線、接線等。在另一個實施例中，條狀部2152中的至少一個可以與環狀部2151分隔開（即與環狀部不連接）。此外，如第3圖所示，條狀部2152可以係交錯的連接到環狀部2151的兩個相對的側邊上。也可以採用其他的佈置方式，例如條狀部2152均連接到環狀部2151的一個側邊上，或者一部分條狀部2152連接到環狀部2151的一個或兩個相對的側邊，其他一部分條狀部2152與環裝部2151不連接。在其他實施例中，導電部分215可以以直線、曲線或直線與曲線的組合延伸，其中，該導電部分215延伸的方向可以是指沿焊盤結構的高度（深度）方向，例如第2B圖中的豎直方向。在第2B圖中，導電部分115是以直線延伸連接第一導電層111和第二導電層113。而在其他實施例中，導電部分115可以以曲線或直線與曲線的組合或其他線型延伸，以連接第一導電層111和第二導電層113。
在另一個實施例中，第一導電層具有至少一個中空部分，其中中空部分的橫截面形狀/延伸形式可以係條形、點狀、圓形、多邊形、環形等。中空部分的橫截面形狀/延伸形式可以相同或不同。只要第一導電層可以釋放機械應力以防止在引線接合期間焊盤結構被損壞即可，本發明的本實施例不限制中空部分的橫截面形狀/延伸形式。另外，中空部分的數量不限於本發明的實施例所示出的數量。
在另一個實施例中，焊盤結構包括至少一個導電部分，其中導電部分可以係條形、點狀、圓形、多邊形、環形等。導電部分的橫截面形狀/延伸形式可以相同或不同。只要導電部分可以保持或提高EM性能即可，本發明的本實施例不限制導電部分的橫截面形狀/延伸形式。另外，導電部分的數量不限於本發明的實施例所示出的數量。
儘管已經根據目前被認為係最實用和優選的實施例描述了本發明，但係應該理解，本發明不必限於所公開的實施例。相反，意圖覆蓋包括在所附申請專利範圍第書的精神和範圍內的各種修改和類似佈置，這些修改和範圍應符合最寬泛的解釋，以涵蓋所有這些修改和類似結構。
儘管已經對本發明實施例及其優點進行了詳細說明，但應當理解的係，在不脫離本發明的精神以及申請專利範圍所定義的範圍內，可以對本發明進行各種改變、替換和變更。所描述的實施例在所有方面僅用於說明的目的而並非用於限制本發明。本發明的保護範圍當視所附的申請專利範圍所界定者為准。本領域技術人員皆在不脫離本發明之精神以及範圍內做些許更動與潤飾。
100‧‧‧IC晶粒
10‧‧‧基板
11‧‧‧接合引線
110、210‧‧‧焊盤結構
120‧‧‧半導體結構
130‧‧‧矽基板
111‧‧‧第一導電層
112‧‧‧介電層
113‧‧‧第二導電層
114‧‧‧鈍化層
115、215‧‧‧導電部分
130u、112u‧‧‧上表面
111h‧‧‧中空部分
111b‧‧‧下表面
114R‧‧‧開口
111h1‧‧‧第一中空部
111h2‧‧‧第二中空部
112h‧‧‧通孔
C1‧‧‧倒角
1131‧‧‧部分
2151‧‧‧環狀部
2152‧‧‧條狀部
A1、A2‧‧‧區域
通過閱讀後續的詳細描述和實施例可以更全面地理解本發明，該實施例參照附圖給出，其中： 第1圖示出了根據本發明實施例的設置在基板上的IC晶粒的示意圖； 第2A圖示出了第1圖的焊盤結構的俯視圖； 第2B圖示出了第2A圖的焊盤結構沿著2B-2B'方向的橫截面圖； 第3圖示出了根據本發明另一實施例的焊盤結構的示意圖。

Claims (12)

  1. 一種焊盤結構，形成在積體電路晶粒上，包括：第一導電層，形成在該積體電路晶粒的上表面上；介電層，覆蓋該第一導電層；第二導電層，形成在該介電層上並電連接到該第一導電層；以及鈍化層，覆蓋該第二導電層，並具有暴露該第二導電層以接收接合引線的開口；其中該第一導電層具有第一中空部及複數個第二中空部，該第一中空部上下對應於該開口，且該複數個第二中空部上下對應於該鈍化層；其中該複數個第二中空部將該第一導電層分隔為複數個部分；該焊盤結構還包括與該第一導電層的該複數個部分相對應的複數個導電部分，其中每個導電部分電連接相對應的該第一導電層的部分與該第二導電層。
  2. 如申請專利範圍第1項所述的焊盤結構，其中該第一導電層直接形成在該積體電路晶粒的矽基板的上表面上。
  3. 如申請專利範圍第1項所述的焊盤結構，其中該第一導電層具有與該積體電路晶粒的矽基板的上表面對齊的下表面。
  4. 如申請專利範圍第1項所述的焊盤結構，其中還包括：通孔，穿過該介電層；其中每個該導電部分，形成在對應的該通孔內。
  5. 如申請專利範圍第4項所述的焊盤結構，其中該導電部分為條狀。
  6. 如申請專利範圍第1項所述的焊盤結構，其中該中空部分填充有該介電層。
  7. 如申請專利範圍第1項所述的焊盤結構，其中該第一中空部具有與該開口的面積相等的面積。
  8. 如申請專利範圍第1項所述的焊盤結構，其中每個第二中空部呈沿著該積體電路晶粒的上表面的方向延伸的條形。
  9. 如申請專利範圍第4項所述的焊盤結構，其中該導電部分以直線、曲線或直線與曲線的組合延伸。
  10. 如申請專利範圍第4項所述的焊盤結構，其中該導電部分包括環狀部以及複數個與該環狀部連接的條狀部。
  11. 如申請專利範圍第1項所述的焊盤結構，其中該第一導電層具有形成在該第一導電層的複數個拐角上的複數個倒角。
  12. 一種積體電路晶粒，包括：矽基板；以及焊盤結構，該焊盤結構為如申請專利範圍第1項所述的一種焊盤結構，並形成在該矽基板上。
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