TWI669559B - 金屬結構及其製作方法與應用之顯示面板 - Google Patents

金屬結構及其製作方法與應用之顯示面板 Download PDF

Info

Publication number
TWI669559B
TWI669559B TW107103680A TW107103680A TWI669559B TW I669559 B TWI669559 B TW I669559B TW 107103680 A TW107103680 A TW 107103680A TW 107103680 A TW107103680 A TW 107103680A TW I669559 B TWI669559 B TW I669559B
Authority
TW
Taiwan
Prior art keywords
substrate
patterned
tantalum oxide
layer
oxide layer
Prior art date
Application number
TW107103680A
Other languages
English (en)
Other versions
TW201928480A (zh
Inventor
王碩宏
林俊男
吳佳聰
郭吉庭
李格睿
李家宏
張家銘
Original Assignee
友達光電股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 友達光電股份有限公司 filed Critical 友達光電股份有限公司
Publication of TW201928480A publication Critical patent/TW201928480A/zh
Application granted granted Critical
Publication of TWI669559B publication Critical patent/TWI669559B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/1368Active matrix addressed cells in which the switching element is a three-electrode device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28568Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising transition metals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31127Etching organic layers
    • H01L21/31133Etching organic layers by chemical means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H01L23/53252Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H01L23/53266Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/1262Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/133302Rigid substrates, e.g. inorganic substrates
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line
    • G02F1/136295Materials; Compositions; Manufacture processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Ceramic Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

金屬結構包括圖案化鉬鉭氧化物層以及圖案化金屬層。圖案化鉬鉭氧化物層設置於一第一基板上,其中該圖案化鉬鉭氧化物層中鉭的原子百分比含量係約介於2%至12%之間,鉬的原子百分比含量與氧的原子百分比含量皆大於鉭的原子百分比含量。圖案化金屬層設置於該圖案化鉬鉭氧化物層上。

Description

金屬結構及其製作方法與應用之顯示面板
本發明是關於一種金屬結構及其製作方法與應用之顯示面板。
液晶顯示面板由於具有外型輕薄、耗電量少以及應用範圍廣等特性,故已成為目前顯示器的主流商品。一方面,為了達到更寬廣的視覺效果,窄邊框逐漸成為液晶顯示面板的發展目標。另一方面,由於液晶顯示面板內的導線會反射外界的光線而影響視覺效果,現今常在液晶顯示面板內設置黑色矩陣層,在防止導線反射外界光線的同時,卻也造成開口率下降、顯示亮度降低的問題。
因此,如何發展出窄邊框或全平面無邊框、能有效降低光線反射、且不降低顯示亮度的顯示面板,是當前的目標。
於本發明之多個實施方式中,藉由設置圖案化鉬鉭氧化物層以及圖案化金屬層,能將主動元件陣列基板鄰近使 用者(亦即主動元件陣列基板提供顯示面)。根據本發明之部分實施方式,金屬結構包括圖案化鉬鉭氧化物層以及圖案化金屬層。圖案化鉬鉭氧化物層,設置於第一基板上,但本發明不以此為限。其中該圖案化鉬鉭氧化物層中鉭的原子百分比含量係約介於2%至12%之間,鉬的原子百分比含量與氧的原子百分比含量皆大於鉭的原子百分比含量。圖案化金屬層設置於該圖案化鉬鉭氧化物層上。
於本發明之部分實施方式中,圖案化鉬鉭氧化物層中氧的原子百分比含量係約介於5%至60%之間。
於本發明之部分實施方式中,圖案化鉬鉭氧化物層的厚度係介於約50埃(Å)~約600埃(Å)之間。
於本發明之部分實施方式中,圖案化金屬層的厚度係介於約50埃(Å)~約10000埃(Å)之間。
於本發明之部分實施方式中,圖案化鉬鉭氧化物層於可見光範圍內的反射率介於約2%至約20%之間。
於本發明之部分實施方式中,金屬結構之側表面與底表面之間具有一夾角,且該夾角約介於10度至80度之間。
根據本發明之部分實施方式,顯示面板包含第一基板、第二基板、顯示介質層、圖案化鉬鉭氧化物層以及圖案化金屬層。第一基板具有外表面、內表面、以及連接外表面與內表面之第一側邊,且外表面作為顯示面板之顯示面。第二基板具有外表面、內表面、以及連接外表面與內表面之第二側邊,且第二基板之內表面對於第一基板之內表面,其中,第一側邊與第二側邊位於顯示面板之同一側,且第一側邊實質上對 齊或超出第二側邊。顯示介質層設置於第一基板與第二基板之間。圖案化鉬鉭氧化物層設置於第一基板之內表面。圖案化金屬層設置於圖案化鉬鉭氧化物層與第二基板之內表面之間。
於本發明之部分實施方式中,顯示面板包含背光元件,用以向第二基板提供一光線,其中第二基板位於第一基板與背光元件之間,且光線依序經過第二基板、顯示介質層與第一基板。
於本發明之部分實施方式中,圖案化金屬層包括閘極線、閘極、共通線、資料線、源極或汲極之其中至少一者。
於本發明之部分實施方式中,圖案化鉬鉭氧化物層中鉭的原子百分比含量係約介於2%至12%之間,且鉬的原子百分比含量與氧的原子百分比含量皆大於鉭的原子百分比含量。
於本發明之部分實施方式中,圖案化鉬鉭氧化物層中氧的原子百分比含量係約介於5%至60%之間。
於本發明之部分實施方式中,圖案化鉬鉭氧化物層的厚度係介於約50埃(Å)~約600埃(Å)之間。
根據本發明之部分實施方式,製作金屬結構的方法包含提供一第一基板;於該第一基板之內表面上形成一鉬鉭氧化物層,其中該鉬鉭氧化物層包括一鉬鉭氧化物,其中該鉬鉭氧化物中鉭的原子百分比含量係約介於2%至12%之間,且鉬的原子百分比含量與氧的原子百分比含量皆大於鉭的原子百分比含量;於該鉬鉭氧化物層上形成一金屬層;以及對該鉬鉭氧化物層與該金屬層進行一圖案化製程,以形成一圖案化鉬 鉭氧化物層以及一圖案化金屬層。
於本發明之部分實施方式中,對該鉬鉭氧化物層與該金屬層進行一圖案化製程之步驟包含於金屬層上形成圖案化光阻層:以及採用酸性蝕刻液,以圖案化光阻層為遮罩對鉬鉭氧化物層與金屬層進行蝕刻。
於本發明之部分實施方式中,對鉬鉭氧化物層與該金屬層進行圖案化製程之步驟包含採用鹼性去光阻液,去除圖案化光阻層。
於本發明之部分實施方式中,鉬鉭氧化物中氧的原子百分比含量係約介於5%至60%之間。
於本發明之部分實施方式中,於第一基板上形成該鉬鉭氧化物層之步驟包括進行非反應性濺鍍(non-reactive sputtering)製程。
於本發明之部分實施方式中,圖案化鉬鉭氧化物層的厚度係介於約50埃(Å)~約600埃(Å)之間。
於本發明之部分實施方式中,圖案化鉬鉭氧化物層於可見光範圍內的反射率介於約2%至約20%之間。
100‧‧‧顯示面板
110‧‧‧背光元件
112‧‧‧光源
114‧‧‧導光板
120‧‧‧第一基板
122‧‧‧外表面
124‧‧‧內表面
126‧‧‧第一側邊
130‧‧‧顯示介質層
140‧‧‧第二基板
142‧‧‧外表面
144‧‧‧內表面
146‧‧‧第二側邊
150‧‧‧軟性電路板
160‧‧‧電路板
170‧‧‧殼體
180‧‧‧保護層
300‧‧‧金屬結構
310‧‧‧鉬鉭氧化物層
310’‧‧‧圖案化鉬鉭氧化物層
320’‧‧‧圖案化金屬層
330‧‧‧圖案化光阻
400‧‧‧金屬結構
410’‧‧‧圖案化鉬鉭氧化物層
420’‧‧‧圖案化金屬層
DL‧‧‧資料線
GL‧‧‧閘極線
CL‧‧‧共通線
GI‧‧‧閘極介電層
AD‧‧‧主動元件
PE‧‧‧畫素電極
PA‧‧‧畫素區域
SL‧‧‧半導體層
GE‧‧‧閘極
SE‧‧‧源極
DE‧‧‧汲極
Q‧‧‧夾角
1B-1B‧‧‧剖線
1C-1C‧‧‧剖線
UC‧‧‧標記
320‧‧‧金屬層
I‧‧‧顯示面
第1A圖為根據本發明之部分實施方式之顯示面板之剖面示意圖。
第1B圖為本發明之一實施例之顯示面板的上視圖。
第1C圖為沿第1B圖中剖線1B-1B所繪示之剖面示意圖。
第1D圖為沿第1B圖中剖線1C-1C所繪示之剖面示意圖。
第2A圖至第2E圖為根據本發明之部分實施方式之金屬結構於其製作方法的多個階段之剖面示意圖。
第3A圖至第3D圖為根據本發明之部分實施方式之金屬結構的掃描式電子顯微鏡圖。
第4A圖至第4D圖為根據本發明之部分實施方式之金屬結構的穿透式電子顯微鏡圖。
第5圖為根據本發明之部分實施方式之金屬結構的反射頻譜圖。
以下將以圖式揭露本發明之多個實施方式,為明確說明起見,許多實務上的細節將在以下敘述中一併說明。然而,應瞭解到,這些實務上的細節不應用以限制本發明。也就是說,在本發明部分實施方式中,這些實務上的細節是非必要的。此外,為簡化圖式起見,一些習知慣用的結構與元件在圖式中將以簡單示意的方式為之。
在附圖中,為了清楚起見,放大了層、膜、面板、區域等的厚度。在整個說明書中,相同的附圖標記表示相同的元件。應當理解,當諸如層、膜、區域或基板的元件被稱為在另一元件”上”或”連接到”另一元件時,其可以直接在另一元件上或與另一元件連接,或者中間元件可以也存在。相反地,當元件被稱為”直接在另一元件上”或”直接連接到”另一元件時,不存在中間元件。如本文所使用的,”連接”可以指物理及 /或電性連接(或稱為耦接)。然而,電性連接(或稱為耦接)係為二元件間存在其它元件。
應當理解,儘管術語“第一”與“第二”等在本文中可以用於描述各種元件、部件、區域、層及/或部分,但是這些元件、部件、區域、及/或部分不應受這些術語的限制。這些術語僅用於將一個元件、部件、區域、層或部分與另一個元件、部件、區域、層或部分區分開。因此,下面討論的“第一元件”、“部件”、“區域”、“層”、或“部分”可以被稱為第二元件、部件、區域、層或部分而不脫離本文的教導。
這裡使用的術語僅僅是為了描述特定實施例的目的,而不是限制性的。如本文所使用的,除非內容清楚地指示,否則單數形式“一”、“一個”和“該”旨在包括複數形式,包括“至少一個”。“或”表示“及/或”。如本文所使用的,術語“及/或”包括一個或多個相關所列項目的任何和所有組合。還應當理解,當在本說明書中使用時,術語“包括”及/或“包括”指定所述特徵、區域、整體、步驟、操作、元件的存在及/或部件,但不排除一個或多個其它特徵、區域整體、步驟、操作、元件、部件及/或其組合的存在或添加。
此外,諸如“下”或“底部”和“上”或“頂部”的相對術語可在本文中用於描述一個元件與另一元件的關係,如圖所示。應當理解,相對術語旨在包括除了圖中所示的方位之外的裝置的不同方位。例如,如果一個附圖中的裝置翻轉,則被描述為在其他元件的“下”側的元件將被定向在其他元件的“上”側。因此,示例性術語“下”可以包括“下”和“上”的取向,取決 於附圖的特定取向。類似地,如果一個附圖中的裝置翻轉,則被描述為在其它元件“下”或“下方”的元件將被定向為在其它元件“上方”。因此,示例性術語“下”或“下面”可以包括上方和下方的取向。
本文使用的“約”或“實質上”包括所述值和在本領域普通技術人員確定的特定值的可接受的偏差範圍內的平均值,考慮到所討論的測量和與測量相關的誤差的特定數量(即,測量系統的限制)。例如,“約”可以表示在所述值的一個或多個標準偏差內,或±30%、±20%、±10%、±5%內。再者,本文使用的“約”或“實質上”可依光學性質、蝕刻性質或其它性質,來選擇較可接受的偏差範圍或標準偏差,而可不用一個標準偏差適用全部性質。
除非另有定義,本文使用的所有術語(包括技術和科學術語)具有與本發明所屬領域的普通技術人員通常理解的相同的含義。將進一步理解的是,諸如在通常使用的字典中定義的那些術語應當被解釋為具有與它們在相關技術和本發明的上下文中的含義一致的含義,並且將不被解釋為理想化的或過度正式的意義,除非本文中明確地這樣定義。
第1A圖為根據本發明之部分實施方式之顯示面板100之剖面示意圖。顯示面板100包含第一基板120、顯示介質層130以及第二基板140。顯示介質層130設置於第一基板120與第二基板140之間。顯示介質層130可為自發光材料(例如有機發光層或微型發光二極體)或非自發光材料(例如液晶層或電泳層)。於本實施例中,顯示介質層130以非自發光材料 (例如液晶層)為範例,則顯示面板100可選擇性的更設置背光元件110,其用以向第二基板140提供光線。第二基板140位於第一基板120與背光元件110之間,且光線依序經過第二基板140、顯示介質層130與第一基板120。於本實施方式中,背光元件110可採用側入式的設計,且背光元件110可包含光源112、導光板114或其他適合元件,而光源112可包含無機發光源、有機發光源、或其它合適的材料、或前述之組合。於部份實施方式中,背光元件110可採用直下式的設計,且背光元件110可包含光源112或其他適合元件。於其它實施方式中,當顯示介質層130為自發光材料時,可以省略背光元件110的配置。
第一基板120具有外表面122、內表面124以及連接外表面122與內表面124之第一側邊126,且外表面122作為顯示面板100之顯示面I。於本發明之部分實施方式中,第一基板120的內表面124上設置有金屬結構。藉以控制顯示介質層130。舉例而言,第一基板120可為主動元件陣列基板,例如薄膜電晶體基板。
第二基板140具有外表面142、內表面144、以及連接外表面142與內表面144之第二側邊146,且第二基板140之內表面144面對第一基板120之內表面124。於一實施例中,第一側邊126與第二側邊146皆位於顯示面板100之同一側,且第一側邊126實質上對齊或超出第二側邊146。舉例而言,第二基板140可為彩色濾光基板或一般基板。
顯示面板100還可包含軟性電路板150、電路板 160以及殼體170。軟性電路板150貼合第一基板120,用以將第一基板120以及第二基板140上的電路連接至電路板160。殼體170用以裝載上述顯示面板100的各種元件。於此,藉由設置第一基板120(例如主動元件陣列基板)鄰近使用者(例如:第一基板120提供顯示面I(例如:第1A圖之空白箭頭處),能夠減少額外設置框體(未標示)遮蔽軟性電路板150等電路配置,進而達到窄邊框的效果。
第1B圖為本發明之一實施例之顯示面板100的局部上視圖。第1C圖為沿第1B圖中剖線1B-1B所繪示之剖面示意圖。第1D圖為沿第1B圖中剖線1C-1C所繪示之剖面示意圖。同時參照第1A圖至第1D圖。
顯示面板100可包括資料線DL、閘極線GL、閘極介電層GI、主動元件AD以及畫素電極PE,設置於第一基板120的內表面124上。於部份實施例中,顯示面板100可選擇性更包含共通線CL或其它合適的線路。資料線DL與閘極線GL交錯,以定義複數個畫素區域PA,但不限於此。於部份實施例中,一個畫素區域PA包括至少一個主動元件AD以及至少一個畫素電極PE,且畫素電極PE電性連接主動元件AD。於部份實施例中,一個畫素區域PA可包含至少一條資料線DL與至少一條閘極線GL或其它合適的線路。
主動元件AD包括半導體層SL、閘極GE、源極SE、汲極DE。源極SE、汲極DE分別電性連接半導體層SL的兩端,閘極GE用以控制半導體層SL的兩端導通與否。閘極GE與半導體層SL由閘極介電層GI隔開。於部分實施方式中,閘 極GE電性連接閘極線GL,源極SE電性連接資料線DL,汲極DE電性連接畫素電極PE。藉此,主動元件AD可經由閘極線GL的控制導通資料線DL與畫素電極PE。於本實施方式中,主動元件AD較佳為底部閘極型薄膜電晶體(Bottom Gate-TFT),例如:閘極GE位於半導體層SL與第一基板120的內表面124之間。在其他實施例中,主動元件AD也可以是頂部閘極型薄膜電晶體(Top Gate-TFT),例如:半導體層SL位於閘極GE與第一基板120的內表面124之間。
此外,畫素電極PE和主動元件AD之間亦設有保護層180。於此,閘極介電層GI與保護層180採用絕緣材料,包含無機材料(例如:氧化矽、氮化矽、氮氧化矽或其它合適的材料)、有機材料(例如:無色或有色光阻、聚亞醯胺、苯並環丁烯或其它合適的材料)或其它合適的材料。
於此,由於以第一基板120(例如主動元件陣列基板)鄰近使用者(例如:主動元件陣列基板提供顯示面I(例如:圖1A之空白箭頭處)),因此第一基板120上的各個金屬及/或合金層之材料容易反射光線,而影響視覺效果。於本發明的多個實施方式中,可以藉由低反射層(例如:金屬或合金層)的設置降低反射率。於一較佳實施例中,第一基板120可不需額外設置黑色矩陣(Black Matrix),藉此增加顯示面板100的開口率,然本發明並不以此為限,本領域技術人員可示實際需求做選擇。
詳細而言,參照第1C圖與第1D圖,於本發明之部分實施方式中,第一基板120的內表面124上的閘極線GL、 可選擇性設置的共通線CL、主動元件AD的閘極GE、或其它合適的線路、或前述線路中的任一者,可以由一圖案化金屬層320’所形成。此圖案化金屬層320’與第一基板120的內表面124之間還設有圖案化鉬鉭氧化物層310’。舉例而言,圖案化鉬鉭氧化物層310’設置於第一基板120之內表面124與圖案化金屬層320’之間,圖案化鉬鉭氧化物層310’與圖案化金屬層320’合稱為金屬結構300。其中,圖案化金屬層320’可為單層或多層結構,且其材料可包含金屬、合金、或其鹽類、或其它具有反射率之材料。圖案化鉬鉭氧化物層310’也可為單層或多層結構。
於本發明之部分實施方式中,第一基板120的內表面124上的資料線DL、主動元件AD的源極SE、汲極DE、或其它合適的線路、或前述線路中的任一者,可以由一圖案化金屬層420’所形成。若以底部閘極型薄膜電晶體(Bottom Gate-TFT)為範例,此圖案化金屬層420’與閘極介電層GI之間還設有圖案化鉬鉭氧化物層410’。舉例而言,圖案化鉬鉭氧化物層410’設置於閘極介電層GI上,圖案化金屬層420’設置於該圖案化鉬鉭氧化物層410’上。若以頂部閘極型薄膜電晶體(Top Gate-TFT)為範例,此圖案化金屬層420’與第一基板120之內表面124之間還設有圖案化鉬鉭氧化物層410’。舉例而言,圖案化金屬層420’設置於該圖案化鉬鉭氧化物層410’上。圖案化鉬鉭氧化物層410’與圖案化金屬層420’合稱為金屬結構400。其中,圖案化金屬層420’可為單層或多層結構,且其材料可包含金屬、合金、或其鹽類、或其它具有反射率之 材料。圖案化鉬鉭氧化物層410’也可為單層或多層結構。
藉此,圖案化鉬鉭氧化物層310’、410’可以防止從第一基板120的外表面122進入顯示面板100之光線被圖案化金屬層320’、420’反射,而影響觀察者的視覺效果。
於此,圖案化鉬鉭氧化物層310’、410’的厚度可介於約50埃(Å)~約600埃(Å)之間,圖案化金屬層320’、420’的厚度可介於約50埃(Å)~約10000埃(Å)之間,但不限於此。
於本發明之部分實施方式中,圖案化鉬鉭氧化物層310、410中鉭的原子百分比(atomic percent)含量係介於約2%至約12%之間,鉬的原子百分比含量與氧的原子百分比含量皆大於鉭的原子百分比含量。此含量設置能夠降低或消除圖案化鉬鉭氧化物層在圖案化過程中的過蝕(over etching)問題。於部分實施方式中,圖案化鉬鉭氧化物層310’、410’中氧的原子百分比含量可係介於約5%至約60%之間。若鉬鉭氧化物中不存在其它元素或雜質,則鉬原子百分比+鉭原子百分比+氧原子百分比之總和約等於100%,無單位;若鉬鉭氧化物中存在其它元素或雜質,則除了前述之原子百分比總和之外,要再加上其它元素或雜質之總和約等於100%,無單位。
於本實施例中,可選擇性更包含共通電極CE係設置於第二基板140上,但本發明不以此為限,共通電極CE可選擇設置於第一基板120或第二基板140之其中一者上。雖然在此以上下電極的配置為例,但本發明不以此為限。於部分實施方式中,前述金屬結構300、400可以配置於橫向電場效應液晶顯示面板(In-Plane-Switching,IPS)面板中。或者,於 其他實施方式中,前述金屬結構300、400可以配置於多區域垂直配向型(Multi-domain Vertical Alignment,MVA)液晶顯示面板中。
第2A圖至第2E圖為根據本發明之部分實施方式之金屬結構300於其製作方法的多個階段之剖面示意圖。以下詳細介紹金屬結構300的製造方法。
參照第2A圖。提供第一基板120,並於第一基板120之內表面124上形成鉬鉭氧化物層310,鉬鉭氧化物層310的厚度可介於約50埃(Å)~約600埃(Å)之間,其中鉬鉭氧化物層310包括鉬鉭氧化物。於本發明之部分實施方式中,於第一基板120上形成鉬鉭氧化物層310之步驟包括進行非反應性濺鍍(non-reactive sputtering)製程或反應性濺鍍(reactive sputtering)製程。於一實施例中,以非反應性濺鍍製程為例,可以採用物理氣相沉積法(physical vapor deposition;PVD)。於本實施例中,在不通入反應性氣體(例如:氧氣、氮氣、或其它合適的氣體、或前述氣體之混合)進行物理氣相沉積,可增加鉬鉭氧化物層310成膜之均勻性。
參照第2B圖。於鉬鉭氧化物層310上形成一金屬層320。金屬層320的厚度可介於約50埃(Å)~約10000埃(Å)之間。金屬層320的材料可以是鋁、銅、銀、鈦、鉬、鉭、鈮、鎂、鋅或釹之其中至少一者、上述材料之金屬複合層、上述材料之合金、上述材料之鹽類、或其他適合之金屬導電材料。於本實施例中,金屬層320係為單層金屬層,但本發明不以此為限,金屬層320亦可為金屬材料的疊合結構,或其它材料與金 屬材料的疊合結構。
參照第2C圖至第2E圖。對鉬鉭氧化物層310與金屬層320進行一圖案化製程,以形成一圖案化鉬鉭氧化物層310’以及一圖案化金屬層320’,合稱金屬結構300。
詳細而言,首先,參照第2C圖,於金屬層320上形成圖案化光阻330。圖案化光阻330可以經由塗佈一光阻層、局部曝光該光阻層以及移除經曝光/未經曝光的光阻層而形成。圖案化光阻330可為正型光阻或負型光阻,本發明並不以此為限。
接著,參照第2D圖,以圖案化光阻330為遮罩,對金屬層320以及鉬鉭氧化物層310進行蝕刻,而形成圖案化金屬層320’以及圖案化鉬鉭氧化物層310’,合稱金屬結構300。如前所述,圖案化金屬層320’可包含閘極線GL、可選擇性設置的共通線CL、主動元件AD的閘極GE(參考第1B圖至第1D圖)或與其它合適的線路中的任一者。於部分實施方式中,此蝕刻以採用酸性蝕刻液進行,例如雙氧水、硫酸或其組合,但不限於此,可依金屬結構300之成份加以選擇合適的蝕刻液成份。
再來,參照第2E圖,去除圖案化光阻330,以利於其他層體設置於圖案化金屬層320’上。於部分實施方式中,此去除圖案化光阻330,較佳採用鹼性去光阻液進行。經歷酸性蝕刻液與鹼性去光阻液,金屬結構300鄰近第一基板120的一側(例如金屬結構300的圖案化鉬鉭氧化物層310’)可能會有側蝕(undercut)的問題。此側蝕問題可經由調整圖案化鉬鉭氧 化物層310’中的鉭原子百分比含量而獲得改善,可參照第3A圖至第3D圖與第4A圖至第4D圖。於部分實施方式中,理想上,金屬結構300之側表面300A與底表面300B之間具有夾角Q,該夾角Q介於約10度至約80度之間。
雖然在此僅提到金屬結構300(參照第1B圖、第2E圖)的製作方法,但應了解到,金屬結構400(參照第1B圖)亦可採用相同的製作方法(參照第3A圖至第3D圖)形成。圖案化金屬層420’(參照第1B圖)可為資料線DL以及主動元件AD的源極SE或汲極DE或與其它合適的線路中的任一者。圖案化金屬層420’的材料可以與圖案化金屬層320’實質上相同或不同。舉例而言,圖案化金屬層420’(參照第1B圖)的材料可以是鋁、銅、銀、鈦、鉬、鉭、鈮、鎂、鋅或釹之其中至少一者、上述材料之金屬複合層、上述材料之合金、上述材料之鹽類、或其他適合之金屬導電材料。圖案化鉬鉭氧化物層310’、410’的可以採用原子百分比實質上相同或不同的材料。金屬結構400(參照第1B圖)的其他細節大致如同金屬結構300的製作方法,在此不再贅述。
第3A圖至第3D圖為根據本發明之部分實施方式之各種原子比例的金屬結構300(參照第2D圖)在蝕刻後尚未去光阻前的掃描式電子顯微鏡(Scanning Electron Microscope;SEM)圖。第3A圖至第3D圖中金屬結構300(參照第2D圖)的圖案化鉬鉭氧化物層310’之鉭(tantalum;Ta)原子比例分別為約0%、約2%、約4%以及約6%。由圖可知,在鉭原子比例約為0%時,金屬結構300具有明顯的側蝕 (undercut)。如第3A圖所示,在標記UC處,金屬結構300的邊緣處有一凹槽,而與第一基板120並未相連,即為側蝕現象。隨著鉭原子比例的提升,側蝕的程度逐漸降低。如第3B圖至第3D圖所示,金屬結構300的邊緣處的凹槽,隨著鉭原子比例的升高逐漸縮小。
雖然第3A圖至第3D圖中金屬結構300(參照第2D圖)僅經歷過酸性蝕刻液,尚未鹼性去光阻液,但已可看出,側蝕的程度與鉭的關係。
第4A圖至第4D圖為根據本發明之部分實施方式之各種原子比例的金屬結構300(參照第2E圖)在去光阻後的穿透式電子顯微鏡(Transmission Electron Microscope;TEM)圖。第4A圖至第4D圖中金屬結構300(參照第2E圖)的圖案化鉬鉭氧化物層之鉭(tantalum;Ta)原子比例分別為約6%、約8%、約10%以及約12%。由圖可知,而隨著鉭原子比例的提升,側蝕(undercut)的程度逐漸降低。然而,隨著鉭原子比例的提升,所需的蝕刻時間也逐間增長。本實施例中,圖案化金屬層320’材料以銅為例,第3A圖至第3D圖中的金屬結構300(參照第2E圖)蝕刻分別經歷約108秒、約120秒、約135秒、約148秒的蝕刻時間,才能達到圖案化金屬結構300的效果,然此蝕刻時間可隨測試條件不同,此僅為說明材料組成的不同所造成蝕刻時間相對的關係。
據此,本發明之部分實施方式中,設計鉬鉭氧化物中鉭的原子百分比含量約介於2%至12%之間,以降低側蝕(undercut)的程度並提升製程效率。在此設計下,鉬的原子百 分比含量與氧的原子百分比含量皆大於鉭的原子百分比含量。於本發明之部分實施方式中,鉬鉭氧化物中氧的原子百分比含量係約介於5%至60%之間。其中,鉬鉭氧化物中鉭、鉬、氧的原子百分比可以透過能量散布分析儀(Energy Dispersive Spectroscopy;EDS),分析圖案化鉬鉭氧化物層310’(參照第2D圖、第2E圖)中的元素含量而獲知。
第5圖為根據本發明之部分實施方式之金屬結構300的反射頻譜圖。編號1至4分別代表圖案化鉬鉭氧化物層310’(參照第2E圖)之鉭(tantalum;Ta)原子比例分別為約6%、約8%、約10%以及約12%的金屬結構300(參照第2E圖)的反射率。如圖所示,金屬結構300(即圖案化金屬層320’以及圖案化鉬鉭氧化物層310’)於可見光範圍內的反射率約介於2%至20%之間,能達到降低環境光反射,而避免觀察者的視覺效果受到影響。
於本發明之多個實施方式中,藉由設置主動元件陣列基板鄰近使用者(亦即主動元件陣列基板提供顯示面),能夠避免電路配置佔據顯示的邊框,進而達到窄邊框的效果。再者,在主動元件陣列基板中,設計低反射層位於金屬層與基板之間,能夠降低環境光的反射,以達到更好的視覺效果。據此,本發明的實施方式中的顯示面板,能達到窄邊框或全平面無邊框(four side bezel-less)、有效防止光線反射、且不降低顯示亮度的效果。雖然本發明已以多種實施方式揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範 圍當視後附之申請專利範圍所界定者為準。

Claims (18)

  1. 一種金屬結構,包括:一圖案化鉬鉭氧化物層,設置於一第一基板上,其中該圖案化鉬鉭氧化物層中鉭的原子百分比含量係介於2%至12%之間,鉬的原子百分比含量與氧的原子百分比含量皆大於鉭的原子百分比含量;以及一圖案化金屬層,設置於該圖案化鉬鉭氧化物層上。
  2. 如請求項1所述之金屬結構,其中該圖案化鉬鉭氧化物層中氧的原子百分比含量係介於5%至60%之間。
  3. 如請求項1所述之金屬結構,其中該圖案化鉬鉭氧化物層的厚度係介於50埃(Å)~600埃(Å)之間。
  4. 如請求項1所述之金屬結構,其中該圖案化金屬層的厚度係介於50埃(Å)~10000埃(Å)之間。
  5. 如請求項1所述之金屬結構,其中該金屬結構於可見光範圍內的反射率介於2%至20%之間。
  6. 如請求項1所述之金屬結構,其中該金屬結構之側表面與底表面之間具有一夾角,且該夾角介於10度至80度之間。
  7. 一種顯示面板,包含:一第一基板,具有一外表面、一內表面、以及一連接該第一基板之該外表面與該內表面之第一側邊,且該外表面作為該顯示面板之顯示面;一第二基板,具有一外表面、一內表面、以及一連接該第一基板之該外表面與該內表面之第二側邊,且該第二基板之該內表面對於該第一基板之該內表面,其中,該第一側邊與該第二側邊位於該顯示面板之同一側,且該第一側邊實質上對齊或超出該第二側邊;一顯示介質層,設置於該第一基板與該第二基板之間;一圖案化鉬鉭氧化物層,設置於該第一基板之內表面,其中該圖案化鉬鉭氧化物層中鉭的原子百分比含量係介於2%至12%之間,且鉬的原子百分比含量與氧的原子百分比含量皆大於鉭的原子百分比含量;以及一圖案化金屬層,設置於該圖案化鉬鉭氧化物層與該第二基板之內表面之間。
  8. 如請求項7所述之顯示面板,更包含:一背光元件,用以向該第二基板提供一光線,其中該第二基板位於該第一基板與該背光元件之間,且該光線依序經過該第二基板、該顯示介質層與該第一基板。
  9. 如請求項7所述之顯示面板,其中該圖案化金屬層包括一閘極線、一閘極、一共通線、一資料線、一源極或一汲極之其中至少一者。
  10. 如請求項7所述之顯示面板,該圖案化鉬鉭氧化物層中氧的原子百分比含量係介於5%至60%之間。
  11. 如請求項7所述之顯示面板,其中該圖案化鉬鉭氧化物層的厚度係介於50埃(Å)~600埃(Å)之間。
  12. 一種製作金屬結構的方法,包含:提供一第一基板;於該第一基板之內表面上形成一鉬鉭氧化物層,其中該鉬鉭氧化物層包括一鉬鉭氧化物,其中該鉬鉭氧化物中鉭的原子百分比含量係介於2%至12%之間,且鉬的原子百分比含量與氧的原子百分比含量皆大於鉭的原子百分比含量;於該鉬鉭氧化物層上形成一金屬層;以及對該鉬鉭氧化物層與該金屬層進行一圖案化製程,以形成一圖案化鉬鉭氧化物層以及一圖案化金屬層。
  13. 如請求項12所述之製作金屬結構的方法,其中對該鉬鉭氧化物層與該金屬層進行一圖案化製程之步驟包含:於該金屬層上形成一圖案化光阻層:以及採用一酸性蝕刻液,以該圖案化光阻層為遮罩對該鉬鉭氧化物層與該金屬層進行蝕刻。
  14. 如請求項12所述之製作金屬結構的方法,其中對該鉬鉭氧化物層與該金屬層進行一圖案化製程之步驟包含:採用一鹼性去光阻液,去除該圖案化光阻層。
  15. 如請求項12所述之製作金屬結構的方法,其中該鉬鉭氧化物中氧的原子百分比含量係介於5%至60%之間。
  16. 如請求項12所述之製作金屬結構的方法,其中於該第一基板上形成該鉬鉭氧化物層之步驟包括進行一非反應性濺鍍(non-reactive sputtering)製程。
  17. 如請求項12所述之製作金屬結構的方法,其中該圖案化鉬鉭氧化物層的厚度係介於50埃(Å)~600埃(Å)之間。
  18. 如請求項12所述之製作金屬結構的方法,其中該圖案化鉬鉭氧化物層於可見光範圍內的反射率介於2%至20%之間。
TW107103680A 2017-12-19 2018-02-01 金屬結構及其製作方法與應用之顯示面板 TWI669559B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201711373560.1A CN108121098B (zh) 2017-12-19 2017-12-19 金属结构及其制作方法与应用的显示面板
??201711373560.1 2017-12-19

Publications (2)

Publication Number Publication Date
TW201928480A TW201928480A (zh) 2019-07-16
TWI669559B true TWI669559B (zh) 2019-08-21

Family

ID=62229328

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107103680A TWI669559B (zh) 2017-12-19 2018-02-01 金屬結構及其製作方法與應用之顯示面板

Country Status (6)

Country Link
US (2) US10852605B2 (zh)
EP (1) EP3731000A4 (zh)
JP (1) JP2021505971A (zh)
CN (1) CN108121098B (zh)
TW (1) TWI669559B (zh)
WO (1) WO2019119490A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI678579B (zh) 2017-12-19 2019-12-01 友達光電股份有限公司 顯示面板以及顯示裝置
KR102526507B1 (ko) * 2018-07-17 2023-04-26 티씨엘 차이나 스타 옵토일렉트로닉스 테크놀로지 컴퍼니 리미티드 배선 기판 및 이를 포함하는 표시 장치
US11251206B2 (en) * 2019-08-20 2022-02-15 Beijing Boe Display Technology Co., Ltd. Display substrate and method for preparing the same, and display device
CN112259557B (zh) * 2020-10-15 2022-12-06 Tcl华星光电技术有限公司 显示面板及其制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104765191A (zh) * 2015-04-30 2015-07-08 京东方科技集团股份有限公司 阵列基板及其制作方法和显示装置
CN105093654A (zh) * 2015-08-27 2015-11-25 京东方科技集团股份有限公司 阵列基板及其制作方法和显示装置
US20170168616A1 (en) * 2015-06-19 2017-06-15 Boe Technology Group Co., Ltd. Substrate, touch display panel having the same, and method thereof
US20170184931A1 (en) * 2015-06-19 2017-06-29 Boe Technology Group Co., Ltd. Array substrate, manufacturing method thereof and display device
TWI591820B (zh) * 2016-03-30 2017-07-11 友達光電股份有限公司 低反射金屬結構、顯示面板及其製作方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100727259B1 (ko) * 2005-12-29 2007-06-11 동부일렉트로닉스 주식회사 반도체 장치의 배선 형성방법
EP3266892B1 (en) 2007-04-27 2018-10-24 H. C. Starck Inc Tantalum based alloy that is resistant to aqueous corrosion
KR101730347B1 (ko) * 2009-09-16 2017-04-27 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 그 제작 방법
KR101597312B1 (ko) * 2009-11-16 2016-02-25 삼성디스플레이 주식회사 박막 트랜지스터 표시판 및 그 제조 방법
AT13879U1 (de) 2013-10-04 2014-10-15 Plansee Se Berührungssensoranordnung
KR20150142139A (ko) * 2014-06-10 2015-12-22 삼성디스플레이 주식회사 박막트랜지스터 어레이 기판 및 그 제조방법
CN104730603B (zh) 2015-04-01 2017-10-17 京东方科技集团股份有限公司 一种防反射层叠结构及其制作方法、基板和显示装置
KR20160128518A (ko) * 2015-04-28 2016-11-08 삼성디스플레이 주식회사 표시장치 및 그 제조방법
CN105204692B (zh) * 2015-10-28 2018-01-26 京东方科技集团股份有限公司 一种触摸屏、显示装置及显示装置的显示驱动方法
JP6138400B1 (ja) * 2016-02-01 2017-05-31 株式会社ワコム 電子ペン
CN106646975A (zh) * 2017-01-03 2017-05-10 京东方科技集团股份有限公司 一种显示面板、显示装置及显示面板的制作方法
KR20190001629A (ko) * 2017-06-26 2019-01-07 삼성디스플레이 주식회사 발광소자 및 표시패널의 제조방법
KR102543167B1 (ko) * 2017-09-15 2023-06-13 삼성디스플레이 주식회사 배선 기판, 이를 포함하는 표시 장치 및 배선 기판의 제조 방법
KR102390321B1 (ko) * 2017-09-27 2022-04-26 삼성디스플레이 주식회사 표시 장치 및 이의 제조 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104765191A (zh) * 2015-04-30 2015-07-08 京东方科技集团股份有限公司 阵列基板及其制作方法和显示装置
US20170168616A1 (en) * 2015-06-19 2017-06-15 Boe Technology Group Co., Ltd. Substrate, touch display panel having the same, and method thereof
US20170184931A1 (en) * 2015-06-19 2017-06-29 Boe Technology Group Co., Ltd. Array substrate, manufacturing method thereof and display device
CN105093654A (zh) * 2015-08-27 2015-11-25 京东方科技集团股份有限公司 阵列基板及其制作方法和显示装置
TWI591820B (zh) * 2016-03-30 2017-07-11 友達光電股份有限公司 低反射金屬結構、顯示面板及其製作方法

Also Published As

Publication number Publication date
EP3731000A1 (en) 2020-10-28
WO2019119490A1 (zh) 2019-06-27
TW201928480A (zh) 2019-07-16
US11556036B2 (en) 2023-01-17
EP3731000A4 (en) 2021-09-15
CN108121098A (zh) 2018-06-05
US10852605B2 (en) 2020-12-01
JP2021505971A (ja) 2021-02-18
US20190187529A1 (en) 2019-06-20
CN108121098B (zh) 2019-08-06
US20210041751A1 (en) 2021-02-11

Similar Documents

Publication Publication Date Title
TWI669559B (zh) 金屬結構及其製作方法與應用之顯示面板
US7696088B2 (en) Manufacturing methods of metal wire, electrode and TFT array substrate
KR101502676B1 (ko) 어레이 기판, 그 제조방법 및 디스플레이 장치
KR100698950B1 (ko) 박막 트랜지스터 어레이 기판의 제조방법
KR101486180B1 (ko) 액티브 매트릭스 기판의 제조 방법, 표시 패널 및 표시 장치
US20150303150A1 (en) Array Substrate, Method of Manufacturing The Same and Display Device
JP2004163901A (ja) 液晶表示装置用アレイ基板及びその製造方法
US20180190679A1 (en) Thin film transistor substrate and method for manufacturing same
US10386684B2 (en) Semiconductor device, display apparatus, and method of manufacturing semiconductor device
JP4677654B2 (ja) 透過型液晶表示装置及びその製造方法
US20060261335A1 (en) Liquid crystal display device
KR100832511B1 (ko) 박막 트랜지스터 어레이 기판 및 그 제조방법과, 반투과형액정 표시장치
JPH0715017A (ja) 平板表示装置およびその製造方法
JP2006041161A (ja) 薄膜トランジスタアレイ基板及びその製造方法
JP2010165732A (ja) エッチング液及びこれを用いたパターン形成方法並びに液晶表示装置の製造方法
JP2006332209A (ja) 薄膜トランジスタ基板及びその製造方法
CN104375348A (zh) 阵列基板及其制造方法和全反射式液晶显示器
WO2021012435A1 (zh) 薄膜晶体管基板及其制作方法
WO2016021320A1 (ja) アクティブマトリクス基板およびその製造方法
KR100596044B1 (ko) 반사형 액정표시장치 및 반투과형 액정표시장치와, 이들의제조방법
KR20210093403A (ko) 표시 패널의 제조 방법 및 그에 따라 제조되는 표시 패널
JP5342731B2 (ja) 液晶表示装置とその製造方法
JP2008217017A (ja) 反射型液晶表示装置および半透過型液晶表示装置
WO2011148728A1 (ja) 表示装置およびその製造方法
KR101035927B1 (ko) Ips 모드 액정표시소자의 제조방법