TWI635584B - 半導體封裝與其製造方法 - Google Patents

半導體封裝與其製造方法 Download PDF

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TWI635584B
TWI635584B TW105135369A TW105135369A TWI635584B TW I635584 B TWI635584 B TW I635584B TW 105135369 A TW105135369 A TW 105135369A TW 105135369 A TW105135369 A TW 105135369A TW I635584 B TWI635584 B TW I635584B
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interposer
semiconductor wafer
semiconductor
redistribution layer
semiconductor package
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TW201814845A (zh
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Pochun Lin
林柏均
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Nanya Technology Corporation
南亞科技股份有限公司
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Abstract

一種半導體封裝包含半導體晶片、中介層、第一重分佈層與模料。半導體晶片具有相對的第一表面與第二表面以及至少一側壁。側壁連接第一表面與第二表面。中介層置於半導體晶片的第一表面上。第一重分佈層置於半導體晶片的第二表面上，且電性連接半導體晶片。模料置於中介層與第一重分佈層之間，且連接半導體晶片的側壁。

Description

半導體封裝與其製造方法
本發明是有關於一種半導體封裝。
半導體裝置係製作於半導體基板或晶圓的表面上，其可被依序分開或晶粒化成複數個晶片或晶粒，每一晶片或晶粒包含形成於其上的裝置或積體電路(Integrated Circuit,IC)。一或多個晶片可接著被封裝體包圍，其在電性連接晶片與外接電路時，提供晶片物理性與化學性保護。晶片可使用模料以塑模。然而，在提供熱至半導體基板的製程(如回焊製程)時，半導體基板可能會翹曲。
本揭露的一態樣提供一種半導體封裝，包含半導體晶片、中介層、第一重分佈層與模料。半導體晶片具有相對的第一表面與第二表面以及至少一側壁。側壁連接第一表面與第二表面。中介層置於半導體晶片的第一表面上。第一重分佈層置於半導體晶片的第二表面上，且電性連接半導體晶片。模 料置於中介層與第一重分佈層之間，且連接半導體晶片的側壁。
在一或多個實施方式中，半導體封裝更包含貫穿結構，置於中介層與模料中，且電性連接第一重分佈層。
在一或多個實施方式中，半導體封裝更包含半導體裝置，電性連接貫穿結構。半導體晶片置於半導體裝置與第一重分佈層之間。
在一或多個實施方式中，中介層的厚度為約10微米至約1000微米。
在一或多個實施方式中，中介層包含矽、二氧化矽、絕緣層上矽或其組合。
在一或多個實施方式中，中介層的楊式模數高於該模料的楊式模數。
在一或多個實施方式中，中介層的熱膨脹係數小於模料的熱膨脹係數。
在一或多個實施方式中，半導體封裝更包含黏合層，置於半導體晶片與中介層之間。
在一或多個實施方式中，半導體封裝更包含第二重分佈層，而中介層置於第一重分佈層與第二重分佈層之間。
本揭露的另一態樣提供一種半導體封裝的製造方法，包含放置半導體晶片於載板上。放置中介層於半導體晶片上。形成模料於載板與中介層之間，並環繞半導體晶片。移除載板。形成第一重分佈層於半導體晶片上。半導體晶片置於中介層與第一重分佈層之間。
在一或多個實施方式中，中介層包含矽、二氧化矽、絕緣層上矽或其組合。
在一或多個實施方式中，中介層的楊式模數高於該模料的楊式模數。
在一或多個實施方式中，中介層的熱膨脹係數小於該模料的熱膨脹係數。
在一或多個實施方式中，放置中介層於半導體晶片上的步驟包含形成一融合鍵(Fusion bond)於中介層與半導體晶片之間。
在一或多個實施方式中，放置中介層於半導體晶片上的步驟包含形成黏合層於半導體晶片上。放置中介層於黏合層上。
在一或多個實施方式中，上述的方法更包含形成貫穿結構於模料與中介層中。
在一或多個實施方式中，形成貫穿結構包含形成貫穿孔於模料與中介層中。形成貫穿結構於貫穿孔中。
在一或多個實施方式中，上述的方法更包含連接半導體裝置至貫穿結構。半導體晶片置於半導體裝置與第一重分佈層之間。
在一或多個實施方式中，上述的方法更包含形成第二重分佈層於中介層上。中介層置於第二重分佈層與第一重分佈層之間。
在一或多個實施方式中，上述的方法更包含形成凸塊於第一重分佈層上。
在上述實施方式中，因半導體封裝包含中介層，因此可防止或抑制半導體封裝於製程中，因半導體晶片與模料之間的熱膨脹係數錯配而產生的翹曲問題。
110‧‧‧載板
120、270‧‧‧黏合層
202‧‧‧貫穿孔
204‧‧‧貫穿結構
210‧‧‧半導體晶片
220‧‧‧中介層
240‧‧‧模料
250‧‧‧第一重分佈層
260‧‧‧凸塊
280‧‧‧第二重分佈層
211a‧‧‧第一表面
211b‧‧‧第二表面
211c‧‧‧側壁
212、292‧‧‧基板
214、294‧‧‧電路層
290‧‧‧半導體裝置
295‧‧‧連接元件
J‧‧‧接合處
T1、T2‧‧‧厚度
第1A圖至第1F圖為本揭露一些實施方式的半導體封裝的製造方法於不同階段的剖面圖。
第2圖為根據本揭露一些實施方式的半導體封裝的剖面圖。
第3圖為根據本揭露一些實施方式的半導體封裝的剖面圖。
第4圖為根據本揭露一些實施方式的半導體封裝的剖面圖。
以下將以圖式揭露本發明的複數個實施方式，為明確說明起見，許多實務上的細節將在以下敘述中一併說明。然而，應瞭解到，這些實務上的細節不應用以限制本發明。也就是說，在本發明部分實施方式中，這些實務上的細節是非必要的。此外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。
第1A圖至第1F圖為本揭露一些實施方式的半導體封裝的製造方法於不同階段的剖面圖。請參照第1A圖。提 供一載板110。在一些實施方式中，載板110的材質可為矽、複合半導體、玻璃、陶瓷或其他合適的材料。載板110可提供後續製程所需的硬度。
形成一黏合層120於載板110上。黏合層120可為焊接膜(bonding film)或膠水(glue)。接著，至少一半導體晶片固定於載板110上。舉例而言，在第1A圖中，二個半導體晶片210接觸至黏合層120以固定於載板110上。此二半導體晶片210可為相同或不同的晶片。舉例而言，半導體晶片210其中一者為快取記憶體(cache memory)，而半導體晶片210另一者為中央處理單元(central processing unit,CPU)晶片或圖形處理單元(graphic processing unit,GPU)晶片。在一些其他的實施方式中，半導體晶片210的數量可大於兩個。在一些實施方式中，半導體晶片210被機械研磨，以降低半導體晶片210的厚度。
至少一半導體晶片210具有第一表面211a、第二表面211b與至少一側壁211c。第二表面211b相對第一表面211a，而側壁211c連接第一表面211a與第二表面211b。半導體晶片210的第二表面211b接觸黏合層120。至少一半導體晶片210包含基板212與形成於基板212上的電路層214。在第1圖中，基板212具有第一表面211a，而電路層214具有第二表面211b。
基板212的材質可為半導體材料，包含，但不限於，塊矽、半導體晶圓、絕緣層上矽基板或矽化鍺基板。其他半導體材料包含第三族、第四族與第五族的元素可被利用。電 路層214可包含複數個微電子元件。微電子元件例如包含電晶體(例如金屬氧化半導體場效電晶體(metal oxide semiconductor field effect transistors,MOSFET)、互補金屬氧化半導體(complementary metal oxide semiconductor,CMOS)電晶體、雙極性電晶體(bipolar junction transistors,BJT)、高壓電晶體、高頻電晶體、P型通道與/或N型通道場效電晶體(PFET/NFET)等等)、電阻、二極體、電容、電感、保險絲與/或其他合適的元件。可執行不同的製程以形成不同的微電子元件，例如沉積、蝕刻、佈植、光微影、退火與/或其他合適的製程。微電子元件可互相連接以形成積體電路，例如邏輯裝置、記憶體裝置(例如靜態隨機存儲器(SRAM))、無線電頻率(RF)裝置、輸入/輸出(input/output,I/O)裝置、晶片上系統(system-on-chip,SoC)裝置、其組合與/或其他合適種類的裝置。
請參照第1B圖。一中介層220置於半導體晶片210的第一表面211a，使得半導體晶片210置於中介層220與載板110之間。中介層220可被融接(fusion bond)於半導體晶片210的第一表面211a，而中介層220與半導體晶片210之間形成接合處J。亦即，中介層220為直接接觸半導體晶片210。在一些實施方式中，中介層220包含矽(Silicon)、二氧化矽(SiO2)、絕緣層上矽(Silicon on insulator,SOI)或其組合。中介層220的厚度T1可大於、小於或實質等於半導體晶片210的厚度T2。在一些實施方式中，中介層220的厚度T1範圍為約10微米至約1000微米。在一些其他實施方式中，中介層220 的厚度T1範圍為約25微米至約1000微米。在又一些其他實施方式中，中介層220的厚度T1範圍為約50微米至約1000微米。中介層220的硬度隨著中介層220的厚度T1而增加。在一些實施方式中，中介層220與半導體晶片210的總厚度(即T1+T2)為約1000微米，而本揭露不以此為限。
在一些實施方式中，中介層220的熱膨脹係數(coefficient of thermal expansion,CTE)小於模料240的熱膨脹係數。舉例而言，中介層220與半導體晶片210的基板212的熱膨脹係數差值小於約500ppm/K。亦即，半導體晶片210的基板212與中介層220具有相似或相同的熱膨脹係數。如此的結構可改善或抑制半導體封裝因熱膨脹係數錯配(mismatch)所產生的翹曲(warpage)。
在一些實施方式中，可形成一種子層(未繪示)於中介層220上。種子層可在中介層220固定於半導體晶片210之前或之後形成。種子層的材質可為金屬，例如為銅、銅合金、鋁、銀或其他合適的材料。種子層可提供中介層220與形成於其上的結構(例如重分佈層)之間良好的黏合力。在一些實施方式中，種子層可被省略。
請參照第1C圖。形成一模料240於載板110與中介層220之間並且環繞半導體晶片210。換言之，模料240連接(或接觸)半導體晶片210的側壁211c。在一些實施方式中，模料240充滿中介層220與載板110之間的空間且置於半導體晶片210之間。模料240可被注射入空間中以封裝半導體晶片210。在一些實施方式中，模料240的材質可為樹脂或其他合適的材料。中介層220的楊式模數(Young’s Modulus)(或彈性模數(elastic modulus)或拉力模數(tensile modulus))高於模料240的楊式模數。亦即，中介層220比模料240較難以變形，因此半導體封裝的翹曲可被改善或抑制。
請參照第1D圖。翻轉第1C圖的結構，且移除第1C圖的載板110與黏合層120。在一些實施方式中，載板110與黏合層120使用機械蝕刻、機械式剝離、化學機械研磨(Chemical Mechanical Polishing,CMP)、機械研磨(Mechanical Grinding)、熱烘、雷射掃描或濕式剝離(Wet stripping)法以去除。之後，形成至少一貫穿孔202於中介層220以及模料240中。舉例而言，在第1D圖中有四個貫穿孔202，然而本揭露不以此為限。貫穿孔202環繞半導體晶片210而形成。亦即，貫穿孔202與半導體晶片210彼此分離。在一些實施方式中，貫穿孔202的形成方式為雷射鑽孔(laser drilling)、機械鑽孔(mechanical drilling)、深反應性離子蝕刻(deep reactive ion etching)或其他合適的製程。之後，複數個貫穿結構204分別形成於貫穿孔202中。貫穿結構204的材質可為鋁、銅、錫、鎳、金、銀、鈦、鎢、多晶矽或其他合適的電性導電材料，且可應用電解電鍍(electrolytic plating)法、無電鍍(化學鍍)(electroless plating)法、或其他合適的金屬沉積製程以形成。在一些實施方式中，貫穿結構204可省略。
請參照第1E圖。形成第一重分佈層250於半導體晶片210的第二表面211b與模料240上，使得第一重分佈層 250電性連接至少一半導體晶片210的電路層214與/或貫穿結構204。在一些實施方式中，如果省略貫穿結構204，第一重分佈層250則電性連接至至少一半導體晶片210。第一重分佈層250可包含耦接至貫穿結構204與/或半導體晶片210的電路層214的一或多個走線(traces)以定出其間的電路連接。
在一些實施方式中，第一重分佈層250以沉積導電材料於半導體晶片210的第二表面211b與模料240上並圖案化導電材料以形成耦合至半導體晶片210的電路層214與貫穿結構204的走線，以提供一或多個輸入/輸出訊號、功率、接地電壓或其組合。沉積製程可以化學氣相沉積法、物理氣相沉積法、原子層沉積法或其他合適的沉積方法。根據此處所提供的揭露與教示，一些製程例如微影、蝕刻、平坦化或清潔操作可使用以形成第一重分佈層250。
接著，形成至少一凸塊260於第一重分佈層250上。舉例而言，在第1E圖中，形成複數個凸塊260於第一重分佈層250上。在一些實施方式中，凸塊260可為焊錫凸塊或為無鉛焊錫，例如錫-銀-銅(Sn-Ag-Au,SAC)合金焊錫、錫-銀合金焊錫、錫-銅合金焊錫或其他合適的材料。在製作完凸塊260後，第1E圖的結構可被翻轉成第1F圖的結構。
第1F的半導體封裝包含半導體晶片210、中介層220、第一重分佈層250、模料240與貫穿結構204。中介層220置於半導體晶片210的第一表面211a上。第一重分佈層250置於半導體晶片210的第二表面211b上，且電性連接至少一半導體晶片210。模料240置於中介層220與第一重分佈層250之間，且連接(或接觸)半導體晶片210的側壁211c。貫穿結構204置於中介層220與模料240中且電性連接至第一重分佈層250。
在一些實施方式中，半導體晶片210的基板212的材質與模料240的材質不同，其可能會產生熱膨脹係數的錯配(mismatch)。熱膨脹係數錯配會在半導體封裝中產生翹曲。此翹曲可能會中斷或降低與毗鄰元件，例如半導體晶片210、第一重分佈層250與貫穿結構204，之間的電性耦合。再者，翹曲可能會在半導體封裝中產生裂鍵。然而，在本實施方式中，中介層220置於半導體晶片210與模料240上。中介層220的楊式模數高於模料240的楊式模數。因此，中介層220係堅硬且較模料240來說較不易變形。更進一步的，因中介層220的熱膨脹係數與半導體晶片210的基板212的熱膨脹係數相似，因此半導體封裝的熱膨脹係數錯配的問題可被改善。如此的結構可改善或抑制半導體封裝的翹曲問題。
在第1F圖，中介層220與半導體晶片210電性絕緣。換言之，半導體晶片210的電性訊號可能會穿過第一重分佈層250、貫穿結構204與凸塊260，但不會穿過中介層220。中介層220亦與貫穿結構204電性絕緣，亦即中介層220可與貫穿結構204電性絕緣，以避免貫穿結構204之間的互相干擾(crosstalk)。
第2圖為根據本揭露一些實施方式的半導體封裝的剖面圖。第2圖與第1F圖的半導體封裝之間的差異在於半導體晶片210與中介層220之間的黏合方法。在第2圖中，黏合層270形成於半導體晶片210與中介層220之間。舉例而言，在第 1B圖的製程中，黏合層270可分別形成於半導體晶片210的第一表面211a上，而中介層220再置於黏合層270上，因此中介層220可藉由黏合層270而接觸半導體晶片210。在一些實施方式中，黏合層270可為膠，然而本揭露不以此為限。至於第2圖的半導體封裝的其他結構細節與第1F圖的半導體封裝相似，因此便不再贅述。
第3圖為根據本揭露一些實施方式的半導體封裝的剖面圖。第3圖與第1F圖的半導體封裝之間的差異在於第二重分佈層280。在第3圖中，第二重分佈層280形成於中介層220上。換言之，中介層220介於第一重分佈層250與第二重分佈層280之間。第二重分佈層280可在形成第一重分佈層250之前(亦即第1D圖的製程)形成或在形成第一重分佈層250之後(亦即第1F圖的製程)形成。第二重分佈層280可包含與一或多個與貫穿結構204耦合的一或多個走線，以定義出其電性連接。在一些實施方式中，第二重分佈層280的形成方法可沉積導電材料於中介層220上，再圖案化導電材料以形成耦合至貫穿結構204的走線，以提供一或多個輸入/輸出訊號、功率、接地電壓或其組合。沉積製程可以化學氣相沉積法、物理氣相沉積法、原子層沉積或其他合適的沉積方法。根據此處所提供的揭露與教示，一些製程例如微影、蝕刻、平坦化或清潔操作可使用以形成第二重分佈層280。至於第3圖的半導體封裝的其他結構細節與第1F圖的半導體封裝相似，因此便不再贅述。
第4圖為根據本揭露一些實施方式的半導體封裝的剖面圖。第4圖與第1F圖的半導體封裝之間的差異在於半導 體裝置。在第4圖中，半導體裝置290與至少一貫穿結構204接合，使得半導體裝置290能夠透過貫穿結構204與第一重分佈層250而與至少一半導體晶片210電性連接。在第4圖中，半導體晶片210置於半導體裝置290與第一重分佈層250之間。半導體裝置290可為記憶體裝置，例如為動態隨機存取記憶體(dynamic random access memory,DRAM)，而本揭露不以此為限。半導體裝置290包含基板292與電路層294，且電路層294面對貫穿結構204。電路層294可藉由連接元件295電性連接至貫穿結構204。連接元件295可為凸塊或金屬層。在一些實施方式中，第3圖的第二重分佈層280可被加入在第4圖的半導體封裝中。至於第4圖的半導體封裝的其他結構細節與第1F圖的半導體封裝相似，因此便不再贅述。
雖然本發明已以實施方式揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。

Claims (19)

  1. 一種半導體封裝，包含：一半導體晶片，具有相對的一第一表面與一第二表面以及至少一側壁，該側壁連接該第一表面與該第二表面；一中介層，置於該半導體晶片的該第一表面上；一融合鍵，形成於該中介層與該半導體晶片之間；一第一重分佈層，置於該半導體晶片的該第二表面上，且電性連接該半導體晶片；以及一模料，置於該中介層與該第一重分佈層之間，且連接該半導體晶片的該側壁。
  2. 如請求項1所述之半導體封裝，更包含一貫穿結構，置於該中介層與該模料中，且電性連接該第一重分佈層。
  3. 如請求項2所述之半導體封裝，更包含一半導體裝置，電性連接該貫穿結構，其中該半導體晶片置於該半導體裝置與該第一重分佈層之間。
  4. 如請求項1所述之半導體封裝，其中該中介層的厚度為約10微米至約1000微米。
  5. 如請求項1所述之半導體封裝，其中該中介層包含矽、二氧化矽、絕緣層上矽或其組合。
  6. 如請求項1所述之半導體封裝，其中該中介層的楊式模數高於該模料的楊式模數。
  7. 如請求項1所述之半導體封裝，其中該中介層的熱膨脹係數小於該模料的熱膨脹係數。
  8. 如請求項1所述之半導體封裝，更包含一黏合層，置於該半導體晶片與該中介層之間。
  9. 如請求項1所述之半導體封裝，更包含一第二重分佈層，而該中介層置於該第一重分佈層與該第二重分佈層之間。
  10. 一種半導體封裝的製造方法，包含：放置一半導體晶片於一載板上；放置一中介層於該半導體晶片上；形成一融合鍵於該中介層與該半導體晶片之間；形成一模料於該載板與該中介層之間，並環繞該半導體晶片；移除該載板；以及形成一第一重分佈層於該半導體晶片上，其中該半導體晶片置於該中介層與該第一重分佈層之間。
  11. 如請求項10所述之方法，其中該中介層包含矽、二氧化矽、絕緣層上矽或其組合。
  12. 如請求項10所述之方法，其中該中介層的楊式模數高於該模料的楊式模數。
  13. 如請求項10所述之方法，其中該中介層的熱膨脹係數小於該模料的熱膨脹係數。
  14. 如請求項10所述之方法，其中放置該中介層於該半導體晶片上的步驟包含：形成一黏合層於該半導體晶片上；以及放置該中介層於該黏合層上。
  15. 如請求項10所述之方法，更包含形成一貫穿結構於該模料與該中介層中。
  16. 如請求項15所述之方法，其中形成該貫穿結構包含：形成一貫穿孔於該模料與該中介層中；以及形成該貫穿結構於該貫穿孔中。
  17. 如請求項15所述之方法，更包含連接一半導體裝置至該貫穿結構，其中該半導體晶片置於該半導體裝置與該第一重分佈層之間。
  18. 如請求項10所述之方法，更包含形成一第二重分佈層於該中介層上，其中該中介層置於該第二重分佈層與該第一重分佈層之間。
  19. 如請求項10所述之方法，更包含形成一凸塊於該第一重分佈層上。
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