TWI633649B - 合併式ｎ／ｐ型電晶體 - Google Patents

合併式ｎ／ｐ型電晶體 Download PDF

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TWI633649B
TWI633649B TW105106681A TW105106681A TWI633649B TW I633649 B TWI633649 B TW I633649B TW 105106681 A TW105106681 A TW 105106681A TW 105106681 A TW105106681 A TW 105106681A TW I633649 B TWI633649 B TW I633649B
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輝 臧
民華 齊
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格羅方德半導體公司
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
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Abstract

一種半導體結構包括半導體基板、至少一個n型或p型的第一延長區、以及至少一個n型或p型中另一個的其它第二延長區，該第一與第二延長區交叉而使得該第一延長區與該第二延長區於共用區交會，並且各共用區上方有共享閘極結構。

Description

合併式N/P型電晶體
本發明大體上涉及用於低功率應用的半導體結構。更具體地說，本發明涉及用於低功率行動應用的合併式n/p場效電晶體結構。
裝置尺寸持續縮減，而且行動應用持續增加，需要超越三維FinFET的新裝置結構及製造程序，對於低功率、高效能行動應用尤其如此。
因此，持續需要新裝置結構及製造程序來符合不斷縮減的裝置尺寸。
通過在一個方面中提供一種半導體結構，得以克服背景技術的缺點，並且提供附加優點。該結構包括半導體基板、至少一個p型與n型其中一個的延長區、至少一個p型與n型中另一個的其它延長區、包含該至少一個延長區與該至少一個其它延長區的交會處的共用區，以及位在各共用區上方的共享閘極。
根據另一方面，提供一種方法。該方法包括提供半導體基板、建立至少一個n型或p型的延長區， 以及建立至少一個n型或p型中另一個的其它延長區，使得該至少一個延長區與該至少一個其它延長區於共用區交會。
本發明的這些及其它目的、特徵及優點通過以下本發明各個態樣的詳細說明，搭配附圖，將會變為顯而易見。
100‧‧‧共用閘極
102‧‧‧基板
104‧‧‧晶鰭
106‧‧‧閘極
108‧‧‧晶鰭
110‧‧‧閘極
112‧‧‧交叉晶鰭
114‧‧‧交叉晶鰭
115‧‧‧輸出電壓
119‧‧‧晶鰭
121‧‧‧晶鰭
130‧‧‧長通道裝置
131‧‧‧源極
132‧‧‧短通道裝置
133‧‧‧汲極
134‧‧‧長通道裝置
135‧‧‧共用閘極
136‧‧‧短通道裝置
137‧‧‧晶鰭
138‧‧‧晶鰭
139‧‧‧晶鰭
140‧‧‧源極
141‧‧‧汲極
142‧‧‧閘極
143‧‧‧源極
144‧‧‧汲極
145‧‧‧晶鰭
147‧‧‧閘極
149‧‧‧晶鰭
150‧‧‧晶鰭
151‧‧‧源極
152‧‧‧汲極
153‧‧‧閘極
160、162、164、166‧‧‧電晶體
200‧‧‧反相器
300‧‧‧反相器
400‧‧‧反相器陣列
500‧‧‧平面型半導體結構
700‧‧‧SRAM胞元
800‧‧‧平面型半導體結構
第1圖根據本發明的一或多個態樣，為交叉鰭形結構的一個實施例的三維透視圖。
第2圖根據本發明的一或多個態樣，繪示包圍交叉晶鰭交會處的共用閘極建立後的第1圖所示結構的一個實施例。
第3圖根據本發明的一或多個態樣，為反相器的一個實施例的頂視圖，該反相器建立有第2圖的交叉晶鰭與閘極結構，所述晶鰭的兩端電氣耦合在一起。
第4圖根據本發明的一或多個態樣，為與第3圖所示類似的反相器的替代實施例，但順著y方向具有兩個交叉晶鰭，而不是一個。
第5圖根據本發明的一或多個態樣，為反相器陣列的一個實施例的頂視圖，該反相器陣列使用多個電氣耦合在一起的第3圖所示反相器。
第6圖根據本發明的一或多個態樣，為非平面型半導體結構的一個實施例的頂視圖，該非平面型半導體結構包括基於交叉鰭形結構的長通道及短通道半導體 裝置。
第7圖根據本發明的一或多個方面，為非平面型半導體結構的另一實施例的頂視圖，該非平面型半導體結構包括基於交叉鰭形結構的p型長通道裝置，以及相鄰於該長通道裝置的短通道裝置。
第8圖根據本發明的一或多個態樣，為基於交叉鰭形結構的半導體SRAM胞元的一個實施例的頂視圖，產生僅需要四個合併電晶體的更小胞元(相比之下，現有的SRAM胞元需要六個現有的電晶體)，所述合併電晶體其中兩者當作反相器作用。
第9圖根據本發明的一或多個態樣，為一種非平面型半導體結構的一個實施例的頂視圖，具有兩個基於交叉鰭形結構的非平面型半導體結構，該種結構有不同取向，在本例中，取向差異約90°。
第10圖根據本發明的一或多個態樣，為一般FinFET製造程序及用以實施交叉鰭形結構的附加步驟的高階流程圖。
本發明的多個方面及特定特徵、優點、及其細節是引用附圖所示非限制性實施例於下文更完整闡釋。省略眾所周知的材料、製造工具、處理技術等說明以避免非必要地混淆本發明的詳細說明。然而，應該瞭解的是，詳細說明及特定實施例雖然指示本發明的多個態樣，仍僅以說明方式來提供，並非作為限制。本發明概念的精 神及/或範疇內的各種取代、修改、新增及/或配置通過本發明對本領域技術人員將顯而易見。
本說明書及申請專利範圍各處近似語言於本文中使用時，可套用來修飾任何定量表徵，可許可改變此定量表徵，但不會改變與其有關的基本功能。因此，一或多個諸如“約”的用語所修飾的值並不受限於指定的精確值。在一些實例中，該近似語言可對應於儀器測量該值時的精確度。
本文所使用的術語用途只是說明特定實施例並且無意於限制本發明。如本文中所用，單數形式“一”、“一種”、“一個”、以及“該”的用意在於同時包括複數形式，上下文另有所指除外。將再理解術語“包含”(以及包含的任何形式，如單數的“包含”和動名詞的“包含”)、“具有”(以及具有的任何形式，如單數的“具有”和動名詞的“具有”)、“包括”(以及包含的任何形式，如單數的“包括”和動名詞的“包括”)、“含有”(以及包含的任何形式，如單數的“含有”和動名詞的“含有”)為開放式連接動詞。因此，“包含”、“具有”、“包括”或“含有”一或多個步驟或元件的方法或裝置處理那些一或多個步驟或元件，但不受限於僅處理那些一或多個步驟或元件。同樣地，“包含”、“具有”、“包括”或“含有”一或多個特徵的方法的步驟或裝置的元件處理那些一或多個特徵，但不受限於僅處理那些一或多個特徵。此外，以特定方式予以配置的裝置或結構是以 至少那方式予以配置，但也可用未列示的方式予以配置。
“連接”一詞於本文中使用時，若是在指稱為兩個實體元件時使用，意為介於該兩個實體元件之間的直接連接。然而，“耦合”一詞可意為直接連接或通過一或多個中間元件的連接。
“可”及“可以是”等詞於本文中使用時，指出一組狀況中出現的可能性；是否具備指定屬性、特性或功能；及/或通過表達與修飾過的動詞相關的能力、功能或可能性其中一或多個來修飾另一動詞。因此，“可”及“可以是”在使用時，指出修飾過的用語明顯適當、可用，或適用於指示的容量、功能或用途，同時還考慮在一些狀況下，修飾過的用語有時可能不適當、可用，或適用。舉例而言，在一些狀況下，事件或容量會是在意料之中，而在其它狀況下，該事件或容量並不會出現，這樣的區別是通過“可”及“可以是”等用語來獲得。
下文引用為易於瞭解未依比例繪示的圖式，其中各個不同圖中所用相同的參考元件符號表示相同或類似組件。
第1圖根據本發明的一或多個態樣，為基板102上交叉鰭形(晶鰭104與108)結構的一個實施例的三維透視圖。更普遍來說，晶鰭是隆起結構(相對基板隆起)的實施例。
該交叉鰭形結構舉例而言，可使用已知程序及技術以現有的方式來製造(例如，現有建立晶鰭的程 序；先順著一個方向進行，然後順著另一個方向進行)。雖然為了簡單起見，僅展示單一交叉鰭形結構，仍將瞭解的是，實際上，同一主體基板上典型為包括許多此類結構。再者，雖然所示為三維結構，本發明在平面型及非平面型(或三維)半導體應用中仍然都適用。又再者，給定共用區中的晶鰭(更普遍來說，延長區)可具有相同或不同寬度。
在一個實施例中，基板102可包括任何含矽基板，其包括但不局限於矽(Si)、單晶矽、多晶Si、非晶Si、氣孔上覆矽(SON)、絕緣層上覆矽(SOI)、或取代絕緣層上覆矽(SRI)或矽鍺基板及類似者。基板102可另外或反而包括各種隔離、摻雜及/或裝置特徵。基板可包括其它合適的基本半導體，舉例而言，例如：晶體中的鍺(Ge)、化合物半導體，諸如碳化矽(SiC)、砷化鎵(GaAs)，磷化鎵(GaP)、磷化銦(InP)、砷化銦(InAs)、及/或銻化銦(InSb)或其組合；合金半導體，包括GaAsP、AlInAs、GaInAs、GaInP、或GaInAsP或其組合。
該一或多個隆起結構(在本實施例中，晶鰭104與108)可從主體基板蝕刻而來，並且舉例而言，可包括上列與基板有關材料的任一個。再者，該一或多個隆起結構中有一些或全部可包括(例如通過摻雜的)添加雜質，使其成為n型或p型。
第2圖根據本發明的一或多個態樣，繪示包圍交叉晶鰭(104與108)交會處(第1圖的106)的共 用閘極110建立後的第1圖所示結構100的一個實施例。
在本實施例中，共用閘極100可以是虛設閘極(dummy gate)(也就是，使用取代閘極程序時)或傳導(或最終)閘極(也就是，使用“閘極先製”製造程序)。再者，共用閘極(或“閘極堆疊”)可為對稱或不對稱；換句話說，共用閘極在所述晶鰭(更普遍來說，n型或p型的延長區)的交會處可失準(misalignment)。以上注意到，所述晶鰭可具有添加雜質。然而，對於完全空乏操作而言，所述晶鰭在包圍該交會處的共用區(即通道(channel))中應該沒有雜質，相比之下，共用區外側的晶鰭典型為具有高濃度的雜質(當作源極與汲極使用)。另外，應注意的是，共用閘極底下的通道區可包括磊晶半導體材料，例如，用於p型合併電晶體的磊晶矽鍺(e-SiGe)，或用於n型合併電晶體的磊晶矽(e-Si)或磊晶碳化矽(e-SiC)。
第3圖根據本發明的一或多個態樣，為反相器200的一個實施例的頂視圖，該反相器建立有第2圖的交叉鰭形與共用閘極結構(104、108及110)，各交叉晶鰭(112與114)的一端舉例而言，通過為簡單起見未展示的源極/汲極上面的矽化物或接觸金屬電氣耦合在一起。
注意交叉晶鰭不需要有相同寬度，但如第3圖所示，可以是不同寬度。在一個實施例中，晶鰭108(垂直晶鰭)為n型且晶鰭104(水平晶鰭)為p型，晶鰭108連結至Vss且晶鰭104連結至Vcc(例如，通過接觸金屬， 為簡單起見，圖中未展示)。若施加於共用閘極110的電壓高(Vcc)(例如：通過位在閘極106上面的接觸部，圖中未展示)，則該閘極(即通道)下面的晶鰭變為n型(電子)，但閘極外側的晶鰭104保留高濃度的p型雜質(電洞)，閘極106外側晶鰭104的一端連接至Vcc，而且輸出電壓115低(Vss)，反之亦然。因此，共用閘極當作反相器的輸入節點作用。注意反相器可在主體半導體或絕緣層上覆矽(SOI)基板上形成。
第4圖根據本發明的一或多個態樣，為與第3圖所示類似的反相器300的替代實施例，但順著y方向具有兩個交叉晶鰭(108與116)，而不是一個。在一個實施例中，晶鰭108與116為n型，而晶鰭104為p型。反相器300的操作與第2圖中反相器200的操作類似。一般而言，反相器可包括用於n型與p型晶鰭其中一個或兩者的多個晶鰭。
第5圖根據本發明的一或多個態樣，為反相器陣列400的一個實施例的頂視圖，該反相器陣列包括電氣耦合在一起的第3圖所示類型的多個反相器(118、120、122、124、126及128)。第3圖也繪示晶鰭中，舉例而言，在晶鰭形成期間使用“切割(CUT)”遮罩在裝置彼此間刻意進行切割而用於電隔離的部分。
在一個實施例中，如第5圖所示，反相器陣列可順著X與Y方向在晶鰭網格上形成。注意晶鰭寬度及晶鰭與晶鰭的間距順著X方向與Y方向可以不同。在一 個實施例中，使用可在陣列各處複製的反相器118，晶鰭119(垂直或Y方向晶鰭)可為n型，而晶鰭121(水平或X方向晶鰭)可為p型，其中晶鰭119連結至Vss而晶鰭121連結至Vcc。注意如本領域技術人員所知，反相器可在BEOL(製造方法產線後端，圖中未展示)使用附加接觸部及金屬互連物連接成邏輯電路。
第6圖根據本發明的一或多個態樣，為非平面型半導體結構500的一個實施例的頂視圖，該非平面型半導體結構包括基於交叉鰭形結構的長通道130及短通道132(與現有類似)半導體裝置。
如第6圖所示，長通道裝置130順著X方向繪示成具有四個Y方向組合晶鰭的晶鰭間距，而短通道裝置132繪示成順著Y方向並且位在單一Y方向晶鰭上。長通道裝置130舉例而言，包括源極131與汲極133，共用閘極135覆蓋晶鰭137與晶鰭138的交會處(即通道)。相比之下，短通道裝置132包括位在單一晶鰭139上的源極140、汲極141、閘極142，晶鰭139的通道部分位在介於源極與汲極間的閘極142下面。注意，雖然為簡單起見未展示，長通道裝置與短通道裝置舉例而言，是通過使用“切割”遮罩移除非所欲連接至相離裝置(如第5圖所示)的晶鰭而彼此電隔離。因此，現有的長通道或短通道MOSFET也可通過交叉晶鰭陣列及共用閘極結構來形成。
第7圖根據本發明的一或多個態樣，為非平面型半導體結構600的另一實施例的頂視圖，該非平面 型半導體結構包括基於交叉鰭形結構的p型長通道裝置(例如：長通道裝置134)，以及與長通道裝置相鄰的n型短通道裝置(例如：短通道裝置136)。
P型長通道裝置134舉例而言，包括順著X方向位在晶鰭145(假設所有X方向晶鰭都是p型)上的源極143、汲極144，以及共用閘極147，該共用閘極覆蓋X方向晶鰭與多個(本例中為四個)順著Y方向的晶鰭149的交會處。N型短通道裝置136舉例而言，包括位在Y方向晶鰭150(假設所有Y方向晶鰭都是n型)上的源極151、汲極152及閘極153。注意長通道裝置134可用短通道裝置136上的偏壓來調製，使長通道裝置具有不同的臨限電壓。
第8圖根據本發明的一或多個態樣，為基於交叉鰭形結構(請不要與第5圖的反相器陣列400搞混)的SRAM胞元700的一個實施例的頂視圖，該交叉鰭形結構產生的胞元更小，只需要四個合併電晶體160、162、164及166(現有的SRAM胞元相較之下需要六個現有的電晶體)，所述合併電晶體其中兩個當作反相器(142與144)作用，而另兩個(160與162)當作通道電晶體(pass transistor)作用。
由於鰭端(例如，鰭端168與170)電氣耦合的關係，裝置160與162為合併電晶體(無電氣耦合的鰭端)，舉例而言，可當作n型通道電晶體使用(也就是，共用閘極外側的p型晶鰭部分沒有用到，而是保持浮動 (floating)無電連接)，而裝置164與166為反相器。在一個實施例中，SRAM功能是在當Y方向晶鰭(n型)通過接觸部與金屬連結至Vss(接地)時達成，此時介於反相器(X方向p型晶鰭)彼此間的共用節點連結至Vcc。反相器172與174將分別有低與高電壓輸出，並且連接至通道電晶體160與162，而且通過接觸部/金屬(圖中未展示)分別交叉耦合至166與164的閘極。寫入線176使通道電晶體160與162兩者接通。160與162的輸出分別展示為178與180。
第9圖根據本發明的一或多個態樣，為非平面型半導體結構800的一個實施例的頂視圖，交叉鰭形結構在建立附加晶鰭之前具有兩組非平面型半導體結構或晶鰭(146與148)，所述結構彼此有不同取向，在本例中，取向有約90°差異。視需要地，所述組晶鰭其中一個可用於製造現有的FinFET，而另一組用於交叉鰭形結構。再者，若X方向晶鰭與Y方向晶鰭的摻雜極性相反(請參閱第3、4及7圖)，交叉晶鰭反相器及長/短電晶體也隨著極性變化(例如：p型水平電晶體變為n型電晶體，反之亦然)而作用，當然，也隨著適當的偏壓連接(例如：反向Vss與Vcc)而作用。
第10圖根據本發明的一或多個態樣，為現有FinFET製造程序的一個實施例的高階流程簡圖900，流程是示於左側(使用閘極後製造方法序)，而右側流程是附加步驟；兩側流程的組合實施交叉鰭形結構，並且建立合 併電晶體。該流程的所有個別態樣舉例而言，可使用現有的程序及技術來進行。
製造流程始於在基板上形成交叉晶鰭(第10圖的200)。大體上請參閱第1圖。在一個實施例中，第一遮罩用於蝕刻交叉晶鰭對的其中一個晶鰭，第二晶鰭舉例而言，是使用第二遮罩，舉一個實施例來說，通過將晶圓轉動90°來建立(第10圖的202)。在任一例中，接著形成必要井體(n及/或p)(第10圖的204)。其次為虛設閘極形成(第10圖的206)，採用的形式為共用虛設閘極形成(第10圖的208)；也就是，兩交叉晶鰭共用一虛設閘極。大體上請參閱第2圖。接著形成源極與汲極(第10圖的210)，首先順著一個方向然後另一方向(第10圖的212)。舉例而言，請參閱第6圖的長通道裝置。源極/汲極形成之後，虛設閘極是以傳導閘極來取代(第10圖的214)，該傳導閘極在本例中採用的形式為取代共用傳導閘極(第10圖的216)。以傳導閘極取代共用虛設閘極之後，所述交叉晶鰭其中一個可形成通道，然後是另一個；在本例中，一個晶鰭的通道中形成磊晶半導體材料，然後是另一個晶鰭(第10圖的218)。於此點，可形成接至裝置的接觸部(第10圖的220)，然後此製造過程進入典型的後段製造方法處理(第10圖的222)。
在第一態樣中，以上揭示的是一種半導體結構。該結構包括半導體基板、一或多個p型與n型其中一個的延長區(例如：位在非平面型結構中的(多個)晶 鰭)、一或多個p型與n型其中另一個的其它延長區、包括所述延長區彼此交會處的共用區，以及位在各共用區上方的共享閘極結構。
在一個實施例中，所述延長區舉例而言，可坐落於該基板中，即平面結構。
在一個實施例中，第一態樣的半導體結構舉例而言，可更包括多個耦合至基板的隆起半導體結構，而所述延長區及所述其它延長區各可坐落於不同的隆起結構中。在一個實施例中，第一態樣的半導體結構的所述延長區舉例而言，可具有與所述其它延長區不同的寬度。
在一個實施例中，第一態樣的起始結構的所述共用區舉例而言，可包括的延長區比其它延長區多一個。
在一個實施例中，舉例而言，與共用區外側相比，在共用區中，第一態樣的半導體結構中對應延長區的添加雜質量更少。在一個實施例中，所述共用區舉例而言，可以沒有添加雜質。
在一個實施例中，第一態樣的起始結構的共享閘極舉例而言，可包括虛設閘極。
在一個實施例中，第一態樣的起始結構的共享閘極舉例而言，可包括傳導閘極。在一個實施例中，第一態樣的起始結構的共享閘極舉例而言，可包括單一中間隙功函數材料，例如碳化鈦(TiC)。
在一個實施例中，第一態樣的起始結構的 所述延長區舉例而言，可包括一個延長區、包括一個其它延長區的所述其它延長區、共用區外側所述延長區的一端與所述其它延長區的一端，舉例而言，可電氣短路，並且該結構當作反相器作用。此類反相器適用於低電壓(例如：Vcc<0.8v)應用，而且，若通道完全空乏，也適用於低功率應用。
在一個實施例中，該半導體結構舉例而言，可包括反相器陣列，所述反相器舉例而言，可連接成邏輯電路。
在一個實施例中，第一態樣的起始結構的所述延長區與所述其它延長區舉例而言，可包括磊晶半導體材料。
在一個實施例中，第一態樣的半導體結構舉例而言，可包括長通道電晶體，而所述延長區中的通道跨越所述其它(交叉)延長區其中至少兩個。
在一個實施例中，包括長通道電晶體的半導體結構舉例而言，可更包括共用區外側沿著所述其它延長區其中一個的短通道電晶體。在另一個實施例中，包括長通道電晶體的半導體結構舉例而言，可更包括共用區內側沿著所述其它延長區其中一個的短通道電晶體。
在一個實施例中，第一態樣的起始結構的所述延長區舉例而言，可包括兩個延長區，所述其它延長區舉例而言，可包括兩個其它延長區，各延長區交會所述其它延長區其中兩個，而各該其它延長區交會所述延長區 其中兩個，四個共用區由所述交會處建立，該結構當作SRAM胞元作用。
在一個實施例中，第一態樣的半導體結構舉例而言，可包括多個分離的此類結構，各該分離結構具有不同的臨限電壓。
在第二方面中，以上揭示的是一種方法。該方法包括提供半導體基板、建立一或多個n型或p型的延長區，以及建立至少一個n型或p型中另一個的其它延長區，使得所述延長區於共用區交會。
在一個實施例中，本方法舉例而言，可更包括在共用區上方建立共用閘極。
儘管本文中已說明並且繪示本發明的數種態樣，本領域技術人員仍可用替代方面來達成相同的目的。因此，隨附申請專利範圍的用意在於涵蓋所有此類屬於本發明真實精神與範疇內的替代態樣。

Claims (18)

  1. 一種半導體結構，其包含：半導體基板；至少一個p型與n型其中一個的延長區；至少一個p型與n型中另一個的其它延長區；共用區，該共用區包含該至少一個延長區與該至少一個其它延長區的交會處，其中，遍及該共用區對應延長區的添加雜質量係少於該共用區外對應延長區的添加雜質量，該交會處對應延長區的添加雜質量係少於該共用區內該交會處外對應延長區的添加雜質量；以及位在各共用區上方的共享閘極結構。
  2. 如申請專利範圍第1項所述的半導體結構，其中，該至少一個延長區與該至少一個其它延長區坐落於該基板中。
  3. 如申請專利範圍第1項所述的半導體結構，更包含多個耦合至該基板的隆起半導體結構，該至少一個延長區及該至少一個其它延長區各坐落於不同的隆起結構。
  4. 如申請專利範圍第1項所述的半導體結構，其中，該至少一個延長區的一或多個具有與該至少一個其它延長區的一或多個不同的寬度。
  5. 如申請專利範圍第1項所述的半導體結構，其中，該共用區包含的該至少一個延長區比包含的該至少一個其它延長區多。
  6. 如申請專利範圍第1項所述的半導體結構，其中，該共 享閘極包含虛設閘極。
  7. 如申請專利範圍第1項所述的半導體結構，其中，該共享閘極包含傳導閘極。
  8. 如申請專利範圍第7項所述的半導體結構，其中，該傳導閘極包含單一中間隙功函數材料。
  9. 如申請專利範圍第1項所述的半導體結構，其中，該至少一個延長區包含一個延長區，其中，該至少一個其它延長區包含一個其它延長區，其中，在該共用區外該延長區的一端與該其它延長區的一端電氣短路，並且其中，該結構當作反相器作用。
  10. 如申請專利範圍第9項所述的半導體結構，其包含數個該反相器構成的陣列。
  11. 如申請專利範圍第1項所述的半導體結構，其中，該至少一個延長區的一或多個及該至少一個其它延長區的一或多個包含磊晶半導體材料。
  12. 如申請專利範圍第1項所述的半導體結構，其中，該結構包含長通道電晶體，並且其中，該至少一個延長區中的通道跨越該至少一個其它延長區的至少兩個。
  13. 如申請專利範圍第12項所述的半導體結構，更包含沿著該至少一個其它延長區的該至少兩個的其中一個位在該共用區外的短通道。
  14. 如申請專利範圍第12項所述的半導體結構，更包含沿著該至少一個其它延長區的該至少兩個的其中一個位在該共用區內側的短通道。
  15. 如申請專利範圍第1項所述的半導體結構，其中，該至少一個延長區包含兩個延長區，其中，該至少一個其它延長區包含兩個其它延長區，各延長區交會這兩個該其它延長區，而各該其它延長區交會這兩個該延長區，其中，四個共用區由所述交會處建立，並且其中，該結構當作SRAM胞元作用。
  16. 如申請專利範圍第1項所述的半導體結構，其包含至少兩個分離的此類結構，各該分離結構具有不同的臨限電壓。
  17. 一種形成半導體結構之方法，該方法包含：提供半導體基板；建立至少一個n型或p型的延長區；以及建立至少一個n型或p型中另一個的其它延長區，使得該至少一個延長區與該至少一個其它延長區於共用區交會，其中，遍及該共用區對應延長區的添加雜質量係少於該共用區外對應延長區的添加雜質量，交會處對應延長區的添加雜質量係少於該共用區內該交會處外對應延長區的添加雜質量。
  18. 如申請專利範圍第17項所述的方法，更包含在該共用區上方建立共用閘極。
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