TWI631685B - 緊密靜電放電保護結構 - Google Patents
緊密靜電放電保護結構 Download PDFInfo
- Publication number
- TWI631685B TWI631685B TW103115860A TW103115860A TWI631685B TW I631685 B TWI631685 B TW I631685B TW 103115860 A TW103115860 A TW 103115860A TW 103115860 A TW103115860 A TW 103115860A TW I631685 B TWI631685 B TW I631685B
- Authority
- TW
- Taiwan
- Prior art keywords
- diode
- coupled
- field effect
- protection device
- integrated circuit
- Prior art date
Links
- 230000005669 field effect Effects 0.000 claims abstract description 35
- 230000001939 inductive effect Effects 0.000 claims abstract description 6
- 239000003990 capacitor Substances 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 4
- 238000000605 extraction Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 2
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
本發明揭示一種緊密靜電放電(ESD)保護結構,其包括:一多閘極肖特基空乏型場效應電晶體(FET)、至少一個二極體及兩個電阻器。此ESD保護器件結構可係佈設於比典型多個二極體ESD器件所需小之一區域中。該多閘極FET可包括各種類型之高電子遷移率電晶體(HEMT)器件,例如,(假晶)pHEMT、(變質)mHEMT、感應HEMT。該肖特基場效應器件之多個閘極係用於形成一ESD觸發及電荷汲取路徑,以用於依據該ESD保護器件之電路保護。單極性及雙極性ESD保護器件兩者皆可係提供於一積體電路晶粒上,用於保護其輸入/輸出電路。
Description
本申請案主張由Pei-Ming Daniel Chow、Yon-Lin Kok、Jing Zhu及Steven Schell於2013年5月3日申請之標題為「Compact ESD Protection Structure」之共同擁有之美國臨時專利申請案第61/819,252號之優先權,且該申請案據此出於所有目的以引用之方式併入本文中。
本發明係關於半導體保護結構,特定而言,係關於靜電放電(ESD)保護結構。
一肖特基(Schottky)閘極空乏型場效應器件由於其精細金屬閘極結構(0.5μm或更小金屬閘極長度)而對ESD損壞敏感。不同於CMOS矽或雙極電晶體程序,在一高電子遷移率電晶體(HEMT)程序中不存在可用於形成一緊密ESD保護二極體之強健P-N接面二極體。一HEMT(亦被稱為異質結構FET(HFET)或調變摻雜FET(MODFET))係代替一經摻雜區(如通常MOSFET之情形)在具有不同帶隙之兩種材料之間併入一接面(亦即,一異質接面)作為通道之一場效應電晶體。存在數個版本之HEMT,例如,假晶HEMT(pHEMT)、變質HEMT(mHEMT)、感應HEMT等。形成有pHEMT器件之閘極之數個大肖特
基二極體必須串聯級聯以充分保護主動HEMT電路。此多個肖特基二極體消耗一昂貴GaAs積體電路晶粒中之一大區域。
一肖特基二極體(亦被稱為一熱載流子二極體)係具有一低正向電壓降及一非常快速之切換動作之一半導體二極體。當電流流經一個二極體時,跨越二極體端子存在一小電壓降。一正常二極體將具有在0.6伏特至1.7伏特之間之一電壓降,而一肖特基二極體電壓降通常在0.15伏特與0.45伏特之間。此較低電壓降提供較佳系統效率及較高切換速度。在一肖特基二極體中,一半導體-金屬接面形成於一半導體與一金屬之間,因此形成一肖特基障壁。一N型半導體充當陰極且金屬側充當肖特基二極體之陽極。此肖特基障壁導致一低正向電壓降及非常快速之切換兩者。可藉由級聯數個大肖特基二極體來提供ESD保護。由於肖特基二極體之低接通電壓,因此需要數個經堆疊二極體來處置操作電壓,且需要一大區域來處置電流。因此,使用一肖特基二極體組態需要一大晶粒區域。
因而,需要一種與不需要使用肖特基二極體之HEMT及其他半導體器件相容之有效且緊密ESD保護結構。
根據一實施例,一種靜電放電(ESD)保護器件可包括:一場效應電晶體(FET),其具有一汲極、至少兩個閘極及一源極,其中其該汲極可耦合至一電路之一節點以保護該電路免受一ESD事件;至少一個二極體,其耦合在該FET之該源極與一電源供應共同點之間;一第一電阻器,其耦合在該FET之該至少兩個閘極之間;及一第二電阻器,其耦合至該至少兩個閘極及該電源供應共同點中之一者。
根據又一實施例,該至少兩個閘極中之一者可係一觸發閘極且該至少兩個閘極中之另一者可係一放電閘極。根據又一實施例,該FET可係一空乏型FET。根據又一實施例,該至少一個二極體可係串
聯連接在該FET之該源極與該電源供應共同點之間之兩個二極體。根據又一實施例,該電源供應共同點可耦合至一電接地。根據又一實施例,該空乏型FET可係一高電子遷移率電晶體(HEMT)。根據又一實施例,該HEMT可係一假晶HEMT(pHEMT)。根據又一實施例,該HEMT可係一變質HEMT(mHEMT)。根據又一實施例,該HEMT可係一感應HEMT。
根據又一實施例,該FET、該至少一個二極體及該第一電阻器及該第二電阻器可製作於一積體電路晶粒上且耦合至該電路節點,該電路節點可耦合至該積體電路晶粒之一外部連接。根據又一實施例,該積體電路晶粒之該外部連接之一功能可選自由以下各項組成之群組:一類比輸入、一數位輸入、一類比輸出、一數位輸出、一類比輸入/輸出、一數位輸入/輸出、一電源連接、一偏壓輸入及一外部補償電容器。
根據另一實施例,一種靜電放電(ESD)保護器件可包括:一場效應電晶體(FET),其具有一汲取、至少兩個閘極及一源極,其中其該汲取可經耦合至一電路之一節點以保護該電路免受一ESD事件;至少一個第一二極體,其具有經耦合至該第一FET之該源極之一陽極;一第一電阻器,其係耦合於該第一FET之該至少兩個閘極之間;及一第二電阻器,其經耦合至該至少兩個閘極及該至少一個第一二極體之一陰極中之一者;一第二場效應電晶體(FET),其具有一汲取、至少兩個閘極及一源極,其中其該汲極可經耦合至一電源供應共同點;至少一個第二二極體,其具有經耦合至該至少一個第一二極體之該陰極之一陰極;一第三電阻器,其係耦合於該第二FET之該至少兩個閘極之間;及一第四電阻器,其經耦合至第二FET之該至少兩個閘極及該至少一個第二二極體之一陰極中之一者。
根據又一實施例,該第一FET及該第二FET之該至少兩個閘極中
之一者可係觸發閘極,且該第一FET及該第二FET之該至少兩個閘極中之另一者可係放電閘極。根據又一實施例,該第一FET及該第二FET可係空乏型FET。根據又一實施例,該至少一個第一二極體及該至少一個第二二極體可係各自串聯連接於該第一FET之源極與該第二FET之該源極之間的兩個二極體。根據又一實施例,該電源供應共同點可經耦合至一電接地。根據又一實施例,該第一空乏型FET及該第二空乏型FET可係高電子遷移率電晶體(HEMT)。根據又一實施例,該等HEMT可係選自由以下各項組成之群組:假晶HEMT(pHEMT)、變質HEMT(mHEMT)及感應HEMT。
根據又一實施例,該第一FET及該第二FET、該至少一個第一二極體及該至少一個第二二極體以及該第一電阻器、該第二電阻器、該第三電阻器及該第四電阻器可係製作於一積體電路晶粒上且經耦合至該電路節點,該電路節點可經耦合至該積體電路晶粒之一外部連接。根據又一實施例,該積體電路晶粒之該外部連接之一功能可包括一射頻信號輸入。根據又一實施例,該積體電路晶粒之該外部連接之一功能可包括一射頻信號輸出。
106‧‧‧障壁
108‧‧‧間隔物
110‧‧‧二維電子氣體層
112‧‧‧基板
202‧‧‧單極性單閘極靜電放電保護器件/靜電放電保護器件/先前技術靜電放電保護器件
206‧‧‧電路
208‧‧‧場效應電晶體/電晶體/空乏型電晶體/電晶體
210‧‧‧第一閘極電阻器/第一電阻器
212‧‧‧第二閘極電阻器/第二電阻器
214‧‧‧第一肖特基二極體/肖特基二極體/位準移位二極體
216‧‧‧第二肖特基二極體/肖特基二極體/位準移位二極體
218‧‧‧第三二極體/觸發式第三二極體
302‧‧‧單極性靜電放電保護器件/靜電放電保護器件/單極性多閘極靜電放電保護器件
304‧‧‧節點
308‧‧‧多閘極肖特基空乏型場效應電晶體/場效應電晶體/多閘極結構場效應電晶體/第一高電子遷移率電晶體器件/元件
310‧‧‧第一閘極電阻器/元件
312‧‧‧第二閘極電阻器/元件
314‧‧‧第一二極體/元件
316‧‧‧第二二極體/元件
702‧‧‧雙極性多閘極肖特基空乏型場效應電晶體靜電放電保護器件/靜電放電保護器件/雙極性多閘極場效應電晶體靜電放電保護器件
706‧‧‧電路
708‧‧‧第二高電子遷移率電晶體器件/元件
710‧‧‧第三閘極電阻器/元件
712‧‧‧第四閘極電阻器/元件
714‧‧‧第三二極體/元件
716‧‧‧第四二極體/元件
D‧‧‧汲極
G‧‧‧閘極
G1‧‧‧第一閘極/第一觸發閘極
G2‧‧‧第二閘極/第二觸發閘極
S‧‧‧源極
藉由參考結合附圖進行之以下說明可更完全地理解本發明,附圖中:圖1圖解說明根據本發明之教示之一HEMT器件之一示意性等角剖面圖;圖2圖解說明用於直流(DC)及控制埠之一先前技術單極性空乏型FET ESD保護器件之一示意圖;圖3圖解說明根據本發明之一特定實例性實施例之用於直流(DC)及控制埠之一單極性多閘極肖特基空乏型FET ESD保護器件之一示意圖;
圖4圖解說明用於在圖2中展示之ESD保護器件之一先前技術結構之一示意性平面視圖;圖5圖解說明根據本發明之一特定實例性實施例之用於在圖3中展示之ESD保護器件之一結構之一示意性平面視圖;圖6圖解說明根據本發明之一特定實例性實施例之用於在圖3中展示之ESD保護器件之一結構之一更詳細示意性平面視圖;圖7圖解說明根據本發明之另一特定實例性實施例之用於射頻(RF)埠之一雙極性多閘極肖特基空乏型FET ESD保護器件之一示意圖;及圖8及圖8A圖解說明根據本發明之一特定實例性實施例之用於在圖7中展示之ESD保護器件之一結構之一示意性平面視圖。
雖然本發明易於作出各種修改及替代形式,但在圖式中展示並在本文中詳細闡述其特定實例性實施例。然而,應理解,本文對特定實例性實施例之說明並非意欲將本發明限制於本文所揭示之特定形式,而是相反,本發明意欲涵蓋所附申請專利範圍所界定之所有修改及等效形式。
根據各項實施例,一假晶高電子遷移率電晶體(pHEMT)(亦被稱為異質結構FET或調變摻雜FET)在本文中作為一實例用來闡述根據本文所揭示之各項實施例之一緊密ESD保護器件之概念。迄今為止,數個大肖特基二極體必須形成有一pHEMT器件之閘極並串聯級聯以增加電壓並充分保護主動電路。此多個二極體器件消耗一昂貴GaAs積體電路晶粒中之一大區域。根據本發明之各項實施例,提出使用一多閘極HEMT來形成一緊密ESD保護器件。HEMT器件之多閘極可用於形成ESD觸發及電荷汲取路徑以用於保護在該等ESD保護器件及結構之後的電路。可將ESD保護器件結構佈設在比多個二極體ESD器件結
構小得多之一區域中。預期且在本發明之範疇內,各種類型之HEMT器件(例如,pHEMT、mHEMT、感應HEMT等)可與本文所揭示之ESD保護器件一起使用。
現在參考圖式,其示意性地圖解說明實例性實施例之細節。圖式中,將由相似編號表示相似元件,且將由帶有一不同小寫字母後綴之相似編號表示類似元件。
參考圖1,根據本發明之教示繪示一HEMT器件之一示意性等角剖面圖。出於說明性目的展示一pHEMT,但預期且在本發明之範疇內,可根據本發明之教示類似地使用其他HEMT器件。HEMT器件可包括一基板112、一個二維電子氣體層110、一間隔物108、一障壁106、一覆蓋層104,以及金屬汲極、源極及閘極電極102。源極、閘極及汲極金屬102可包括(但不限於)金。障壁106可包括(但不限於)砷化鋁鎵(AlGaAs)。間隔物108可包括(但不限於)砷化鎵(GaAs)。二維電子氣體層110可包括(但不限於)砷化銦鎵(InGaAs)。基板可包括(但不限於)高電阻率GaAs。第一電阻器210可具有自約500歐姆至約2000歐姆之一電阻值。第二電阻器212可具有約2000歐姆之一電阻值。
參考圖2及圖4,所繪示者係用於直流(DC)及控制埠之一先前技術單極性空乏型FET ESD保護器件之一示意圖,以及用於在圖2中展示之ESD保護器件之先前技術結構之一示意性平面視圖。一單極性單閘極ESD保護器件202已用於保護一積體電路封裝(未展示)之電路206的控制信號及/或偏壓供應節點(接腳)。ESD保護器件202可包括:一場效應電晶體(FET)208,其具有一汲極(D)、一源極(S)及一單個閘極(G);第一肖特基二極體214及第二肖特基二極體216;一第三二極體218;及第一閘極電阻器210及第二閘極電阻器212。第三二極體218係當發生一ESD事件時導電(進入雪崩崩潰)從而接通電晶體208之一觸發二極體。肖特基二極體214及216係用於電壓位準移位以防止空乏型電
晶體208在正常操作期間接通及傳導電流。
參考圖3、圖5及圖6,所繪示者係根據本發明之一特定實例性實施例之用於直流(DC)及控制埠之一單極性多閘極肖特基空乏型FET ESD保護器件之一示意圖,以及用於在圖3中展示之ESD保護器件之一結構之示意性平面視圖。具有肖特基多閘極之一單極性ESD保護器件302可用於保護一積體電路封裝(未展示)之電路306的控制信號及/或偏壓供應節點(接腳)。ESD保護器件302可包括:一多閘極肖特基空乏型場效應電晶體(FET)308(例如,HEMT器件),其具有一汲極(D)、一源極(S)、第一觸發閘極(G1)及第二觸發閘極(G2);第一二極體314及第二二極體316;及第一閘極電阻器310及第二閘極電阻器312。預期且在本發明之範疇內,FET 308可具有兩個或兩個以上閘極。至少一個位準移位二極體可經耦合於FET 308之源極與一電源供應共同點(例如,一電接地)之間。FET 308之汲極可經耦合至一節點304,節點304可經耦合至一積體電路(IC)封裝(未展示)之一外部連接(接腳)。IC封裝之外部連接(接腳)可用作(舉例而言,但不限於)一類比輸入、一數位輸入、一類比輸出、一數位輸出、一類比輸入/輸出、一數位輸入/輸出、一電源連接、一偏壓輸入、一外部補償電容器等。
當負靜電電荷在節點304處累積時,將正向加偏壓於第二觸發閘極(G2),並透過第二閘極電阻器312將此等電荷汲取至接地。當正靜電電荷在節點304處累積時,將積聚一正電位,直至第一觸發閘極(G1)處於反向崩潰中。此崩潰電流將流動至接地,並跨越第二閘極電阻器312建立一正電位。因此,當閘極至源極電位比串聯連接之第一二極體314及第二二極體316之接通電壓更具正性時,提供足夠電壓以藉助其第二閘極G2接通FET 308。此第一二極體314及第二二極體316係耦合於FET 308之源極與一電源供應共同點(例如,接地)之間,並提供電壓位準移位以防止一空乏型電晶體接通(導電)。FET 308之汲
極電流提供另一路徑以使節點304處之正靜電電荷消散,並有助於防止第一觸發閘極G1具有可損壞第一觸發閘極G1之過量崩潰電流。
由此,一多閘極結構FET 308係組合一觸發二極體器件與一放電閘極FET以節省寶貴積體電路晶粒區域之一獨特方式。另外,僅三個主動器件區域對單極性多閘極ESD保護器件302係必需的:1)FET 308、2)第一二極體314,及3)第二二極體316。先前技術ESD保護器件202需要四個主動器件區域:1)FET 208、2)觸發式第三二極體218、3)位準移位二極體214,及4)位準移位二極體216。因而,根據本發明之教示,先前技術ESD保護器件202需要比單極性多閘極ESD保護器件302所需大之積體電路晶粒(未展示)上之一主動器件區域來達成相同ESD保護位準。
參考圖7、圖8及圖8A,其繪示根據本發明之另一特定實例性實施例之用於射頻(RF)埠之一雙極性多閘極肖特基空乏型FET ESD保護器件之一示意圖,以及用於在圖7中展示之ESD保護器件之一結構之一示意性平面視圖。一雙極性多閘極肖特基空乏型FET ESD保護器件702可用於保護一積體電路封裝(未展示)之電路706之控制信號及/或偏壓供應節點(接腳)。ESD保護器件702可包括:一第一HEMT器件308,其具有一汲極、一源極以及第一閘極(G1)及第二閘極(G2);第一二極體314及第二二極體316;第一閘極電阻器310及第二閘極電阻器312;一第二HEMT器件708,其具有一汲極、一源極及第一閘極(G1)及第二閘極(G2);第三二極體714及第四二極體716;第三閘極電阻器710及第四閘極電阻器712。ESD保護器件702可有利地與相關聯於高RF功率器件之RF埠一起使用。此ESD保護電路可在存在大正RF電壓擺幅及大負RF電壓擺幅之情況下使用。此雙極性多閘極FET ESD保護器件702之工作原理實質上類似於單極性多閘極ESD保護器件302之工作原理。元件708至716用作元件308至316之一鏡像。
雖然已參考本發明之實例性實施例來繪示、闡述及定義本發明之各實施例,但此等參考並非暗示限制本發明,且不應推斷出存在此限制。所揭示之標的物能夠在形式及功能上具有大量修改、變更及等效形式,熟習相關技術者將會聯想到此等修改、變更及等效形式並受益於本發明。本發明之所繪示及所闡述之實施例僅係實例,而並非係對本發明之範疇之窮盡性說明。
Claims (18)
- 一種靜電放電(ESD)保護器件,其包括:一第一場效應電晶體,其具有一汲極、至少兩個閘極及一源極,其中其該汲極經耦合至一電路之一節點以保護該電路免受一ESD事件;至少一第一二極體,其係耦合於該第一場效應電晶體之該源極與一共同節點之間;及一第一電阻器及一第二電阻器,其等經串聯耦合於該至少兩個閘極之一第一閘極及該共同節點之間,其中在該第一電阻器及該第二電阻器之間的一第一節點與該至少兩個閘極之一第二閘極耦合。
- 如請求項1之ESD保護器件,其中該共同節點係一電源供應共同點。
- 如請求項1之ESD保護器件,其進一步包括:一第二場效應電晶體,其具有一汲極、至少兩個閘極及一源極,其中其該汲極經耦合至一電源供應共同點;至少一第二二極體,其具有一陰極,該陰極耦合至該至少一第一二極體之一陰極;一第三電阻器及一第四電阻器,其等經串聯耦合於該第二場效應電晶體之一第一閘極及該共同節點之間,其中在該第三電阻器及該第四電阻器之間的一第二節點與該第二場效應電晶體之一第二閘極耦合。
- 如請求項1之ESD保護器件,其中該第一場效應電晶體之該至少兩個閘極中之一者或該第一及第二場效應電晶體之該至少兩個閘極中之一者係觸發閘極,且該至少兩個閘極中之另一者係放 電閘極。
- 如請求項1之ESD保護器件,其中該第一場效應電晶體係一空乏型場效應電晶體,或該第一及第二場效應電晶體係空乏型場效應電晶體。
- 如請求項1之ESD保護器件,其中該至少一第一二極體或該至少一第一二極體及該至少一第二二極體各係串聯連接在該第一或第二場效應電晶體之該源極與該共同節點之間的兩個二極體。
- 如請求項1之ESD保護器件,其中該電源供應共同點係耦合至一電接地。
- 如請求項5之ESD保護器件,其中該空乏型場效應電晶體係一高電子遷移率電晶體(HEMT)。
- 如請求項8之ESD保護器件,其中該HEMT係一假晶HEMT(pHEMT)。
- 如請求項8之ESD保護器件,其中該HEMT係一變質HEMT(mHEMT)。
- 如請求項8之ESD保護器件,其中該HEMT係一感應HEMT。
- 如請求項1之ESD保護器件,其中該第一場效應電晶體或該第一及第二場效應電晶體、該至少一第一二極體或該至少一第一二極體及該至少一第二二極體以及該第一及第二電阻器或該第一、第二、第三及第四電阻器係製作於一積體電路晶粒上且經耦合至該電路節點,該電路節點係耦合至該積體電路晶粒之一外部連接。
- 如請求項2之ESD保護器件,其中該第一場效應電晶體、該至少一第一二極體以及該第一及第二電阻器係製作於一積體電路晶粒上且經耦合至該電路節點,該電路節點係耦合至該積體電路晶粒之一外部連接,且其中該積體電路晶粒之該外部連接之一 功能係選自由以下各項組成之群組:一類比輸入、一數位輸入、一類比輸出、一數位輸出、一類比輸入/輸出、一數位輸入/輸出、一電源連接、一偏壓輸入及一外部補償電容器。
- 如請求項3之ESD保護器件,其中該第一及第二場效應電晶體、該至少一第一二極體及該至少一第二二極體,以及該第一、第二、第三及第四電阻器係製作於一積體電路晶粒上且經耦合至該電路節點,該電路節點係耦合至該積體電路晶粒之一外部連接,且其中該積體電路晶粒之該外部連接之一功能係選自由以下各項組成之群組:一類比輸入、一數位輸入、一類比輸出、一數位輸出、一類比輸入/輸出、一數位輸入/輸出、一電源連接、一偏壓輸入及一外部補償電容器。
- 如請求項2之ESD保護器件,其中該第一場效應電晶體、該至少一第一二極體以及該第一及第二電阻器係製作於一積體電路晶粒上且經耦合至該電路節點,該電路節點經耦合至該積體電路晶粒之一外部連接,且其中該積體電路晶粒之該外部連接之一功能包括一射頻信號輸入。
- 如請求項3之ESD保護器件,其中該第一及第二場效應電晶體、該至少一第一二極體及該至少一第二二極體以及該第一、第二、第三及第四電阻器係製作於一積體電路晶粒上且經耦合至該電路節點,該電路節點經耦合至該積體電路晶粒之一外部連接,且其中該積體電路晶粒之該外部連接之一功能包括一射頻信號輸入。
- 如請求項2之ESD保護器件,其中該第一場效應電晶體、該至少一第一二極體以及該第一及第二電阻器係製作於一積體電路晶粒上且經耦合至該電路節點,該電路節點經耦合至該積體電路晶粒之一外部連接,且其中該積體電路晶粒之該外部連接之一 功能包括一射頻信號輸出。
- 如請求項3之ESD保護器件,其中該第一及第二場效應電晶體、該至少一第一二極體及該至少一第二二極體以及該第一、第二、第三及第四電阻器係製作於一積體電路晶粒上且經耦合至該電路節點,該電路節點經耦合至該積體電路晶粒之一外部連接,且其中該積體電路晶粒之該外部連接之一功能包括一射頻信號輸出。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201361819252P | 2013-05-03 | 2013-05-03 | |
US61/819,252 | 2013-05-03 | ||
US14/267,185 US9431390B2 (en) | 2013-05-03 | 2014-05-01 | Compact electrostatic discharge (ESD) protection structure |
US14/267,185 | 2014-05-01 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201508894A TW201508894A (zh) | 2015-03-01 |
TWI631685B true TWI631685B (zh) | 2018-08-01 |
Family
ID=51841005
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW103115860A TWI631685B (zh) | 2013-05-03 | 2014-05-02 | 緊密靜電放電保護結構 |
Country Status (7)
Country | Link |
---|---|
US (2) | US9431390B2 (zh) |
EP (1) | EP2992555B1 (zh) |
JP (1) | JP6366687B2 (zh) |
KR (1) | KR102198021B1 (zh) |
CN (1) | CN105190887B (zh) |
TW (1) | TWI631685B (zh) |
WO (1) | WO2014179651A1 (zh) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9728532B2 (en) * | 2011-04-13 | 2017-08-08 | Qorvo Us, Inc. | Clamp based ESD protection circuits |
US9627883B2 (en) | 2011-04-13 | 2017-04-18 | Qorvo Us, Inc. | Multiple port RF switch ESD protection using single protection structure |
US9431390B2 (en) * | 2013-05-03 | 2016-08-30 | Microchip Technology Incorporated | Compact electrostatic discharge (ESD) protection structure |
KR20150048427A (ko) * | 2013-10-28 | 2015-05-07 | 에스케이하이닉스 주식회사 | 디스차지 회로 |
US10610326B2 (en) * | 2015-06-05 | 2020-04-07 | Cianna Medical, Inc. | Passive tags, and systems and methods for using them |
KR102364340B1 (ko) * | 2015-06-30 | 2022-02-17 | 엘지디스플레이 주식회사 | 표시장치 |
JP6597357B2 (ja) * | 2016-02-09 | 2019-10-30 | 三菱電機株式会社 | 保護ダイオード付き電界効果トランジスタ |
US10158029B2 (en) | 2016-02-23 | 2018-12-18 | Analog Devices, Inc. | Apparatus and methods for robust overstress protection in compound semiconductor circuit applications |
WO2017177074A1 (en) | 2016-04-06 | 2017-10-12 | Cianna Medical, Inc. | Reflector markers and systems and methods for identifying and locating them |
US20180026029A1 (en) * | 2016-07-21 | 2018-01-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated ESD Protection Circuit for GaN Based Device |
US10438940B2 (en) * | 2016-12-29 | 2019-10-08 | Nxp Usa, Inc. | ESD protection for depletion-mode devices |
WO2018175667A1 (en) | 2017-03-21 | 2018-09-27 | Cianna Medical, Inc. | Reflector markers and systems and methods for identifying and locating them |
US10475783B2 (en) * | 2017-10-13 | 2019-11-12 | Nxp B.V. | Electrostatic discharge protection apparatuses |
US10381828B1 (en) * | 2018-01-29 | 2019-08-13 | Dialog Semiconductor (Uk) Limited | Overvoltage protection of transistor devices |
US11883150B2 (en) | 2018-09-06 | 2024-01-30 | Cianna Medical, Inc. | Systems for identifying and locating reflectors using orthogonal sequences of reflector switching |
GB2580155A (en) * | 2018-12-21 | 2020-07-15 | Comet Ag | Radiofrequency power amplifier |
CN111756028B (zh) * | 2019-03-29 | 2022-07-01 | 北京小米移动软件有限公司 | 电子设备 |
CN114023738B (zh) * | 2019-05-15 | 2024-01-23 | 英诺赛科(珠海)科技有限公司 | 静电防护电路及电子装置 |
US11309435B2 (en) * | 2020-03-09 | 2022-04-19 | Globalfoundries U.S. Inc. | Bandgap reference circuit including vertically stacked active SOI devices |
US11764204B2 (en) * | 2020-06-18 | 2023-09-19 | Analog Devices, Inc. | Electrostatic discharge and overdrive protection circuitry |
CN117239685A (zh) * | 2022-06-08 | 2023-12-15 | 长鑫存储技术有限公司 | 静电保护结构、可控硅整流器和半导体存储器 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200812059A (en) * | 2006-08-23 | 2008-03-01 | Win Semiconductors Corp | On-chip ESD protection circuit using enhancement-mode HEMT/MESFET technology |
TW200908812A (en) * | 2007-04-19 | 2009-02-16 | Qualcomm Inc | Stacked ESD protection circuit having reduced trigger voltage |
TW201433036A (zh) * | 2013-02-15 | 2014-08-16 | Win Semiconductors Corp | 具有靜電保護元件之積體電路 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6826025B2 (en) * | 2002-05-20 | 2004-11-30 | International Business Machines Corporation | Method and apparatus for providing ESD protection and/or noise reduction in an integrated circuit |
US6835969B1 (en) * | 2003-06-26 | 2004-12-28 | Raytheon Company | Split-channel high electron mobility transistor (HEMT) device |
US6984853B2 (en) | 2004-02-26 | 2006-01-10 | Agilent Technologies, Inc | Integrated circuit with enhancement mode pseudomorphic high electron mobility transistors having on-chip electrostatic discharge protection |
JP2006165182A (ja) * | 2004-12-06 | 2006-06-22 | Toshiba Corp | 電界効果トランジスタ |
KR100818086B1 (ko) * | 2006-04-06 | 2008-03-31 | 주식회사 하이닉스반도체 | 정전기 방전 보호 회로 |
US7593204B1 (en) | 2006-06-06 | 2009-09-22 | Rf Micro Devices, Inc. | On-chip ESD protection circuit for radio frequency (RF) integrated circuits |
US8144441B2 (en) * | 2006-08-30 | 2012-03-27 | Triquint Semiconductor, Inc. | Electrostatic discharge protection circuit for compound semiconductor devices and circuits |
US7881029B1 (en) | 2008-07-07 | 2011-02-01 | Rf Micro Devices, Inc. | Depletion-mode field effect transistor based electrostatic discharge protection circuit |
US9171963B2 (en) | 2011-04-11 | 2015-10-27 | University Of Central Florida Research Foundation, Inc. | Electrostatic discharge shunting circuit |
US9728532B2 (en) | 2011-04-13 | 2017-08-08 | Qorvo Us, Inc. | Clamp based ESD protection circuits |
US8970998B2 (en) * | 2012-12-31 | 2015-03-03 | Win Semiconductors Corp. | Compound semiconductor ESD protection devices |
US9431390B2 (en) * | 2013-05-03 | 2016-08-30 | Microchip Technology Incorporated | Compact electrostatic discharge (ESD) protection structure |
-
2014
- 2014-05-01 US US14/267,185 patent/US9431390B2/en active Active
- 2014-05-02 WO PCT/US2014/036499 patent/WO2014179651A1/en active Application Filing
- 2014-05-02 JP JP2016512060A patent/JP6366687B2/ja active Active
- 2014-05-02 CN CN201480025014.7A patent/CN105190887B/zh active Active
- 2014-05-02 EP EP14728389.9A patent/EP2992555B1/en active Active
- 2014-05-02 TW TW103115860A patent/TWI631685B/zh active
- 2014-05-02 KR KR1020157031623A patent/KR102198021B1/ko active IP Right Grant
-
2016
- 2016-08-29 US US15/250,855 patent/US9685432B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200812059A (en) * | 2006-08-23 | 2008-03-01 | Win Semiconductors Corp | On-chip ESD protection circuit using enhancement-mode HEMT/MESFET technology |
TW200908812A (en) * | 2007-04-19 | 2009-02-16 | Qualcomm Inc | Stacked ESD protection circuit having reduced trigger voltage |
TW201433036A (zh) * | 2013-02-15 | 2014-08-16 | Win Semiconductors Corp | 具有靜電保護元件之積體電路 |
Also Published As
Publication number | Publication date |
---|---|
US9685432B2 (en) | 2017-06-20 |
JP6366687B2 (ja) | 2018-08-01 |
WO2014179651A1 (en) | 2014-11-06 |
US9431390B2 (en) | 2016-08-30 |
CN105190887A (zh) | 2015-12-23 |
CN105190887B (zh) | 2018-11-09 |
EP2992555B1 (en) | 2018-04-04 |
JP2016521008A (ja) | 2016-07-14 |
US20160372459A1 (en) | 2016-12-22 |
EP2992555A1 (en) | 2016-03-09 |
KR102198021B1 (ko) | 2021-01-05 |
TW201508894A (zh) | 2015-03-01 |
KR20160004290A (ko) | 2016-01-12 |
US20140327048A1 (en) | 2014-11-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI631685B (zh) | 緊密靜電放電保護結構 | |
KR102039872B1 (ko) | GaAs계 또는 GaN계의 보호 다이오드 부착 전계 효과 트랜지스터 | |
US8964342B2 (en) | Compound semiconductor ESD protection devices | |
JP6201422B2 (ja) | 半導体装置 | |
US10438940B2 (en) | ESD protection for depletion-mode devices | |
US7881030B1 (en) | Enhancement-mode field effect transistor based electrostatic discharge protection circuit | |
WO2006041087A1 (ja) | 高周波集積回路 | |
US9064704B2 (en) | Integrated circuits with ESD protection devices | |
US9780738B2 (en) | Semiconductor device | |
CN111192872A (zh) | 集成在氮化镓半导体装置上的嵌位电路及相关半导体装置 | |
JP4535668B2 (ja) | 半導体装置 | |
US8970998B2 (en) | Compound semiconductor ESD protection devices | |
US20050285143A1 (en) | Semiconductor device | |
US8854112B2 (en) | FET drive circuit and FET module | |
JP2005340550A (ja) | 半導体装置 | |
CN107293537B (zh) | 静电放电保护装置、存储器元件及静电放电保护方法 | |
US8743518B1 (en) | Protection circuit | |
JP2016174240A (ja) | 半導体スイッチ | |
JP5147169B2 (ja) | スイッチ回路装置 | |
TW200812059A (en) | On-chip ESD protection circuit using enhancement-mode HEMT/MESFET technology | |
CN117121156A (zh) | 用于控制半导体衬底的电压的电路和方法 |