200812059 九、發明說明： 【發明所屬之技術領域】 • 本發明係一種關於半導體電子電路中靜電放電（ESD) 的防護電路’特別是關於三五族化合物半導體晶片内靜電 放電防邊電路’利用增強型（enhancement mode)高電子遷移 率電晶體（HEMT)/金屬半導體場效電晶體（MESFET)分流靜 電放電供以保護主要電路免於靜電放電的損壞。 【先前技術】 •根據靜電放電產生的原因與對積體電路放電的方式可分 為四類靜電放電核式·人體放電模式（||uman-B〇dy Model，HBM)、機器放電模式（Machine Mode卜 MM)、元 件充電模式（Charged-Device Model，CDM)與電場感應模 式（Field-Induced Model，FIM);當靜電放電發生的時候， 產生的高壓與高電流會對積體電路造成嚴重的破壞，因此 在主要電路與外界的接觸上需要靜電放電（ESD)防護電 馨路。傳統的靜電放電防護電路採用大量二極體串聯來吸收 放電，不只佔去不少空間，因其增加的寄生電阻（parasitic impedance)與寄生電容（parasitic capacitance)也會對所保護 的電路造成不少的影響，尤其是在低訊號的射頻(RF)元件 中，傳統的靜電放電防護電路的寄生效應（parasitic effect) 會破壞射頻元件的性能，例如減低射頻元件的功率放大倍 率、降低射頻應用頻率以及產生雜訊等等。 一種特別用於射頻元件中的靜電放電防護電路由 Maoyou Sun於美國專利申請號：1〇/255,787所揭示，該電 5 200812059 • 路乃是利用與被保護的電路並聯之電晶體來分流靜電放電 的突波，由於電晶體具有高電流低壓差的特性，因此能在 .發生靜電放電的瞬間將放電經由電晶體快速地移除；除此 之外，電晶體還具有開關（switch)的功能，若將電晶體與 二極體組串並聯，並將電晶體閘極（gate)與二極體組串連 接，透過變動的二極體的數目便可以變動電晶體的開關電 壓，使得該靜電放電防護電路不會因正常使用中的電壓而 打開電晶體造成短路。該靜電放電防護電路不需要大量串 ⑩接二極體，取而代之的是用來觸發電晶體的少量二極體串 以及與之並聯的電晶體，因大量二極體串產生的寄生效應 (parasitic effect)便可以減少，同時可以得到較快速的 放電分流效果，適合用於需要維持高品質訊號的射頻元件。 對於射頻元件中常用的功率放大器（PA)，同樣也需要寄 生效應（parasitic effect)低的靜電放電防護電路；同時， 若該靜電放電防護電路可以與被保護的電路整合 ⑩（integrate)在同一晶片上’對於降低成本、減低功率的耗 損以及壓縮元件尺寸將是一大利基。尤其是用於射頻元件 中的三五族化合物半導體的功率放大器（PA)，常使用異質 接面雙極電晶體（HBT)來達到增益的效果。若上述孫博士 (Dr· Sun)於申請號1〇/255,787所揭示的電晶體部分改成異 質接面雙極電晶體（HBT)則可以將靜電放電防護電路直接 做在功率放大器的晶片上；如YinMa與Diamond Bar於美 國專利申請號：10/501，651所揭示的達靈頓對（Dari ingt〇n pair)靜電放電防護電路’即是利用兩個異質接面雙極電晶 200812059 ^ 體（HBT)組合而成的達靈頓對（Darlington pair)來承接大 量電流的放電，一樣地也是利用二極體串來觸發分流；對 ―於達靈頓對（Darlington pair)形成的寄生效應（parasitic effect)，馬博士（Dr· Ma)另外加上一個與達靈頓對 (Darlington pair)串接的二極體來減低其寄生電容。 上述的功率放大器晶片内靜電放電防護電路，乃是因應 功率放大器常用的異質接面雙極電晶體（HBT)來設計晶片 内靜電放電防護電路；而射頻元件中常應用的電晶體不只 參異質接面雙極電晶體（HBT)，偽型態高電子遷移率電晶體 (pseudo morphic- pHEMT)或金屬半導體場效電晶體 (MESFET)也因其有低雜訊或低製作成本的優點，在市場上 佔有一定的地位。面對與異質接面雙極電晶體（HBT)磊晶 (epitaxy)結構完全不同的偽型態高電子遷移率電晶體 (pHEMT)或金屬半導體場效電晶體（MESFET)時，晶片内的靜 電放電防護電路便需要改成以偽型態高電子遷移率電晶體 (pHEMT)或金屬半導體場效電晶體（MESFET)為主的防護電 路；然而空毛型（depletion mode)偽型態高電子遷移率電 晶體（pHEf)或金屬半導體場效電晶體（mesfet)*像異質 接面雙極迅晶體⑽τ)或雙極接面電晶體⑻一樣是常閉 (normal名電晶體，反而是常開（耐〇η)電晶 2恭時便可以啟動的狀態下，無法利用二極體串來 :二：：後;對此’本發明利用增強型(enhance— —e) 偽型態尚電子遷移輋雷曰雜广ττ 日日_ ρΗ贿Τ)或金屬半導體場效電 日日體CMESFET)的常閉特性來 H代靜電放電防護電路中電晶 7 200812059 體的位置。 因此，本發明揭示的利用增強型（enhancement mode) .偽型態高電子遷移率電晶體（pHEMT)或金屬半導體場效電 ，晶體（MESFET)的靜電放電防護電路可以與被保護的電路整 合在同一晶片内；同時，本發明另揭示的雙閘極設計，可 在不浪費電路空間下達到寄生電容縮減的目的，以維持被 保護的主要電路性能，例如：增益性、線性化與頻寬。 【發明内容】 _ 本發明之基本結構為並聯一觸發二極體串與分流裝置， 在超出正常使用電壓之高壓突波事件發生時，供以分流高 壓突波以保護主要電路不受侵害；在以高電子遷移率電晶 體/金屬半導體場效電晶體（HEMTs/MESFET)為主的晶片 上，該分流裝置同樣使用高電子遷移率電晶體/金屬半導體 場效電晶體（HEMTs/MESFET)使該防護電路得以作為晶片 内之防護電路，以達到節省晶片空間與製作成本之目的。 0為了能使分流裝置得以被觸發，本發明利用具有常閉 (normally off)性質之增強型（enhancement mode)高電子遷 移率電晶體/金屬半導體場效電晶體（HEMTs/MESFET)為分 流裝置；另外，在不浪費晶片内空間條件下，本發明採雙 閘極設計以期達到縮減防護電路中寄生電容之目的，供以 維持被保護電路之精密效能。 為達上述發明之目的，本發明所設之利用增強型 (enhancement mode)高電子遷移率電晶體（HEMT)/金屬半導 體場效電晶體（MESFET)之晶片内靜電放電（ESD)防護電 8 200812059 路，包括一個内部電路端（pad point)、一個接地端（gr〇und point) —個連接該内部電路端與該接地端並與該内部電路 . 端座於同一晶片基板上之晶片内二極體串（diode string)，以 及至少一個與該二極體串並聯之連接該内部電路端與該接 地端並與該内部電路端座於同一晶片基板上之晶片内增強 型高電子遷移率電晶體/金屬半導體場效電晶體。該二極體 串（diode string)供以觸發靜電放電突波之分流，而該增強型 高電子遷移率電晶體/金屬半導體場效電晶體之閘極銜接 _該二極體串之陰極端，供以接受二極體串之觸發以承接靜 電放電之分流。 為了讓本發明上述以及其他目的、特徵、和優點能更 明顯易懂，以下配合圖式以及較佳實施例以說明本發明。 【實施方式】 第1圖係說明本發明靜電放電（ESD)防護電路1之概念 圖，該防護電路1包括了一個供以銜接内部電路的内部電 路端11〇、接地端1如、一觸發二極體串121以及與觸發二 鲁極體串121 ϋ聯之靜電放電分流裝置122。 當靜電放電事件120發生時（如第1 -1圖所不）’該防邊 電路1中的靜電放電分流裝置122可將該靜電放電產生的 高壓高電流順利的分流到接地端1°然而’内部電路知 110在正常使用下是有電壓變化的，因此該靜電放電防護電 路必須要能分別什麼時候是需要分流’而什麼時候是正常 使用電壓不需啟動分流；如第2圖所述之觸發二極體串121 即供以分辨高壓突波來襲事件，當高壓突波發生時，位於 9 200812059 内部電路端110與接地端130之間的電壓差即大於該觸發 二極體串121的臨界順偏壓降（Vth)，使得該觸發二極體串 • 121被打通，銜接靜電放電分流裝置122閘極221之端點電 .壓與接地端開始有了壓差，因而啟動了該靜電放電分流裝 置122，内部電路端110之高壓突波得以分流至接地端 130。在本實施例中，所述的靜電放電分流裝置122係為增 強型偽型態高電子遷移率電晶體/金屬半導體場效電晶體 (E-mode pHEMTs/MESFET)。 ® 在精簡空間與成本的條件下，該觸發用二極體之數目以 能在正常電壓使用下未觸發分流之最小數目為原則，例 如：觸發用二極體之數目N =正常電壓Vpad/臨界順偏壓 降Vth ;另外，如前所述，在以偽型態高電子遷移率電晶 體/金屬半導體場效電晶體（pHEMTs/MESFET)為主的晶片 上，該靜電放電分流裝置122若為晶片内設計，則應使用 增強型（enhancement mode)的偽型態高電子遷移率電晶體/ ⑩金屬半導體場效電晶體（pHEMTs/MESFET)，乃是因其不同 於空乏型（depletion mode)偽型態高電子遷移率電晶體/金 屬半導體場效電晶體（pHEMTs/MESFET)之常閉（normally off)性質。 第3圖係表示該靜電放電防護電路1對内部電路產生寄 生電容（parasitic capacitance)之來源，該寄生電容來源有 二··一是來自觸發二極體串121 ;二是來自增強型 (enhancement mode)偽型態高電子遷移率電晶體/金屬半導 體場效電晶體（pHEMTs/MESFET)。由於觸發二極體串121 200812059 產生之寄生電容Ct相對於增強型（enhancement mode)偽型 態高電子遷移率電晶體/金屬半導體場效電晶體 .(pHEMTs/MESFET)產生之寄生電容Ce要來得小，總寄生電 容Ctotall約略等於來自於增強型（enhancement mode)偽型態 高電子遷移率電晶體/金屬半導體場效電晶體 (pHEMTs/MESFET)之寄生電容Ce。如前所述，在射頻元件 中靜電放電防護電路中產生之寄生電容，會對欲保護的電 路性能造成一定的影響，因此，良好的防護電路其寄生效 _應是越小越好；串接增強型（enhancement mode)偽型態高電 子遷移率電晶體/金屬半導體場效電晶體（pHEMTs/MESFET) 串可順利縮減該寄生電容。如第4圖所示，串接的第一、 第二增強型（enhancement mode)偽型態高電子遷移率電晶 體/金屬半導體場效電晶體（pHEMTs/MESFET)之寄生電容 Cel、Ce2可使總寄生電容Ct()tal2變為原來總寄生電容CtDtall 之一半；然而串接所需的空間與成本係成倍數增加，雖然 |減低了寄生電容，卻使晶片所需之空間變大，就應用上來 說，晶片内設計之優勢便也減少了。 本發明中另一個重要突破便如第5圖所示，維持原有增 強型（enhancement mode)偽型態高電子遷移率電晶體/金屬 半導體場效電晶體（PHEMTs/MESFET)之空間大小，而其閘 極採用雙閘極設計，使雙閘極（dual gate)增強型偽型態高電 子遷移率電晶體/金屬半導體場效電晶體除其中一閘極銜 接於二極體串121之終端陰極端供以接受該二極體串121 之觸發外，另一閘極銜接於增強型偽型態高電子遷移率電 η 200812059 • 晶體/金屬半導體場效電晶體之汲極，以取代原有增強型 (enhancement mode)偽型態高電子遷移率電晶體/金屬半導 . 體場效電晶體（pHEMTs/MESFET)串接之設計，在不浪費空 間的條件下達到縮減寄生電容的結果。而如第6圖所示， 其為上述雙閘極設計之各種不同樣態，乃為增強型 (enhancement mode)偽型態高電子遷移率電晶體/金屬半導 體場效電晶體(pHEMTs/MESFET)其中一閘極仍連接於觸發 二極體串121供以被觸發，而另一閘極則是與内部電路端 ⑩ 相連、或是與該觸發二極體串121之間任一結點相連，以 求達到不同縮減寄生電容，與達到需要不同觸發電壓之電 路設計之要求。 第7圖即顯示該防護電路其中一例之佈局結果，分別顯 示觸發二極體串121與匹配用電阻720之位置，藉由該電 阻720以調整内部電路匹配之阻抗；同時，該增強型 (enhancement mode)偽型態高電子遷移率電晶體/金屬半導 體場效電晶體（pHEMTs/MESFET)以多指形（multi-finger)閘 極設計對稱交叉分佈於觸發二極體串121之兩侧，而指形 數目則由所需之裝置大小L與指狀閘極的寬度W決定，例 如··裝置大小1 mm = 4 (指形數目）X 125 μιη(閘極寬度）X 2(對稱兩侧設計）、或是裝置大小1mm = 8 (指形數目）X 62·5 μπι(閘極寬度）X 2(對稱兩側設計）。 實施時’上述二極體串121的方向與數目應使在正常使 用期間之最高電壓下，該二極體串121為不導通的狀態。 【圖式簡單說明】 12 200812059 第1圖係為本發明靜電放電（esd)防護電路之概念圖。 弟1 -1圖係為靜電放電事件發生時之示意圖。 第2圖係為本發明靜電放電（ESD)防護電路之各項元件配 置實施例圖。 第3圖係表示本發明靜電放電（ESD)防護電路對内部電路 產生寄生電容（parasitic capacitance)之來源。 第4圖係表示本發明靜電放電（ESD)防護電路在串接增強 型（enhancement mode)偽型態高電子遷移率電晶體/ 金屬半導體場效電晶體(pHEMTs/MESFET)下之寄 生電容。 第5圖係表示本發明靜電放電（esd)防護電路在維持原有 空間大小下其雙閘極電路實施例圖。 第6圖係表示本發明靜電放電（ESD)防護電路不同雙閉極 之閘極接點電路實施例圖。 第7圖係顯示本發明靜電放電（ESD)防護電路其中—例之 佈局結果。 【主要元件符號說明】 110 :内部電路端 120 :靜電放電事件 121 :觸發二極體串 122 :靜電放電分流裝置 130 :接地端 221 :分流裝置閘極200812059 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a protection circuit for electrostatic discharge (ESD) in a semiconductor electronic circuit, particularly regarding the use of an electrostatic discharge anti-edge circuit in a three-five-group compound semiconductor wafer. An enhancement mode high electron mobility transistor (HEMT)/metal semiconductor field effect transistor (MESFET) shunt electrostatic discharge to protect the main circuit from electrostatic discharge damage. [Prior Art] • According to the cause of electrostatic discharge and the way of discharging the integrated circuit, it can be divided into four types of electrostatic discharge nuclear type, human discharge mode (||uman-B〇dy Model, HBM), machine discharge mode (Machine) Mode MM), Charged-Device Model (CDM) and Field-Induced Model (FIM); when electrostatic discharge occurs, the high voltage and high current generated will cause serious damage to the integrated circuit. Destruction, therefore, electrostatic discharge (ESD) protection is required on the contact of the main circuit with the outside world. The traditional ESD protection circuit uses a large number of diodes in series to absorb the discharge, which not only takes up a lot of space, but also increases the parasitic impedance and parasitic capacitance. The effects, especially in low-signal radio frequency (RF) components, the parasitic effects of conventional ESD protection circuits can degrade the performance of RF components, such as reducing the power amplification of RF components, reducing the frequency of RF applications, and Generate noise and so on. An electrostatic discharge protection circuit, particularly for use in a radio frequency device, is disclosed in U.S. Patent Application Serial No. 1/255,787, the entire disclosure of which is incorporated herein by reference. The spurt, because the transistor has the characteristics of high current and low voltage difference, can quickly remove the discharge through the transistor at the moment of electrostatic discharge; in addition, the transistor also has a switch function. If the transistor is connected in series with the diode group, and the gate of the transistor is connected to the diode string, the switching voltage of the transistor can be changed by the number of the changed diodes, so that the electrostatic discharge The protection circuit does not open the transistor due to the voltage in normal use, causing a short circuit. The ESD protection circuit does not require a large number of serial 10-connected diodes. Instead, a small number of diode strings for triggering the transistor and a transistor connected in parallel with it, parasitic effect due to a large number of diode strings (parasitic effect) It can be reduced, and a faster discharge shunt can be obtained, which is suitable for RF components that need to maintain high quality signals. For power amplifiers (PAs) commonly used in RF components, an electrostatic discharge protection circuit with a low parasitic effect is also required. Meanwhile, if the ESD protection circuit can be integrated with the protected circuit, it is integrated on the same wafer. The above will be a big niche for reducing costs, reducing power consumption and compressing component size. In particular, power amplifiers (PAs) for tri-five compound semiconductors used in RF components often use a heterojunction bipolar transistor (HBT) to achieve gain. If the above-mentioned transistor part of Dr. Sun (Dr. Sun) is changed to a heterojunction bipolar transistor (HBT) as disclosed in the application No. 1/255,787, the electrostatic discharge protection circuit can be directly applied to the wafer of the power amplifier; For example, the Dari ingt〇n pair electrostatic discharge protection circuit disclosed in US Patent Application No. 10/501,651 uses two heterojunction bipolar electro-crystals 200812059 ^ body The (HBT) combination of the Darlington pair to withstand the discharge of a large amount of current, the same is also the use of a diode string to trigger the shunt; the parasitic effect on the Darlington pair ( Parasitic effect), Dr. Ma (Dr. Ma) adds a diode connected in series with the Darlington pair to reduce its parasitic capacitance. The above-mentioned electrostatic discharge protection circuit of the power amplifier chip is designed to design an electrostatic discharge protection circuit in the wafer in response to a heterojunction bipolar transistor (HBT) commonly used in a power amplifier; and a transistor commonly used in a radio frequency component is not only a heterojunction junction. Bipolar transistors (HBT), pseudo-morphic-pHEMT or metal-semiconductor field-effect transistors (MESFETs) are also on the market due to their low noise or low manufacturing cost. Occupy a certain position. In the case of a pseudo-type high electron mobility transistor (pHEMT) or a metal-semiconductor field-effect transistor (MESFET) that is completely different from a heterojunction bipolar transistor (HBT) epitaxy structure, static electricity in the wafer The discharge protection circuit needs to be changed to a protection circuit based on pseudo-type high electron mobility transistor (pHEMT) or metal semiconductor field effect transistor (MESFET); however, depletion mode pseudo-type high electron mobility Rate transistor (pHEf) or metal semiconductor field effect transistor (mesfet) * like a heterojunction bipolar crystal (10) τ) or a bipolar junction transistor (8) is normally closed (normal name transistor, but normally open ( 〇 ) ) 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电The normally closed characteristic of the Thunder 广 τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ Therefore, the present invention discloses an electrostatic discharge protection circuit that can be integrated with a protected circuit using an enhancement mode, a pseudo-type high electron mobility transistor (pHEMT) or a metal-semiconductor field effect transistor. At the same time, the dual gate design disclosed in the present invention can achieve the purpose of parasitic capacitance reduction without wasting circuit space to maintain the main circuit performance to be protected, such as gain, linearization and bandwidth. SUMMARY OF THE INVENTION The basic structure of the present invention is a parallel-trigger diode string and a shunt device. When a high-voltage surge event exceeding the normal use voltage occurs, a high-voltage surge is applied to protect the main circuit from damage; On a wafer dominated by high electron mobility transistor/metal semiconductor field effect transistors (HEMTs/MESFETs), the shunt device also uses high electron mobility transistor/metal semiconductor field effect transistors (HEMTs/MESFET) to The protection circuit can be used as a protection circuit in the wafer to save wafer space and manufacturing cost. In order to enable the shunt device to be triggered, the present invention utilizes an enhancement mode high electron mobility transistor/metal semiconductor field effect transistor (HEMTs/MESFET) having a normally off property as a shunt device; In addition, the present invention adopts a double gate design to reduce the parasitic capacitance in the protection circuit in order to maintain the precision performance of the protected circuit without wasting the intra-wafer space. For the purpose of the above invention, the present invention provides an intra-system electrostatic discharge (ESD) protection power using an enhancement mode high electron mobility transistor (HEMT)/metal semiconductor field effect transistor (MESFET) 2008 20080 The circuit includes an internal circuit point (pad point) and a ground terminal (gr〇und point) - an intra-wafer diode connected to the internal circuit end and the ground terminal and the internal circuit. a diode string, and at least one intra-wafer enhanced high electron mobility transistor connected in parallel with the diode in series with the internal circuit end and the ground end and the internal circuit end on the same wafer substrate / Metal semiconductor field effect transistor. The diode string is provided to trigger a shunt of the electrostatic discharge surge, and the gate of the enhanced high electron mobility transistor/metal semiconductor field effect transistor is connected to the cathode end of the diode string. To accept the trigger of the diode string to take over the shunt of the electrostatic discharge. The above and other objects, features, and advantages of the invention will be apparent from [Embodiment] FIG. 1 is a conceptual diagram illustrating an electrostatic discharge (ESD) protection circuit 1 of the present invention. The protection circuit 1 includes an internal circuit terminal 11 for connecting an internal circuit, a ground terminal 1 such as a trigger 2 The polar body string 121 and the electrostatic discharge shunt device 122 coupled to the triggering diode diode string 121. When the electrostatic discharge event 120 occurs (as shown in Figure 1-1), the electrostatic discharge shunt device 122 in the anti-edge circuit 1 can smoothly shunt the high-voltage and high-current generated by the electrostatic discharge to the ground terminal 1°. The internal circuit knows that 110 has a voltage change under normal use, so the ESD protection circuit must be able to separately shunt when and when it is normal to use the voltage without starting the shunt; as shown in Figure 2 The diode string 121 is provided to distinguish the high voltage surge event. When a high voltage surge occurs, the voltage difference between the internal circuit terminal 110 and the ground terminal 130 at 9 200812059 is greater than the critical value of the trigger diode string 121. The bias voltage drop (Vth) causes the trigger diode string 121 to be turned on, and the end point of the gate 221 of the electrostatic discharge shunt device 122 is connected. The voltage and the ground end begin to have a voltage difference, thereby starting the electrostatic discharge. The shunt device 122, the high voltage surge of the internal circuit terminal 110 is shunted to the ground terminal 130. In the present embodiment, the electrostatic discharge shunt device 122 is an enhanced pseudo-type high electron mobility transistor/metal-semiconductor field effect transistor (E-mode pHEMTs/MESFET). ® In the case of reduced space and cost, the number of diodes used for triggering is based on the minimum number of untriggered shunts under normal voltage usage. For example, the number of triggering diodes N = normal voltage Vpad / critical The forward bias drops Vth; in addition, as described above, on the wafer mainly based on the pseudo-type high electron mobility transistor/metal-semiconductor field effect transistor (pHEMTs/MESFET), the electrostatic discharge shunt device 122 is For in-wafer design, an excitation mode high-electron mobility mobility transistor/10 metal-semiconductor field-effect transistor (pHEMTs/MESFET) should be used because it is different from the depletion mode pseudo- The normally off nature of the type high electron mobility transistor/metal semiconductor field effect transistor (pHEMTs/MESFET). Figure 3 is a diagram showing the source of the parasitic capacitance generated by the ESD protection circuit 1 to the internal circuit. The source of the parasitic capacitance is from the trigger diode string 121; the second is from the enhancement mode (enhancement mode). Pseudotype high electron mobility transistor/metal semiconductor field effect transistor (pHEMTs/MESFET). The parasitic capacitance Ct generated by the trigger diode string 121200812059 is derived from the parasitic capacitance Ce generated by the enhancement mode high-electron mobility transistor/metal-semiconductor field-effect transistor (pHEMTs/MESFET). Small, the total parasitic capacitance Ctotall is approximately equal to the parasitic capacitance Ce from the enhancement mode high electron mobility transistor/metal semiconductor field effect transistor (pHEMTs/MESFET). As mentioned above, the parasitic capacitance generated in the ESD protection circuit in the RF component will have a certain impact on the performance of the circuit to be protected. Therefore, the parasitic effect of a good protection circuit should be as small as possible; The enhancement mode of the high-electron mobility mobility transistor/metal-semiconductor field-effect transistor (pHEMTs/MESFET) string can smoothly reduce the parasitic capacitance. As shown in FIG. 4, the parasitic capacitances Cel and Ce2 of the first and second enhancement mode high-electron mobility transistor/metal-semiconductor field-effect transistor (pHEMTs/MESFET) can be connected in series. The total parasitic capacitance Ct() tal2 becomes half of the original total parasitic capacitance CtDtall; however, the space and cost required for the series connection are multiplied, although the parasitic capacitance is reduced, the space required for the wafer is increased, and the application is applied. In general, the advantages of in-wafer design are also reduced. Another important breakthrough in the present invention is to maintain the spatial size of the original enhancement mode high-electron mobility transistor/metal-semiconductor field-effect transistor (PHEMTs/MESFET) as shown in FIG. The gate adopts a double gate design, so that the dual gate enhanced pseudo-type high electron mobility transistor/metal semiconductor field effect transistor has one gate connected to the terminal of the diode string 121. Extremely for triggering the trigger of the diode string 121, the other gate is connected to the enhanced pseudo-type high electron mobility η 200812059 • The base of the crystal/metal-semiconductor field-effect transistor to replace the original enhancement Enhancement mode High-electron mobility mobility transistor/metal semi-conductor. The field-effect transistor (pHEMTs/MESFET) is designed in series to achieve the result of reducing parasitic capacitance without wasting space. As shown in Fig. 6, it is a different mode of the above double gate design, which is an enhancement mode pseudo-type high electron mobility transistor/metal semiconductor field effect transistor (pHEMTs/MESFET). One of the gates is still connected to the trigger diode string 121 for being triggered, and the other gate is connected to the internal circuit terminal 10 or to any node between the trigger diode strings 121. In order to achieve different reduction of parasitic capacitance, and to meet the requirements of circuit design that requires different trigger voltages. FIG. 7 shows the layout result of one example of the protection circuit, respectively showing the position of the trigger diode string 121 and the matching resistor 720, and the resistor 720 is used to adjust the impedance of the internal circuit matching; meanwhile, the enhancement type (enhancement) Mode) The pseudo-type high electron mobility transistor/metal-semiconductor field effect transistor (pHEMTs/MESFET) is symmetrically cross-distributed on both sides of the trigger diode string 121 in a multi-finger gate design. The number of fingers is determined by the required device size L and the width W of the finger gate, for example, device size 1 mm = 4 (number of fingers) X 125 μιη (gate width) X 2 (symmetric side design ), or device size 1mm = 8 (number of fingers) X 62·5 μπι (gate width) X 2 (symmetrical design on both sides). In the implementation, the direction and number of the above-mentioned diode strings 121 are such that the diode strings 121 are in a non-conducting state at the highest voltage during normal use. [Simple description of the diagram] 12 200812059 The first diagram is a conceptual diagram of the electrostatic discharge (esd) protection circuit of the present invention. The brother 1-1 diagram is a schematic diagram of the occurrence of an electrostatic discharge event. Fig. 2 is a view showing the arrangement of various components of the electrostatic discharge (ESD) protection circuit of the present invention. Figure 3 is a diagram showing the source of the parasitic capacitance of the internal circuit of the electrostatic discharge (ESD) protection circuit of the present invention. Figure 4 is a graph showing the parasitic capacitance of the electrostatic discharge (ESD) protection circuit of the present invention in a series mode of the pseudo mode high electron mobility transistor/metal semiconductor field effect transistor (pHEMTs/MESFET). Fig. 5 is a view showing an embodiment of the double gate circuit of the electrostatic discharge (esd) protection circuit of the present invention while maintaining the original space. Fig. 6 is a view showing an embodiment of a gate contact circuit of different double closed electrodes of the electrostatic discharge (ESD) protection circuit of the present invention. Fig. 7 is a view showing the layout results of the electrostatic discharge (ESD) protection circuit of the present invention. [Main component symbol description] 110: Internal circuit terminal 120: Electrostatic discharge event 121: Trigger diode string 122: Electrostatic discharge shunt device 130: Ground terminal 221: Shunt device gate
Ct:觸發二極體串之寄生電容 13 200812059Ct: Triggering the parasitic capacitance of the diode string 13 200812059
Ce :增強型（enhancement mode)偽型態高電子遷移率電晶體 /金屬半導體場效電晶體（pHEMTs/MESFET)之寄生電容 Ctotal2 ·總寄生電容 cei :第一增強型（enhancement mode)偽型態高電子遷移率 電晶體/金屬半導體場效電晶體（pHEMTs/MESFET)之寄 生電容Ce: enhancement mode parasitic capacitance of high electron mobility transistor/metal semiconductor field effect transistor (pHEMTs/MESFET) Ctotal2 · total parasitic capacitance cei: first enhancement mode pseudotype Parasitic capacitance of high electron mobility transistor/metal semiconductor field effect transistor (pHEMTs/MESFET)
Ce2 :第二增強型（enhancement mode)偽型態高電子遷移率 電晶體/金屬半導體場效電晶體（pHEMTs/MESFET)之寄 生電容Ce2: second enhancement mode pseudotype high electron mobility parasitic capacitance of transistor/metal semiconductor field effect transistor (pHEMTs/MESFET)
Ct〇tal2 :總寄生電容 720 :匹配用電阻 L :襞置大小 W:指狀閘極的寬度Ct〇tal2 : Total parasitic capacitance 720 : Matching resistance L : Setting size W: Width of finger gate