TWI628796B - 藉由層轉移之在反向極性基板上的高電子遷移率電晶體製程 - Google Patents
藉由層轉移之在反向極性基板上的高電子遷移率電晶體製程 Download PDFInfo
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- TWI628796B TWI628796B TW104114132A TW104114132A TWI628796B TW I628796 B TWI628796 B TW I628796B TW 104114132 A TW104114132 A TW 104114132A TW 104114132 A TW104114132 A TW 104114132A TW I628796 B TWI628796 B TW I628796B
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- semiconductor layer
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- barrier layer
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Classifications
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7781—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
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Abstract
一種方法,包括在犧牲基板上的極性複合半導體層上形成屏障層,將該犧牲基板耦接到載體基板,用以形成複合結構,其中該屏障層係設置在該極性複合半導體層與該載體基板之間,將該犧牲基板從該複合結構分離,用以暴露該極性複合半導體層,以及形成至少一個電路裝置。一種設備,包括:屏障層,其在基板上;電晶體裝置,其在該屏障層上;極性複合半導體層,其設置在該屏障層和該電晶體裝置之間,該極性複合半導體層包括二維電子氣體於其中。
Description
複合半導體裝置。
複合半導體裝置被視為以矽為基礎的裝置之有前景的替代或互補。複合半導體可以一般地描述為二元或三元III-V族半導體材料。III-V族分別引用表示在元素週期表的XIII族和XV族。III族和V族符號引用前國際純化學和應用化學聯合會(IUPAC)編號。
二元複合半導體如氮化鎵具有纖鋅礦晶體結構和晶體極性。氮化鎵高電子遷移率電晶體(HEMT)被用於無線基礎設施應用。氮化鎵基體金屬氧化物半導體場效電晶體(MOSFET)和金屬半導體場效電晶體(MESFET)也提供在高功率電子裝置的優點。
異質整合方案通常關於不同的半導體材料之整合,以產生虛擬基板。半導體層的層轉移至基板是一種
有前景的用以產生虛擬基板之方法,因為晶格不匹配材料之間可以避免相對厚的緩衝層。對於氮化鎵的層轉移的可行性而言,氮化鎵製造方案往往喜好某些晶體極性,即正或+c表面極性。對於將極性複合半導體層如按照這種方案製造的氮化鎵層轉移的努力傾向於導致具有+c極性表面的半導體層可用於裝置形成。
100‧‧‧結構
110‧‧‧犧牲基板
120‧‧‧極性複合半導體層
125‧‧‧二維電子氣體層
130‧‧‧屏障層
135‧‧‧穿孔層
140‧‧‧載體基板
150‧‧‧電晶體
155‧‧‧閘極電極
160‧‧‧源極區
165‧‧‧汲極區
170‧‧‧閘極介電層
200‧‧‧中介層
202‧‧‧第一基板
204‧‧‧第二基板
206‧‧‧球閘陣列(BGA)
208‧‧‧金屬互連
210‧‧‧通孔
212‧‧‧穿透矽通孔(TSV)
214‧‧‧嵌入式裝置
300‧‧‧計算裝置
302‧‧‧積體電路晶粒
304‧‧‧處理器
306‧‧‧晶粒上記憶體
308‧‧‧通訊晶片
310‧‧‧揮發性記憶體
312‧‧‧非揮發性記憶體
314‧‧‧圖形處理單元
316‧‧‧數位信號處理器
320‧‧‧晶片組
322‧‧‧天線
324‧‧‧觸控螢幕顯示器
326‧‧‧觸控式螢幕控制器
328‧‧‧電池
330‧‧‧羅盤
332‧‧‧動作感測器
334‧‧‧揚聲器
336‧‧‧照相機
338‧‧‧輸入裝置
340‧‧‧大容量儲存裝置
342‧‧‧加密處理器
344‧‧‧全球定位系統
圖1顯示在模板或犧牲基板上的極性半導體材料層的橫截面側視圖。
圖2顯示在極性半導體層上引入屏障層之後圖1的結構。
圖3顯示在結構的反轉和其連接到載體基板以形成複合結構之後圖2的結構。
圖4顯示在極性半導體層中之穿孔層的複合結構之分離或分裂之後圖3的複合結構。
圖5顯示在結構上的極性複合半導體層的厚度減小之後圖4的結構。
圖6顯示引入在結構上的裝置之後圖5的結構。
圖7是實現一個或多個實施例之中介層。
圖8是根據實施例建立的計算裝置。
說明一種製造積體電路裝置的方法,特別
是,藉由層轉移之包括高電子遷移率電晶體(HEMT)的積體電路裝置。在一種觀點中,該方法允許對於極性半導體材料層如極性複合半導體材料,選擇期望的表面極性。在一種觀點中,也說明包括在極性複合半導體層上的電晶體裝置之設備,也說明包括包含耦接到印刷電路板之微處理器之計算裝置的系統,該微處理器包括多個電晶體裝置,如多個HEMT裝置。
在以下的說明中,說明的實現的各種觀點將使用本領域的技術人員通常使用的用語來說明,以傳達其工作的實質給其他本領域的技術人員。然而,對於本領域的技術人員顯而易見的,實施例中僅可以用一些所描述的觀點被實施。用於解釋的目的,具體的數字、材料和配置都闡述以便提供說明性實現的徹底理解。然而,對於本領域的技術人員顯而易見的,這些實施例可以在沒有這些具體細節的情況下被實施。在其它實例中,眾所皆知的特徵被省略或簡化以便不糢糊說明性實現。
以最有助於理解本文所述實施例的方式,各種操作將被描述為多個依次獨立操作,然而,描述的順序不應該被解釋為暗示這些操作一定是順序相關的。尤其是,這些操作不需要以呈現的順序執行。
各個HEMT包括形成至少兩個層,閘極介電層和閘極電極層,的閘極堆疊層。閘極介電層可以包括一層或層的堆疊。一個或多個層可包括氧化矽、二氧化矽(SiO2)和/或高k介電材料。高k介電材料可以包括元
素,如鉿、矽、氧、鈦、鉭、鑭、鋁、鋯、鋇、鍶、釔、鉛、鈧、鈮和鋅。可用在閘極介電層之高k材料的實例包括但不限於,氧化鉿、氧化鉿矽、氧化鑭、氧化鑭鋁、氧化鋯、氧化鋯矽、氧化鉭、氧化鈦、氧化鋇鍶鈦、氧化鋇鈦、氧化鍶鈦、氧化釔、氧化鋁、氧化鉛鈧鉭和鈮酸鉛鋅。在一些實施例中,退火程序可以在閘極介電層上被進行,以在使用高k材料時提高其品質。
閘極電極層係形成在閘極介電層上,並且可以包括至少一個功函數金屬,如氮化鈦、鎳、鉑或鎢。在一些實施例中,閘極電極層可以兩個或多個金屬層的堆疊,其中一個或多個金屬層係功函數金屬層以及至少一個金屬層係填充金屬層。
在一些實施例中,閘極電極可以由“U”形結構組成,該“U”形結構包括實質上平行於基板表面之底部和實質上垂直於該基板頂表面之兩個側壁部分。在另一實現中,形成閘極電極的金屬層中的至少一個可以簡單地是實質上平行於基板頂表面之平面層,並且不包括實質上垂直於該基板頂表面之側壁部分。在另外的實現中,閘極電極可以由U形結構和平面的、非U形結構之組合組成。例如,閘極電極可包括形成在一個或多個平面的、非U形層之上的一個或多個U形金屬層。
在一些實施例中,一對側壁間隔物可形成在托住閘極堆疊的閘極堆疊之相對側。側壁間隔物可以由一種材料形成,諸如氮化矽、氧化矽、碳化矽、摻雜碳之氮
化矽以及氮氧化矽。在本領域中,用於形成側壁間隔物的程序是眾所皆知的,通常包括沉積和蝕刻程序步驟。在一個替代實現中,可以使用多個間隔物對,例如兩對、三對或四對的側壁間隔物可在閘極堆疊的相對側形成。
正如本領域已知的,源極區和汲極區係形成在基板內相鄰於各HEMT的閘極堆疊。源極區和汲極區通常使用佈植/擴散程序或者蝕刻/沉積程序來形成。在前者的程序中,摻雜劑如矽可以是離子佈植到基板中,以形成源極區和汲極區。通常在離子佈植程序之後,退火程序可激活摻雜劑並導致它們進一步擴散到基板中。在後者的程序中,基板可以首先被蝕刻,以在源極區和汲極區的位置形成凹部。磊晶沉積程序可以接著被進行用以利用被用於製造源極區和汲極區之材料來填充凹部。在一些實現中,源極區和汲極區可用摻雜劑如矽或鍺就地摻雜。在進一步的實施例中,源極區和汲極區可以使用一個或多個其他的半導體材料如氮化銦鎵或氮化鎵或氮化銦或III-V族材料或合金來形成。並且在進一步的實施例中,一個或多個金屬層和/或金屬合金可以被使用來形成源極區和汲極區。
一個或多個層間介電質(ILD)係沉積在MOS電晶體之上。ILD層可以利用已知適用於積體電路結構的介電材料來形成,例如低k介電材料。可使用之介電質材料的例子包括但不限於二氧化矽(SiO2)、摻雜碳的氧化物(CDO)、氮化矽、有機聚合物如全氟環丁烷或聚四氟乙烯、氟矽酸鹽玻璃(FSG)和有機矽酸酯如倍半矽
氧烷、矽氧烷或有機矽酸鹽玻璃。ILD層可以包括孔或空隙,以進一步降低其介電常數。
圖1顯示在模板或犧牲基板上的極性半導體材料層的橫截面側視圖。代表性地,犧牲基板110是單晶矽基板、多晶矽半導體基板、碳化矽基板或藍寶石基板。在犧牲基板110的一個表面上是一層極性複合半導體材料。在一種實施例中,合適的極性複合半導體材料係具有纖鋅礦晶體結構的材料,如氮化鎵、氮化鋁或氧化鋅。在一種實施例中,極性複合半導體層120為沉積至30微米厚度之氮化鎵。在一種實施例中,氮化鎵的複合半導體層120是藉由磊晶生長程序來形成。在所示實施例中,層120在與犧牲基板110的界面具有-c極性,並在相對的表面具有+c極性。
圖2顯示在極性半導體層上引入屏障層之後圖1的結構。圖2顯示具有厚度為約20奈米(nm)之材料的屏障層130。在一種實施例中,屏障層130是代表性地藉由磊晶程序形成的複合半導體材料,如氮化鋁鎵(AlGaN)。在一種實施例中,屏障層130的材料被選擇由於其在層120中引起二維電子氣體(2DEG)的能力。圖2顯示在層120中形成的2DEG層125。如圖所示,代表性地,2DEG層125被形成在屏障層130之表面和極性複合半導體層120之表面的界面之下幾個奈米(例如,二至四個奈米)。
圖2還顯示在極性複合半導體層120中引入
穿孔層之後的結構100。在一種實施例中,穿孔層135藉由離子切割、非晶起泡或應力誘發的剝離程序形成。在一種實施例中,穿孔層135位於距離極性複合半導體層120之表面與屏障層130之表面的界面數十奈米之處。代表性地,穿孔層135距離該界面100奈米。
圖3顯示在結構100的反轉和其連接到載體基板以形成複合結構之後圖2的結構。圖3顯示屏障層130連接到載體基板,特別是載體基板140。在一種實施例中,載體基板140係,例如,單晶矽基板、多晶矽基板、碳化矽基板或藍寶石基板。如圖所示,如圖2中顯示結構100被反轉或翻轉,使得屏障層130的表面與載體基板140接觸。
圖4顯示在穿孔層的複合結構之分離或分裂之後圖3的複合結構。該分離暴露在暴露的表面具有-c極性的極性複合半導體層120。
圖5顯示在結構上的極性複合半導體層120的厚度減小之後圖4的結構。在一種實施例中,極性複合半導體層120的厚度可以藉由研磨、拋光或蝕刻來減小。代表性的目標厚度為約10奈米。
圖6顯示引入在結構上的裝置之後圖5的結構。圖示的裝置是電晶體。圖6顯示電晶體150包括閘極電極155、源極區160和汲極區165。每個閘極電極155、源極區160和汲極區165可藉由金屬化被連接到電性接點。如圖所示,在一種實施例中,在形成結構100上
的閘極電極155之前,介電層,如氧化物,可以形成在極性複合半導體層120的一部分上,以提供用於閘極電極的閘極介電質。形成氧化的閘極介電層170的一種方式是藉由生長技術。閘極介電層170的代表性厚度是約一到二奈米。可以理解的,閘極介電層170可以被省略,如希望在閘極電極和複合半導體層之間形成肖特基屏障時。
參照圖6,在一種實施例中,閘極電極155和2DEG層125之間的距離是顯示為距離D的閘極通道分離。考慮閘極介電質170可以是薄約一奈米,距離D主要取決於極性複合屏障層120的厚度。層轉移厚度可以精確地被控制以及薄化程序如蝕刻和/或拋光可以使複合半導體層薄至數十奈米或更少。在這種情況下,在圖6中所示的翻轉層結構的閘極-通道分離(有效閘極氧化物厚度)可以小於具有複合半導體層與閘極電極之間的屏障層的非翻轉結構的有效閘極氧化物厚度。較薄的閘極-通道分離致使在空乏模式中HEMT裝置有更好的閘極控制。
圖7顯示包括一個或多個實施例之中介層200。中介層200是用於將第一基板202橋接至第二基板204的居間基板。例如,第一基板202可以是積體電路晶粒。例如,第二基板204可以是記憶體模組、電腦主機板或另一積體電路晶粒。一般地,中介層200的目的是要將連接擴散到更寬的間距或將連接重新佈線到不同的連接。例如,中介層200可以耦接積體電路晶粒到球閘陣列(BGA)206,其可隨後被耦接到第二基板204。在一些
實施例中,第一和第二基板202/204被連接到中介層200的相對側。在其他實施例中,第一和第二基板202/204被連接到中介層200的同一側。而在進一步的實施例中,三個或更多個基板藉由中介層200的方式相互連接。
中介層200可以由環氧樹脂、玻璃纖維增強環氧樹脂、陶瓷材料或聚合物材料(如聚酰亞胺)形成。在進一步實施方式中,中介層可以由穿插的剛性或撓性的材料形成,其可以包括上述用在半導體基板中的相同材料,諸如矽、鍺以及其它III-V族和IV族材料。
該中介層可以包括金屬互連208和通孔210,其包括但不限於穿透矽通孔(TSV)212。中介層200可進一步包括嵌入式裝置214,其包括被動和主動裝置。這樣的裝置包括但不限於,電容器、去耦電容器、電阻器、電感器、熔絲、二極體、變壓器、感測器和靜電放電(ESD)裝置。更為複雜的裝置,如無線電頻率(RF)裝置、功率放大器、電源管理裝置、天線、陣列、感測器和MEMS裝置也可形成在中介層200上。
根據實施例,本文揭露的裝置或程序可以使用在中介層200的製造。
圖8顯示根據一種實施例的計算裝置300。計算裝置300可以包括多個元件。在一種實施例中,這些元件被連接到一個或多個主機板。在一種替代實施例中,這些元件被製造至單一系統單晶片(SoC)晶粒上,而不是至主機板上。計算裝置300中的元件包括但不限於,積體
電路晶粒302以及至少一個通訊晶片308。在一些實現中,通訊晶片308被製造為積體電路晶粒302的一部分。積體電路晶粒302可以包括CPU 304以及通常被用作快取記憶體的晶粒上記憶體306,其可以藉由如嵌入式DRAM(eDRAM)或者自旋轉移力矩記憶體(STTM或STTM-RAM)技術來提供。
計算裝置300可以包括可以或可以不實體地和電性地耦接到主機板或製造在系統單晶片晶粒之內的其它元件。這些其它元件包括但不限於,揮發性記憶體310(例如,DRAM)、非揮發性記憶體312(例如,ROM或快閃記憶體)、圖形處理單元314(GPU)、數位信號處理器316、加密處理器342(在硬體內執行加密演算法的專用處理器)、晶片組320、天線322、顯示器或觸控螢幕顯示器324、觸控式螢幕控制器326、電池328或其他電源、功率放大器(未顯示)、全球定位系統(GPS)裝置344、羅盤330、動作協同處理器或感測器332(其可包括加速計、陀螺儀和羅盤)、揚聲器334、照相機336、使用者輸入裝置338(諸如鍵盤、滑鼠、手寫筆和觸控板)和大容量儲存裝置340(諸如硬碟、光碟(CD)、數位多功能光碟(DVD)等)。
通訊晶片308致使用於資料傳送往來於計算裝置300的無線通訊。用語“無線”及其衍生詞可以用於描述電路、裝置、系統、方法、技術、通訊通道等,其可藉由非固體媒體、藉由使用調製的電磁輻射來傳送資料。該
用語不暗示相關的裝置不包含任何導線,儘管在一些實施例中它們可能沒有。通訊晶片308可以實現任何數目的無線標準或協議,包括但不限於Wi-Fi(IEEE 802.11系列)、WiMAX(IEEE 802.16系列)、IEEE 802.20、長期演進(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍牙,其衍生物,以及任何被指定為3G、4G、5G及之後的其他無線協議。計算裝置300可以包括多個通訊晶片308。例如,第一通訊晶片308可專用於短範圍無線通訊,如Wi-Fi和藍牙,以及第二通訊晶片308可專用於長範圍無線通訊,如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO和其他。
計算裝置300的處理器304包括一個或多個裝置,諸如電晶體或金屬互連,其按照上述實施例來形成。用語“處理器”可以指任何裝置或裝置的部分,其處理來自暫存器和/或記憶體的電子資料以轉換該電子資料成其他可以儲存在暫存器和/或記憶體的電子資料。
通訊晶片308還可以包括一個或多個裝置,諸如電晶體或金屬互連,其按照上述實施例來形成。
在進一步的實施例中,其他容納在計算裝置300內的元件可包含一個或多個裝置,諸如電晶體或金屬互連,其按照上述實現來形成。
在各種實施例中,計算裝置300可以是膝上型電腦、小筆電、筆記型電腦、超輕薄電腦、智慧手機、
平板電腦、個人數位助理(PDA)、超行動PC、行動電話、桌上電腦、伺務器、印表機、掃描器、監視器、機上盒、娛樂控制單元、數位相機、可攜式音樂播放器或者數位錄影機。在另外的實現中,計算裝置300可以是處理資料的任何其它電子裝置。
實例1為一種方法,包括在犧牲基板上的極性複合半導體層上形成屏障層;將該犧牲基板耦接到載體基板,用以形成複合結構,其中該屏障層係設置在該極性複合半導體層與該載體基板之間;將該犧牲基板從該複合結構分離,用以暴露該極性複合半導體層;以及形成至少一個電路裝置。
在實例2中,實例1的極性複合半導體層在與該屏障層的接面具有第一極性以及在藉由將該犧牲基板從該複合結構分離而暴露的該表面具有第二不同極性。
在實例3中,實例2的該第一極性係+c而該第二極性係-c。
在實例4中,實例1的形成屏障層包括在該極性複合半導體層中沉積引起二維電子氣體的材料。
在實例5中,在耦接之前,實例1的方法在該複合半導體層中形成穿孔區以及將該犧牲基板分離包括在該穿孔區分離。
在實例6中,在將該犧牲基板分離之後,實
例5的方法包括將該複合半導體層薄化。
在實例7中,實例6的形成至少一個電路裝置包括在閘極介電層上形成包括閘極電極之電晶體。
實例8為由實例1~7中任何一種方法製成的一種積體電路。
實例9為一種設備,包括屏障層,其在基板上;電晶體裝置,其在該屏障層上;以及極性複合半導體層,其設置在該屏障層和該電晶體裝置之間,該極性複合半導體層包括二維電子氣體於其中。
在實例10中,實例9的該極性複合半導體層在定義與該屏障層的接面之表面具有第一極性以及在相對表面具有第二不同極性。
在實例11中,實例9的該第一極性係+c而該第二極性係-c。
在實例12中,實例9的該電晶體裝置包括閘極電極以及在該閘極電極各別側的源極區與汲極區,該設備還包括在該極性複合半導體層與該閘極電極之間的閘極介電層。
在實例13中,實例9的該極性複合半導體層包括包含纖鋅礦晶體結構的材料。
在實例14中,實例9的該極性複合半導體層包括氮化鎵。
在實例15中,實例14的該屏障層包括氮化鋁鎵。
實例16為一種系統,包括計算裝置,包括耦接到印刷電路板的微處理器,該微處理器包括在極性半導體層上的複數個電晶體裝置,該極性半導體層包含二維電子氣體於其中,該極性半導體層包含複合基板層,該複合基板層包括屏障層,其中該極性半導體層係設置在該等複數個電晶體裝置和該屏障層之間。
在實例17中,實例16的該極性複合半導體層在定義與該屏障層的接面之表面具有第一極性以及在相對表面具有第二不同極性。
在實例18中,實例17的該第一極性係+c而該第二極性係-c。
在實例19中,實例16的該等複數個電晶體裝置各包括設置在介電層上的閘極電極。
在實例20中,實例16的該極性複合半導體層包括包含纖鋅礦晶體結構的材料。
在實例21中,實例16的該極性複合半導體層包括氮化鎵。
上述圖示實現的說明,包括在摘要中所描述的,並非意在窮舉或限制本發明的實施例為所揭露的精確形式。雖然在本文中描述的具體實現和實例用於說明性目的,那些相關領域技術人員將理解各種等同修改是可能在本發明的範圍之內。
可以根據上述詳細說明修飾本發明的實施例。在下面的申請專利範圍中使用的用語不應當被解釋為
限制本發明的各種實施例在說明書和申請專利範圍中揭露的具體實現。相對的,根據申請專利範圍詮釋的既定原則解釋,範圍完全由下面的申請專利範圍來確定。
Claims (13)
- 一種藉由層轉移之在反向極性基板上製造高電子遷移率電晶體的方法,包括:在犧牲基板上的極性複合半導體層上形成屏障層;將該屏障層直接耦接到載體基板,用以形成複合結構,其中該屏障層係設置在該極性複合半導體層與該載體基板之間;將該犧牲基板從該複合結構分離,用以暴露該極性複合半導體層;以及形成至少一個電路裝置;其中用於該屏障層的材料係選自能夠在該極性複合半導體層中引起二維電子氣體(2DEG)的材料。
- 如申請專利範圍第1項的方法,其中該極性複合半導體層在與該屏障層的接面具有第一極性以及在藉由將該犧牲基板從該複合結構分離而暴露的該表面具有第二不同極性。
- 如申請專利範圍第2項的方法,其中該第一極性係+c而該第二極性係-c。
- 如申請專利範圍第1項的方法,其中在耦接之前,該方法包括在該複合半導體層中形成穿孔區以及將該犧牲基板分離包括在該穿孔區分離。
- 如申請專利範圍第4項的方法,其中在將該犧牲基板分離之後,該方法進一步包括將該複合半導體層薄化。
- 如申請專利範圍第5項的方法,其中形成至少一個 電路裝置包括在閘極介電層上形成包括閘極電極之電晶體。
- 一種具有高電子遷移率電晶體的裝置,包括:屏障層,其直接接觸基板;電晶體裝置,其在該屏障層上;以及極性複合半導體層,其設置在該屏障層和該電晶體裝置之間,該極性複合半導體層包括二維電子氣體於其中;其中用於該屏障層的材料係選自能夠在該極性複合半導體層中引起二維電子氣體(2DEG)的材料。
- 如申請專利範圍第7項的裝置,其中該極性複合半導體層在定義與該屏障層的接面之表面具有第一極性以及在相對表面具有第二不同極性。
- 如申請專利範圍第7項的裝置,其中該第一極性係+c而該第二極性係-c。
- 如申請專利範圍第7項的裝置,其中該電晶體裝置包括閘極電極以及在該閘極電極各別側的源極區與汲極區,該裝置還包括在該極性複合半導體層與該閘極電極之間的閘極介電層。
- 如申請專利範圍第7項的裝置,其中該極性複合半導體層包括包含纖鋅礦晶體結構的材料。
- 如申請專利範圍第7項的裝置,其中該極性複合半導體層包括氮化鎵。
- 如申請專利範圍第12的裝置,其中該屏障層包括氮化鋁鎵。
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