CN106415846B - 通过层转移在反向极化衬底上的高电子迁移率晶体管制造工艺 - Google Patents
通过层转移在反向极化衬底上的高电子迁移率晶体管制造工艺 Download PDFInfo
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- CN106415846B CN106415846B CN201480078732.0A CN201480078732A CN106415846B CN 106415846 B CN106415846 B CN 106415846B CN 201480078732 A CN201480078732 A CN 201480078732A CN 106415846 B CN106415846 B CN 106415846B
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Abstract
一种方法包括:在牺牲衬底上的极性化合物半导体层上形成阻挡层;将牺牲衬底耦合到载体衬底以形成复合结构,其中,阻挡层布置在极性化合物半导体层与载体衬底之间;将牺牲衬底从复合结构分离以暴露出极性化合物半导体层;以及形成至少一个电路器件。一种装置包括:在衬底上的阻挡层;在阻挡层上的晶体管器件;以及布置在阻挡层与晶体管器件之间的极性化合物半导体层,极性化合物半导体层包括其中的二维电子气。
Description
技术领域
化合物半导体器件。
背景技术
化合物半导体器件被视为是硅基器件的有前途的替代物或补足物。化合物半导体可通常被描述为二元或三元III-V族半导体材料。III-V族参考标记表示分别在周期表的第XIII和XV族中的元素。III族和V族符号参考了先前的国际理论化学与应用化学联合会(IUPAC)标号。
诸如氮化镓之类的二元化合物半导体具有纤锌矿晶体结构和晶体极性。在无线基础设施应用中使用氮化镓高电子迁移率晶体管(HEMT)。氮化镓基金属氧化物半导体场效应晶体管(MOSFET)和金属半导体场效应晶体管(MESFET)也在高功率电子器件中提供优点。
异构集成方案通常涉及不同半导体材料的集成以制造虚拟衬底。半导体层到衬底的层转移是制造虚拟衬底的有前途的方法,因为在晶格失配材料之间可避免相对厚的缓冲层。从氮化镓的层转移的可行性方面来说,氮化镓制造方案倾向于优选某一晶体极性,即正或+c表面极性。转移极性化合物半导体层(例如,根据这样的方案制造的氮化镓层)的努力往往导致具有可用于器件形成的+c极性表面的半导体层的转移。
附图说明
图1示出了在模板或牺牲衬底上的极性半导体材料层的横截面侧视图。
图2示出了在极性半导体层上引入阻挡层之后的图1的结构。
图3示出了在结构的倒置以及将其连接到载体衬底以形成复合结构之后的图2的结构。
图4示出了复合结构在极性半导体层中的贯穿(perforation)层处的分离或分割之后的图3的复合结构。
图5示出了在结构上的极性化合物半导体层的厚度减小之后的图4的结构。
图6示出了在结构上引入器件之后的图5的结构。
图7是实现一个或多个实施例的内插器。
图8是根据实施例构建的计算设备。
具体实施方式
描述了通过层转移来制造集成电路器件、特别是包括高电子迁移率晶体管(HEMT)的集成电路器件的方法。在一个方面,该方法允许针对极性半导体材料(例如,极性化合物半导体材料)层选择期望的表面极性。还描述了一种装置,其在一个方面包括在极性化合物半导体层上的晶体管器件,因为它是包括计算设备的系统,该计算设备包括耦合到印刷电路板的微处理器,该微处理器包括多个晶体管器件,例如多个HEMT。
在下面的描述中,将使用本领域技术人员通常采用的术语来描述例示性实施方式的各个方面,以将他们的工作的实质传达给本领域其他技术人员。然而,对于本领域技术人员将显而易见的是,可以只利用所述方面中的一些方面来实践实施例。出于解释的目的,阐述了特定的数量、材料和配置,以便提供对例示性实施方式的透彻理解。然而,对于本领域技术人员将显而易见的是,可在没有这些特定细节的情况下实践实施例。在其它示例中,公知的特征被省略或简化,以便不使例示性实施方式难以理解。
各个操作将以最有助于理解本文所述的实施例的方式依次被描述为多个分立操作,然而,描述的顺序不应被解释为暗示这些操作必须是顺序相关的。具体而言,这些操作不需要以呈现的顺序被执行。
每个HEMT包括由至少两层(栅极电介质层和栅极电极层)形成的栅极叠置体。栅极电介质层可包括一层或层的堆叠。一个或多个层可包括氧化硅、二氧化硅(SiO2)和/或高k电介质材料。高k电介质材料可包括元素,例如铪、硅、氧、钛、钽、镧、铝、锆、钡、锶、钇、铅、钪、铌和锌。可在栅极电介质层中使用的高k材料的示例包括,但不限于:氧化铪、氧化铪硅、氧化镧、氧化镧铝、氧化锆、氧化锆硅、氧化钽、氧化钛、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化钇、氧化铝、氧化铅钪钽和铌酸铅锌。在一些实施例中,可在栅极电介质层上执行退火工艺,以在使用高k材料时提高它的质量。
栅极电极层在栅极电介质层上形成,并可由至少一种功函数金属(例如,氮化钛、镍、铂或钨)组成。在一些实施方式中,栅极电极层可由两个或更多个金属层的叠置体组成,其中一个或多个金属层是功函数金属层,且至少一个金属层是填充金属层。
在一些实施方式中,栅极电极可由“U”形结构组成,该“U”形结构包括基本上平行于衬底的表面的底部部分以及基本上垂直于衬底的顶部表面的两个侧壁部分。在另一实施方式中,形成栅极电极的金属层中的至少一个金属层可以简单地是基本上平行于衬底的顶部表面的平面层,且不包括基本上垂直于衬底的顶部表面的侧壁部分。在另外的实施方式中,栅极电极可由U形结构和平面非U形结构的组合所组成。例如,栅极电极可由在一个或多个平面非U形层的顶部上形成的一个或多个U形金属层组成。
在一些实施方式中,一对侧壁间隔体可在栅极叠置体的对侧上形成,该对侧围住该栅极叠置体。侧壁间隔体可由诸如氮化硅、氧化硅、碳化硅、掺杂有碳的氮化硅和氮氧化硅之类的材料形成。用于形成侧壁间隔体的工艺在本领域中是公知的,并通常包括沉积和蚀刻工艺步骤。在替代实施方式中,可使用多个间隔体对,例如两对、三对或四对侧壁间隔体可在栅极叠置体的对侧上形成。
如本领域所公知的,源极区和漏极区在相邻于每个HEMT的栅极叠置体的衬底内形成。通常使用注入/扩散工艺或蚀刻/沉积工艺来形成源极区和漏极区。在前一工艺中,诸如硅之类的掺杂剂可被离子注入到衬底中,以形成源极区和漏极区。激活掺杂剂并使它们进一步扩散到衬底中的退火工艺典型地在离子注入工艺之后。在后一工艺中,衬底可首先被蚀刻以在源极区和漏极区的位置处形成凹陷部。然后可执行外延沉积工艺以使用用于制造源极区和漏极区的材料来填充凹陷部。在一些实施方式中,可原位用掺杂剂(例如,硅或锗)来掺杂源极区和漏极区。在另外的实施例中,可使用一种或多种替代的半导体材料(例如,氮化铟镓或氮化镓或氮化铟或III-V族材料或合金)来形成源极区和漏极区。并且在另外的实施例中,一层或多层金属和/或金属合金可用于形成源极区和漏极区。
一个或多个层间电介质(ILD)沉积在MOS晶体管上方。可使用因它们在集成电路结构中的适用性而公知的电介质材料(例如,低k电介质材料)来形成ILD层。可被使用的电介质材料的示例包括,但不限于:二氧化硅(SiO2)、掺碳氧化物(CDO)、氮化硅、有机聚合物(例如,八氟环丁烷或聚四氟乙烯)、氟硅酸盐玻璃(FSG)和有机硅酸盐(例如,硅倍半氧烷、硅氧烷或有机硅酸盐玻璃)。ILD层可包括小孔或空气间隙以进一步减小它们的介电常数。
图1示出了在模板或牺牲衬底上的极性半导体材料层的横截面侧视图。代表性地,牺牲衬底110是单晶硅衬底、多晶半导体衬底、碳化硅衬底或蓝宝石衬底。在牺牲衬底110的一个表面上的是极性化合物半导体材料层。在一个实施例中,适当的极性化合物半导体材料是具有纤锌矿晶体结构的材料,例如氮化镓、氮化铝或氧化锌。在一个实施例中,极性化合物半导体层120是被沉积到30微米的厚度的氮化镓。在一个实施例中,通过外延生长工艺来形成氮化镓的化合物半导体层120。在所示实施例中,层120在与牺牲衬底110的界面处具有-c极性并且在相对的表面处具有+c极性。
图2示出了在极性半导体层上引入阻挡层之后的图1的结构。图2示出具有20纳米(nm)量级的厚度的材料的阻挡层130。在一个实施例中,阻挡层130是代表性地通过外延工艺形成的化合物半导体材料,例如氮化铝镓(AlGaN)。在一个实施例中,用于阻挡层130的材料出于它在层120中引入二维电子气(2DEG)的能力而被选择。图2示出在层120中形成的2DEG层125。代表性地,2DEG层125被形成为低于阻挡层130的表面和极性化合物半导体层120的表面的界面几纳米(例如,2到4纳米),如所视的。
图2还示出在极性化合物半导体层120中引入贯穿层之后的结构100。在一个实施例中,通过离子切割(ion cut)工艺、非晶起泡(amorphous blistering)工艺或应力引入的散裂(stress-induced spalling)工艺来形成贯穿层135。在一个实施例中,贯穿层135位于离极性化合物半导体层120的表面与阻挡层130的表面的界面数十纳米处。代表性地,贯穿层135离界面100纳米。
图3示出了在结构100的倒置以及将其连接到载体衬底以形成复合结构之后的图2的结构。图3示出连接到载体衬底(显而易见地,载体衬底140)的阻挡层130。在一个实施例中,载体衬底140是例如单晶硅衬底、多晶硅衬底、碳化硅衬底或蓝宝石衬底。如所示的,如图2中所示的结构100被倒置或翻转,以使得阻挡层130的表面与载体衬底140接触。
图4示出了复合结构在贯穿层处的分离或分割之后的图3的复合结构。分离暴露出极性化合物半导体层120,其在被暴露表面处具有-c极性。
图5示出了减小结构上的极性化合物半导体层120的厚度之后的图4的结构。在一个实施例中,可通过研磨、抛光或蚀刻来减小极性化合物半导体层120的厚度。代表性的目标厚度是10nm量级。
图6示出了在结构上引入器件之后的图5的结构。所示器件是晶体管。图6示出包括栅极电极155、源极区160和漏极区165的晶体管150。栅极电极155、源极区160和漏极区165中的每个可通过金属化连接到电接触部。如所示的,在一个实施例中,在结构100上形成栅极电极155之前,电介质层(例如,氧化物)可在极性化合物半导体层120的部分上形成,以为栅极电极提供栅极电介质。形成氧化物的栅极电介质层170的一种方式是通过生长技术。栅极电介质层170的代表性厚度是1到2纳米量级。应认识到,例如当期望形成栅极电极与化合物半导体层之间的肖特基势垒时,可省略栅极电介质层170。
参考图6,在一个实施例中,栅极电极155与2DEG层125之间的距离是被示为距离D的栅极-沟道间隔。考虑到栅极电介质170可以薄至大约一纳米,距离D主要取决于极性化合物阻挡层120的厚度。层转移厚度可被精确地控制,且薄化工艺(例如,蚀刻和/或抛光)可使化合物半导体层变得薄至几十纳米或更小。在这样的情况下,图6中所示的翻转层结构的栅极-沟道间隔(有效栅极氧化物厚度)可小于非翻转结构的有效栅极氧化物厚度,其中在化合物半导体层与栅极电极之间存在阻挡层。较薄的栅极-沟道间隔实现在耗尽模式HEMT器件中的较好的栅极控制。
图7示出了包括一个或多个实施例的内插器200。内插器200是用于将第一衬底202桥接到第二衬底204的居间衬底。第一衬底202可以是例如集成电路管芯。第二衬底204可以是例如存储器模块、计算机母板或另一集成电路管芯。通常,内插器200的目的是将连接扩展到较宽间距或将连接重新布线到不同的连接。例如,内插器200可将集成电路管芯耦合到可随后耦合到第二衬底204的球栅阵列(BGA)206。在一些实施例中,第一衬底和第二衬底202/204附接到内插器200的对侧。在其它实施例中,第一衬底和第二衬底202/204附接到内插器200的同一侧。并且在另外的实施例中,三个或更多个衬底通过内插器200被互连。
内插器200可由环氧树脂、玻璃纤维加强的环氧树脂、陶瓷材料或聚合物材料(例如,聚酰亚胺)形成。在另外的实施方式中,内插器可由可包括上面所述的用于半导体衬底中的相同材料(例如,硅、锗和其它III-V族和IV族材料)的替代刚性或柔性材料形成。
内插器可包括金属互连件208和过孔210,包括但不限于穿硅过孔(TSV)212。内插器200还可包括嵌入式器件214,包括无源器件和有源器件两者。这样的器件包括但不限于:电容器、去耦电容器、电阻器、电感器、熔丝、二极管、变压器、传感器和静电放电(ESD)器件。更复杂的器件(例如,射频(RF)器件、功率放大器、功率管理器件、天线、阵列、传感器和MEMS器件)也可在内插器200上形成。
根据实施例,可在内插器200的制造中使用本文公开的装置或工艺。
图8示出了根据一个实施例的计算设备300。计算设备300可包括多个部件。在一个实施例中,这些部件附接到一个或多个母板。在替代实施例中,这些部件被制造至单个片上系统(SoC)管芯而非母板上。计算设备300中的部件包括但不限于集成电路管芯302和至少一个通信芯片308。在一些实施方式中,通信芯片308被制造为集成电路管芯302的部分。集成电路管芯302可包括CPU 304以及常常用作高速缓存存储器的管芯上存储器306,其可由诸如嵌入式DRAM(eDRAM)或自旋转移扭矩存储器(STTM或STTM-RAM)之类的技术来提供。
计算设备300可包括可以或可以不物理耦合和电气地耦合到母板或者被制造在SoC管芯内的其它部件。这些其它部件包括但不限于:易失性存储器310(例如,DRAM)、非易失性存储器312(例如,ROM或闪存)、图形处理单元314(GPU)、数字信号处理器316、密码处理器342(执行硬件内的加密算法的专用处理器)、芯片组320、天线322、显示器或触摸屏显示器324、触摸屏控制器326、电池328或其它电源、功率放大器(未示出)、全球定位系统(GPS)设备344、罗盘330、运动协处理器或传感器332(其可包括加速度计、陀螺仪和罗盘)、扬声器334、照相机336、用户输入设备338(例如,键盘、鼠标、手写笔和触摸板)以及大容量存储设备340(例如,硬盘驱动器、光盘(CD)、数字通用盘(DVD)等)。
通信芯片308实现了往返于计算设备300进行数据的传送的无线通信。术语“无线”及其派生词可用于描述可通过使用经由非固体介质的经调制电磁辐射来传输数据的电路、器件、系统、方法、技术、通信信道等。该术语并不暗示相关联的器件不包含任何线,虽然在一些实施例中它们可以不包含线。通信芯片308可实现多种无线标准或协议中的任一种,包括但不限于Wi-Fi(IEEE 802.11系列)、WiMAX(IEEE 802.16系列)、IEEE 802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、其派生物以及被指定为3G、4G、5G和更高代的任何其它无线协议。计算设备300可包括多个通信芯片308。例如,第一通信芯片308可专用于较短距离的无线通信(例如,Wi-Fi和蓝牙),而第二通信芯片308可专用于较长距离的无线通信,例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等。
计算设备300的处理器304包括根据上面所述的实施例形成的一个或多个器件,例如晶体管或金属互连件。术语“处理器”可以指代对来自寄存器和/或存储器的电子数据进行处理以将该电子数据转换成可存储在寄存器和/或存储器中的其它电子数据的任何器件或器件的部分。
通信芯片308也可包括根据上面所述的实施例形成的一个或多个器件,例如晶体管或金属互连件。
在另外的实施例中,容纳在计算设备300内的另一部件可包含根据上面所述的实施方式形成的一个或多个器件,例如晶体管或金属互连件。
在各个实施例中,计算设备300可以是膝上型计算机、上网本计算机、笔记本计算机、超级本计算机、智能电话、平板计算机、个人数字助理(PDA)、超移动PC、移动电话、台式计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字照相机、便携式音乐播放器或数字视频记录器。在另外的实施方式中,计算设备300可以是处理数据的任何其它电子设备。
示例
示例1是一种方法,包括:在牺牲衬底上的极性化合物半导体层上形成阻挡层;将牺牲衬底耦合到载体衬底以形成复合结构,其中,阻挡层布置在极性化合物半导体层与载体衬底之间;将牺牲层从复合结构分离以暴露出极性化合物半导体层;以及形成至少一个电路器件。
在示例2中,示例1的极性化合物半导体层在与阻挡层的接合处具有第一极性,并且在通过将牺牲衬底从复合结构分离而暴露出的表面处具有不同的第二极性。
在示例3中,示例2的第一极性是+c,并且第二极性是-c。
在示例4中,示例1的形成阻挡层包括沉积一种材料,所述材料在极性化合物半导体层中引入二维电子气。
在示例5中,在耦合之前,示例1的方法包括在化合物半导体层中形成贯穿区,并且分离牺牲衬底包括在贯穿区处进行分离。
在示例6中,在分离牺牲衬底之后,示例5的方法包括使化合物半导体层变薄。
在示例7中,示例6的形成至少一个电路器件包括形成晶体管,所述晶体管包括栅极电介质层上的栅极电极。
示例8是通过示例1-7所述的方法中的任一方法制造的集成电路器件。
示例9是一种装置,包括:在衬底上的阻挡层;在阻挡层上的晶体管器件;以及布置在阻挡层与晶体管器件之间的极性化合物半导体层,该极性化合物半导体层包括其中的二维电子气。
在示例10中,示例9的极性化合物半导体层在界定与阻挡层的接合的表面处具有第一极性,并且在相对的表面处具有不同的第二极性。
在示例11中,示例9的第一极性是+c,并且第二极性是-c。
在示例12中,示例9的晶体管器件包括栅极电极以及在栅极电极的相应侧部上的源极区和漏极区,该装置还包括位于极性化合物半导体层与栅极电极之间的栅极电介质层。
在示例13中,示例9的极性化合物半导体层包括包含纤锌矿晶体结构的材料。
在示例14中,示例9的极性化合物半导体层包括氮化镓。
在示例15中,示例14的阻挡层包括氮化铝镓。
示例16是一种包括计算设备的系统,该计算设备包括耦合到印刷电路板的微处理器,微处理器包括在极性半导体层上的多个晶体管器件,极性半导体层包括在其中的二维电子气,极性半导体层包括包含阻挡层的复合衬底层,其中,极性半导体层布置在多个晶体管器件与阻挡层之间。
在示例17中,示例16的极性化合物半导体层在界定与阻挡层的接合的表面处具有第一极性,并且在相对的表面处具有不同的第二极性。
在示例18中,示例17的第一极性是+c,并且第二极性是-c。
在示例19中,示例16的多个晶体管器件中的每个晶体管器件包括布置在电介质层上的栅极电极。
在示例20中,示例16的极性化合物半导体层包括包含纤锌矿晶体结构的材料。
在示例21中,示例16的极性化合物半导体层包括氮化镓。
所示实施方式的以上描述(包括在摘要中描述的内容)并非旨在是穷尽的或将本发明限于所公开的精确形式。尽管在本文中出于说明性目的描述了本发明的特定实施方式和示例,但是各种等效修改在如本领域技术人员将认识到的范围内是可能的。
根据以上具体实施方式,可以对本发明做出这些修改。在所附权利要求中使用的术语不应被解释为将本发明限于在说明书和权利要求中公开的特定实施方式。更确切地,范围应完全由所附权利要求来确定,应根据已确立的权利要求的解释原则来解释权利要求书。
Claims (18)
1.一种用于形成半导体装置的方法,包括:
在牺牲衬底上的极性化合物半导体层上形成阻挡层;
将所述牺牲衬底耦合到载体衬底以形成复合结构,其中,所述阻挡层布置在所述极性化合物半导体层与所述载体衬底之间;
将所述牺牲衬底从所述复合结构分离以暴露出所述极性化合物半导体层;以及
形成至少一个电路器件,其中,所述至少一个电路器件包括栅极电极以及在所述栅极电极的相应侧部上的源极区和漏极区,并且其中,所述源极区、所述漏极区和所述栅极电极均位于所述极性化合物半导体层上,并且均与所述极性化合物半导体层相接触。
2.根据权利要求1所述的方法,其中,所述极性化合物半导体层在与所述阻挡层的接合处具有第一极性,并且在通过将所述牺牲衬底从所述复合结构分离而暴露出的表面处具有不同的第二极性。
3.根据权利要求2所述的方法,其中,所述第一极性是+c,并且所述第二极性是-c。
4.根据权利要求1所述的方法,其中,形成阻挡层包括沉积一种材料,所述材料在所述极性化合物半导体层中引入二维电子气。
5.根据权利要求1所述的方法,其中,在耦合之前,所述方法包括在所述化合物半导体层中形成贯穿区,并且分离所述牺牲衬底包括在所述贯穿区处进行分离。
6.根据权利要求5所述的方法,其中,在分离所述牺牲衬底之后,所述方法还包括使所述化合物半导体层变薄。
7.一种通过权利要求1-6所述的方法中的任一方法制造的集成电路器件。
8.一种半导体装置,包括:
阻挡层,所述阻挡层位于衬底上;
晶体管器件,所述晶体管器件位于所述阻挡层上;以及
极性化合物半导体层,所述极性化合物半导体层被布置在所述阻挡层与所述晶体管器件之间,所述极性化合物半导体层包括其中的二维电子气,其中,所述晶体管器件包括栅极电极以及在所述栅极电极的相应侧部上的源极区和漏极区,并且其中,所述源极区、所述漏极区和所述栅极电极均位于所述极性化合物半导体层上,并且均与所述极性化合物半导体层相接触。
9.根据权利要求8所述的半导体装置,其中,所述极性化合物半导体层在界定与所述阻挡层的接合的表面处具有第一极性,并且在相对的表面处具有不同的第二极性。
10.根据权利要求8所述的半导体装置,其中,所述第一极性是+c,并且所述第二极性是-c。
11.根据权利要求8-9中任一项所述的半导体装置,其中,所述极性化合物半导体层包括包含有纤锌矿晶体结构的材料。
12.根据权利要求8所述的半导体装置,其中,所述极性化合物半导体层包括氮化镓。
13.根据权利要求12所述的半导体装置,其中,所述阻挡层包括氮化铝镓。
14.一种包括计算设备的系统,
所述计算设备包括耦合到印刷电路板的微处理器,所述微处理器包括在极性半导体层上的多个晶体管器件,所述极性半导体层包括在其中的二维电子气,所述极性半导体层包括包含有阻挡层的复合衬底层,其中,所述极性半导体层被布置在所述多个晶体管器件与所述阻挡层之间,其中,所述多个晶体管器件中的每个晶体管器件均包括栅极电极以及在所述栅极电极的相应侧部上的源极区和漏极区,并且其中,所述多个晶体管器件中的每个晶体管器件的所述源极区、所述漏极区和所述栅极电极均位于所述极性半导体层上,并且均与所述极性半导体层相接触。
15.根据权利要求14所述的系统,其中,所述极性半导体层在界定与所述阻挡层的接合的表面处具有第一极性,并且在相对的表面处具有不同的第二极性。
16.根据权利要求15所述的系统,其中,所述第一极性是+c,并且所述第二极性是-c。
17.根据权利要求14-15中任一项所述的系统,其中,所述极性半导体层包括包含纤锌矿晶体结构的材料。
18.根据权利要求14-15中任一项所述的系统,其中,所述极性半导体层包括氮化镓。
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