TWI625860B - 啟用間隔物之多晶矽閘極 - Google Patents

啟用間隔物之多晶矽閘極 Download PDF

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TWI625860B
TWI625860B TW103108556A TW103108556A TWI625860B TW I625860 B TWI625860 B TW I625860B TW 103108556 A TW103108556 A TW 103108556A TW 103108556 A TW103108556 A TW 103108556A TW I625860 B TWI625860 B TW I625860B
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保羅 菲思特
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Abstract

一種間隔物蝕刻程序，其產生用於與絕緣閘極電晶體一起使用之絕緣閘極的超窄多晶矽及閘極氧化物。使用介電質及間隔物薄膜沈積技術來形成窄通道。從該介電質移除該間隔物薄膜，其中在該介電質中形成窄通道。在曝露於此等窄通道底部之半導體基板的部分上生長絕緣閘極氧化物。接著，使用多晶矽來填充該等窄通道。從該半導體之面移除該介電質，僅留下該等十分窄的閘極氧化物及該多晶矽。將該等十分窄的閘極氧化物及該多晶矽分開成用於該等絕緣閘極電晶體的絕緣閘極。

Description

啟用間隔物之多晶矽閘極
本發明係關於半導體積體電路(IC)製造，且更特定言之係關於在半導體晶粒(例如，積體電路晶粒)製造期間在其上形成多晶矽絕緣閘極之子微影圖樣。
已藉由可用之微影程序限制用於一半導體晶粒中之絕緣閘極電晶體(例如，亦已知為金屬氧化物半導體場效應電晶體(MOSFET)之絕緣閘極場效應電晶體(IGFET)及絕緣閘極雙極電晶體(IGBT))之圖案化多晶矽絕緣閘極之大小之減小。隨著由形成此等電晶體之微影遮蔽程序中之改良引起的在該半導體晶粒上之此等電晶體之數目增加，與此等不斷減小大小之電晶體一起使用之該等絕緣閘極已不能夠與該等更小電晶體成比例地減小大小。
因此，存在對於在不受可用於製造半導體積體電路之微影程序之限制之情況下減小用於電晶體之圖案化絕緣閘極之大小之一方式之需求。
根據一實施例，一種用於在一半導體積體電路晶粒上形成絕緣多晶矽閘極之方法可包括以下步驟：將一第一介電質沈積於一半導體基板之一面上；在該第一介電質中建立至少一個溝渠向下至該半導體基板之一面；將一間隔物薄膜沈積於該第一介電質上，包含該至少一 個溝渠之壁及一底部；從該第一介電質之一面及曝露該半導體基板之該面之該至少一個溝渠之該底部移除該間隔物薄膜之部分，其中僅間隔物薄膜保留於該至少一個溝渠之該等壁上；將一第二介電質沈積於該第一介電質上方及該至少一個溝渠之該等壁上之該等間隔物薄膜之間且足夠填充在其等之間之一間隔；移除該第一介電質及該第二介電質之一部分直至可曝露於該第一介電質與該第二介電質之間之該等間隔物薄膜之實質上平坦頂部部分；移除在該第一介電質與該第二介電質之間的該等間隔物薄膜直至該半導體基板之該曝露面，藉此在其中留下至少兩個窄通道；在該至少兩個窄通道之底部之該半導體基板之曝露面上生長閘極氧化物；將多晶矽沈積於該第一介電質及該第二介電質之該等面上且沈積至該至少兩個窄通道中；移除在該第一介電質及該第二介電質之該等面上之該多晶矽之部分且移除在該至少兩個窄通道中之該多晶矽之頂部部分；從該半導體基板之該面移除該第一介電質及該第二介電質，留下其上之該多晶矽及閘極氧化物；及將該多晶矽之部分及閘極氧化物之部分分開為用於絕緣閘極電晶體之獨立絕緣閘極。
根據該方法之一進一步實施例，沈積該第一介電質之該步驟可包括：在該半導體基板之該面上將該第一介電質沈積至自約5奈米至約1000奈米之一厚度之步驟。根據該方法之一進一步實施例，建立該至少一個溝渠之該步驟可包括：在該第一介電質中建立具有自約5奈米至約1000奈米之一寬度之該至少一個溝渠之步驟。根據該方法之一進一步實施例，沈積該間隔物薄膜之該步驟可包括：將該間隔物薄膜沈積至自約5奈米至約1000奈米之一厚度之步驟。根據該方法之一進一步實施例，沈積該第二介電質之該步驟可包括：將該第二介電質沈積至自約5奈米至約1000奈米之一厚度之步驟。根據該方法之一進一步實施例，該多晶矽及該等閘極氧化物之寬度可為自約5奈米至約500 奈米。
根據該方法之一進一步實施例，該間隔物薄膜可包括二氧化矽。根據該方法之一進一步實施例，該第一介電質可包括氮化矽。根據該方法之一進一步實施例，該第二介電質可包括氮化矽。
根據該方法之一進一步實施例，將該多晶矽之部分與閘極氧化物分開之該步驟可包括：使用反應性離子蝕刻(RIE)將該多晶矽之部分與閘極氧化物之部分分開之步驟。根據該方法之一進一步實施例，該RIE可為侵蝕性的。根據該方法之一進一步實施例，將該多晶矽之部分與閘極氧化物之部分分開之該步驟可包括在：該多晶矽之該等部分與閘極氧化物之該等部分之間建立通孔之步驟。
根據另一實施例，一種半導體晶粒可包括複數個絕緣閘極電晶體，其中建立該等電晶體之絕緣閘極可包括以下步驟：將一第一介電質沈積於一半導體基板之一面上；在該第一介電質中建立至少一個溝渠向下至該半導體基板之一面；將一間隔物薄膜沈積於該第一介電質上，包含該至少一個溝渠之壁及一底部；從該第一介電質之一面及曝露該半導體基板之該面之該至少一個溝渠之該底部移除該間隔物薄膜之部分，其中僅間隔物薄膜保留於該至少一個溝渠之該等壁上；將一第二介電質沈積於該第一介電質上方及該至少一個溝渠之該等壁上之該等間隔物薄膜之間且足夠填充在其等之間之一間隔；移除該第一介電質及該第二介電質之一部分直至可曝露於該第一介電質與該第二介電質之間之該等間隔物薄膜之實質上平坦頂部部分；移除在該第一介電質與該第二介電質之間的該等間隔物薄膜直至該半導體基板之該曝露面，藉此在其中留下至少兩個窄通道；在該至少兩個窄通道之底部之該半導體基板之曝露面上生長閘極氧化物；將多晶矽沈積於該第一介電質及該第二介電質之該等面上且沈積至該至少兩個窄通道中；移除在該第一介電質及該第二介電質之該等面上之該多晶矽之部分且移 除在該至少兩個窄通道中之該多晶矽之頂部部分；從該半導體基板之該面移除該第一介電質及該第二介電質，留下其上之該多晶矽及閘極氧化物；及將該多晶矽之部分及閘極氧化物之部分分開為用於絕緣閘極電晶體之獨立絕緣閘極。
根據一進一步實施例，該第一介電質可具有自約5奈米至約1000奈米之一厚度。根據一進一步實施例，該至少一個溝渠可具有自約5奈米至約1000奈米之一寬度。根據一進一步實施例，該等間隔物薄膜可具有自約5奈米至約1000奈米之一厚度。根據一進一步實施例，該第二介電質可具有自約5奈米至約1000奈米之一厚度。根據一進一步實施例，該多晶矽及該等閘極氧化物之寬度可為自約5奈米至約500奈米。
根據一進一步實施例，該間隔物薄膜可包括二氧化矽。據一進一步實施例，該第一介電質及該第二介電質可包括氮化矽。
102‧‧‧矽晶圓
104‧‧‧半導體基板(晶粒)/p型基板
204‧‧‧n井區域
206‧‧‧場氧化物(FOX)
208‧‧‧n+ n井接觸件
210‧‧‧p+源極
216‧‧‧p+汲極
218‧‧‧n+汲極
224‧‧‧n+源極
230‧‧‧閘極氧化物
230a‧‧‧閘極氧化物
230b‧‧‧閘極氧化物
230c‧‧‧閘極氧化物
230d‧‧‧閘極氧化物
232‧‧‧多晶矽/多晶矽層
232a‧‧‧多晶矽閘極
232b‧‧‧多晶矽閘極
232c‧‧‧多晶矽閘極
232d‧‧‧多晶矽閘極
312‧‧‧第一介電質/第一介電質層
312a‧‧‧第二介電質/第二介電質層
314‧‧‧溝渠
314a‧‧‧溝渠
314b‧‧‧溝渠
316‧‧‧溝渠之壁
322‧‧‧間隔物薄膜
322a‧‧‧間隔物薄膜
620‧‧‧多晶矽之末端
820‧‧‧多晶矽
822a‧‧‧分開位置
822b‧‧‧分開位置
822c‧‧‧分開位置
822d‧‧‧分開位置
822e‧‧‧分開位置
822f‧‧‧分開位置
1020‧‧‧獨立絕緣多晶矽閘極
1102‧‧‧步驟
1104‧‧‧步驟
1106‧‧‧步驟
1108‧‧‧步驟
1110‧‧‧步驟
1112‧‧‧步驟
1114‧‧‧步驟
1116‧‧‧步驟
1118‧‧‧步驟
1120‧‧‧步驟
1122‧‧‧步驟
1124‧‧‧步驟
藉由結合附圖參考下列描述可獲得本發明之更完全理解，在附圖中：圖1圖解說明包括複數個半導體晶粒之一半導體積體電路晶圓之一示意性平面視圖；圖2圖解說明製造於一半導體基板上之P通道場效應電晶體及N通道場效應電晶體之一示意性正視圖；圖3、圖3A、圖3B及圖3C圖解說明根據本發明之一特定實例實施例之用於在一半導體晶粒上形成絕緣多晶矽閘極之子微影圖樣之半導體製造步驟之示意性正視圖；圖4圖解說明根據本發明之一特定實例實施例之形成於一半導體晶粒上之絕緣多晶矽閘極之複數個子微影圖樣之一示意性平面視圖；圖5圖解說明根據本發明之一特定實例實施例之形成於一半導體 晶粒上之絕緣多晶矽閘極之複數個子微影圖樣之一示意性平面視圖；圖6圖解說明根據本發明之一特定實例實施例之在圖5中所示之絕緣多晶矽閘極經備製以使絕緣多晶矽閘極彼此分開之複數個子微影圖樣之一示意性平面視圖；圖7圖解說明根據本發明之一特定實例實施例之在圖5及圖6中所示之絕緣多晶矽閘極之複數個子微影圖樣之一示意性平面視圖，其中移除該等絕緣多晶矽閘極之部分以使該等絕緣多晶矽閘極彼此分開；圖8圖解說明根據本發明之另一特定實例實施例之形成於一半導體晶粒上具有多種佈線路徑之絕緣多晶矽閘極之複數個子微影圖樣之一示意性平面視圖；圖9圖解說明根據本發明之另一特定實例實施例之如在圖8中所示之在一半導體晶粒上具有多種佈線路徑之絕緣多晶矽閘極經備製分開為獨立絕緣多晶矽閘極之複數個子微影圖樣之一示意性平面視圖；圖10圖解說明根據本發明之另一特定實例實施例之如在圖8及圖9中所示之在一半導體晶粒上具有多種佈線路徑之絕緣多晶矽閘極在分開為獨立絕緣多晶矽閘極之後之複數個子微影圖樣之一示意性平面視圖；圖11及圖11A圖解說明根據本發明之特定實例實施例之用於在一半導體晶粒上形成複數個絕緣多晶矽閘極之一示意性流程圖。
雖然本發明易於以多種修改及替代形式呈現，其之特定實例實施例已在該等圖式中展示且在本文中詳細描述。然而，應理解，特定實例實施例在本文中之描述不旨在將本發明限制於本文揭示之特定形式，而相反，本發明將覆蓋如由隨附申請專利範圍界定之所有修改及等效物。
根據本發明之教示，可使用一間隔物蝕刻程序，在沈積至一半 導體晶粒之一面上之一第一介電質中產生至少一個溝渠，其中可在該至少一個溝渠之底部曝露該半導體晶粒之一部分。可在該第一介電質之一面上(包含該至少一個溝渠之壁)及在該溝渠底部之該半導體晶粒之該曝露部分，沈積一間隔物薄膜至一所要厚度。接著，可從該第一介電質之該面及在該至少一個溝渠之該底部之該半導體晶粒的該曝露部分移除該間隔物薄膜，僅留下在該至少一個溝渠之該等壁上的間隔物薄膜。此可藉由(舉例而言，但非限於)從該第一介電質的該面及在該至少一個溝渠底部曝露之該半導體晶粒的部分蝕刻該間隔物薄膜來完成。接著，可將一第二介電質沈積於該第一介電質、該等溝渠之該等壁上之該等間隔物薄膜及在該至少一個溝渠之該底部曝露之該半導體晶粒的該部分上方，其中可使用該第二介電質來填充該至少一個溝渠之該等壁上之該等間隔物薄膜之間的一間隙。接著，可藉由(舉例而言而非限於)拋光來移除該第二介電質的一部分直至再次曝露該至少一個溝渠之該等壁上之該等間隔物薄膜的頂部部分。
接著，可藉由(舉例而言，但非限於)浸出來移除該間隔物薄膜，其中該浸出程序具有良好選擇性，以便不移除該介電質材料，但從於由先前程序步驟形成之第一介電質壁與第二介電質壁之間保留的窄通道有效移除所有間隔薄膜。然而，輕微蝕刻介電質材料可使此等窄通道之頂部角變圓而可改良其之填充。接著，閘極氧化物可選擇性地生長於在窄通道之底部的曝露半導體基板上。接著，一多晶矽層可沈積於該第一介電質及該第二介電質上方、沈積至該等窄通道中，且沈積於在該等窄通道之該等底部之該等閘極氧化物上方。接著，可藉由(舉例而言，但非限於)蝕刻來移除該多晶矽層，以將其從該第一介電質及該第二介電質之該等頂面移除，且稍微蝕刻入該等窄通道之該等頂部部分中。其後，從該半導體晶粒之該面移除該第一介電質及該第二介電質，其中該多晶矽及閘極氧化物保留於該半導體晶粒之該面 上。
可在合適位置(例如，「破裂」)移除多晶矽之部分，以產生包括閘極氧化物及在閘極氧化物上方之多晶矽的所要絕緣閘極圖樣。溝渠深度有助於判定閘極氧化物及多晶矽之一個尺寸(例如，高度)，且至少一個溝渠之壁上之間隔物薄膜之一厚度判定一第二尺寸(例如，寬度)。藉由多晶矽及閘極氧化物在何處自彼此「破裂」(例如，分開，在其間切斷連接等)來判定多晶矽及閘極氧化物之長度。
現參考圖式示意性地圖解說明特定實例實施例之細節。在該等圖式中之相同元件將由相同元件符號表示，且類似元件將由具有一不同小寫字體字母下標之相同元件符號表示。
參考圖1，圖中描繪包括複數個半導體晶粒之一半導體積體電路晶圓之一示意性平面視圖。一矽晶圓102可劃刻出複數個半導體晶粒104以用於進一步處理，以在複數個半導體晶粒104之每一者上建立平坦電晶體、二極體及導體。在所有電路已製造於複數個半導體晶粒104上之後，晶粒104被切割(分開)且封裝至積體電路(未展示)中。
參考圖2，圖中描繪製造於一半導體基板上之P通道場效應電晶體及N通道場效應電晶體之一示意性正視圖。P通道場效應電晶體及N通道場效應電晶體可製造於一矽半導體基板104上且獨立使用或作為一互補金屬氧化物半導體(CMOS)裝置一起使用。P通道電晶體可包括在一p型基板104中之一n井區域204、一p+源極210、一n+ n井接觸件208、一p+汲極216、一閘極氧化物230a及藉由閘極氧化物230a而與基板104絕緣之一多晶矽閘極232a。N通道電晶體可包括一n+汲極218、一n+源極224、一閘極氧化物230b及藉由閘極氧化物230b從基板104絕緣之一多晶矽閘極232b。可使用場氧化物(FOX)206(例如，二氧化矽)隔離及保護下伏電晶體元件及基板。
參考圖3、圖3A、圖3B及圖3C，圖中描繪根據本發明之一特定實 例實施例之用於在一半導體晶粒上形成絕緣多晶矽閘極之子微影圖樣之半導體製造步驟之示意性正視圖。形成絕緣多晶矽閘極之子微影圖樣之第一步驟(a)展示於圖2中，其中一第一介電質312可沈積於複數個半導體晶粒104之每一者之一表面上。在下一步驟(b)中，第一介電質312可具有在其中蝕刻至一深度之至少一個溝渠314，而在至少一個溝渠底部曝露半導體晶粒104之一部分。至少一個溝渠314可包括壁316及曝露半導體晶粒之一部分之一底部。在步驟(c)中，一間隔物薄膜322可沈積於第一介電質312、壁316及在至少一個溝渠314之底部之半導體晶粒104之曝露部分上方。在步驟(d)中，可選擇性地從第一介電質312之面及半導體晶粒104之曝露部分蝕刻間隔物322，僅留下在至少一個溝渠314之壁316上之間隔物薄膜322。
在步驟(e)中，一第二介電質312a可沈積於第一介電質312之曝露表面及間隔物薄膜322a上方且足夠厚以填充其等之間的間隙。在步驟(f)中，可移除(例如，拋光)第二介電質312a之一部分，足夠深以通過及移除間隔物薄膜322a之圓頂，否則可存在十分難以填充之一凹入輪廓。在步驟(g)中，可藉由(舉例而言而非限於)選擇性濕蝕刻或電漿蝕刻從第一介電質312之壁與第二介電質312a之壁之間移除間隔物薄膜322a，藉此在其中留下超薄通道(例如，溝渠、畦溝或溝槽)。選擇性蝕刻亦可使此等十分窄之通道變圓，其可改良在其中填充材料。在步驟(h)中，閘極氧化物可選擇性地生長於在窄通道底部之曝露半導體基板上。在步驟(i)中，一多晶矽層可沈積於第一介電質312及第二介電質312a上方、沈積至窄通道中且沈積於閘極氧化物230上方。
在步驟(j)中，可藉由(舉例而言而非限於)蝕刻移除多晶矽層232以將其從第一介電質312及第二介電質312a之頂面移除且稍微蝕刻入窄通道之頂部部分中。在步驟(k)中，從半導體晶粒104之面移除第一介電質312及第二介電質312a，其中多晶矽232及閘極氧化物230保留 於其之面上。溝渠314之深度可判定高度，且所沈積之間隔物薄膜322之厚度可判定多晶矽232之厚度。
第一介電質層312可為(舉例而言而非限於)氮化矽。第二介電質層312a可為(舉例而言而非限於)氮化矽。間隔物薄膜322可為(舉例而言而非限於)二氧化矽。閘極氧化物230可為(舉例而言而非限於)二氧化矽。多晶矽232可為(舉例而言而非限於)多晶矽、非晶矽。
第一介電質312之層厚度可為自約5奈米至約1000奈米。第二介電質312a之層厚度可為自約5奈米至約1000奈米。間隔物薄膜322之層厚度可為自約5奈米至約1000奈米。多晶矽232及閘極氧化物230之寬度或厚度可為自約5奈米至約500奈米。
參考圖4及圖5，圖中描繪根據本發明之特定實例實施例之形成於一半導體晶粒中之絕緣多晶矽閘極之複數個子微影圖樣之示意性平面視圖。在如圖3C之步驟(k)中所示移除第一介電質312及第二介電質312a之後，多晶矽232及閘極氧化物230準備好用於進一步處理以分開其等之部分，以形成用於半導體晶粒104之絕緣閘極電晶體之絕緣閘極。在圖5中所示之複數個多晶矽232及閘極氧化物230可有利地用於在一陣列中之複數個絕緣閘極電晶體之製造。
參考圖6，圖中描繪根據本發明之一特定實例實施例之在圖5中所示之絕緣多晶矽閘極經備製以使絕緣多晶矽閘極彼此分開之複數個子微影圖樣之一示意性平面視圖。多晶矽232之末端(由元件符號620表示)將破裂(例如，分開，在其等之間切斷連接等)。末端620可佈線至晶粒104上之一「安全」區域且可使用諸如(舉例而言而非限於)侵蝕性反應性離子蝕刻(RIE)之一移除程序「斷絕」(切割)末端620，其中曝露末端620且保護多晶矽232之其餘部分以免於RIE，例如，被遮蔽。
參考圖7，圖中描繪根據本發明之一特定實例實施例之在圖5及 圖6中所示之絕緣多晶矽閘極之複數個子微影圖樣之一示意性平面視圖，其中移除絕緣多晶矽閘極之部分以使絕緣多晶矽閘極彼此分開。在移除末端620之後，可做出進一步處理以添加導體至絕緣閘極電晶體之元件且用於至其之外部連接。
參考圖8，圖中描繪根據本發明之另一特定實例實施例之形成於一半導體晶粒上之具有多種佈線路徑之絕緣多晶矽閘極之複數個子微影圖樣之一示意性平面視圖。已在上文中更全面地描述如所示之多晶矽232。可預期且在本發明之範疇內，多晶矽820可如許多所要之不同路徑佈線於且組態為用於在半導體晶粒104上之電晶體之絕緣多晶矽閘極。可透過合適遮罩(未展示)及如在圖3、圖3A、圖3B及圖3C中所示之程序步驟及如上文中更全面描述之其之隨附描述之相同或類似程序形成用於建立此圖樣之一溝渠及建立多晶矽820之步驟。
參考圖9，圖中描繪根據本發明之另一特定實例實施例之如在圖8中所示之在一半導體晶粒上具有多種佈線路徑之絕緣多晶矽閘極經備製分開為用於一半導體晶粒104中之電晶體之獨立絕緣多晶矽閘極之複數個子微影圖樣之一示意性平面視圖。多晶矽820可在半導體晶粒104上之多個位置(一般由元件符號822表示)分開(例如，在其間切斷連接)。可使用如一般半導體製造技術者所熟知且具有本發明之益處之通孔型程序來完成此等分開位置822。
參考圖10，圖中描繪根據本發明之另一特定實例實施例之如在圖8及圖9中所示之在一半導體晶粒104上具有多種佈線路徑之絕緣多晶矽閘極分開為獨立多晶矽閘極之後之複數個子微影圖樣之一示意性平面視圖。可在半導體晶粒104之進一步處理期間填充通孔型分開。
參考圖11及圖11A，圖中描繪根據本發明之特定實例實施例之用於在一半導體晶粒中形成絕緣多晶矽閘極之複數個子微影圖樣之一示意性流程圖。在步驟1102中，一第一介電質312可沈積於一半導體基 板(晶粒)104之一面上。在步驟1104中，至少一個溝渠314可蝕刻至第一介電質312中向下至半導體晶粒104之一面。在步驟1106中，可在第一介電質312、至少一個溝渠314之壁及底部上沈積一間隔物薄膜322至一所要厚度。在步驟1108中，可選擇性地從第一介電質312之頂面及半導體晶粒104之曝露部分蝕刻間隔物薄膜322，僅留下在至少一個溝渠314之壁316上的間隔物薄膜322。在步驟1110中，一第二介電質312a可沈積於第一介電質312及至少一個溝渠314之壁上的保留間隔物薄膜322上方，且其足夠厚以填充其等之間的間隙。在步驟1112中，可移除(例如，拋光)第二介電質312a之一部分，其足夠深以通過及移除間隔物薄膜322a之圓頂部，否則可存在十分難以填充之一凹入輪廓。在步驟1114中，可藉由(舉例而言，但非限於)濕蝕刻，從第一介電質312之壁與第二介電質312a之壁之間移除間隔物薄膜322a，藉此在其中留下超薄通道(例如，溝渠、畦溝或溝槽)。在步驟1116中，閘極氧化物230可選擇性地生長於在窄通道底部之曝露半導體基板上。在步驟1118中，多晶矽232之一層可沈積於第一介電質312及第二介電質312a上方、沈積至窄通道中，及沈積於閘極氧化物230上方。在步驟1120中，可(舉例而言，但非限於)蝕刻多晶矽層232以將其從第一介電質312及第二介電質312a之頂面移除，且稍微蝕刻入窄通道之頂部部分中。在步驟1122中，從半導體晶粒104之面移除第一介電質312及第二介電質312a，其中多晶矽232及閘極氧化物230保留於其之面上。在步驟1124中，可分開(例如，在其間切斷連接)多晶矽232之部分及閘極氧化物230之部分，以建立可用於製造於半導體晶粒104上之電晶體裝置之獨立絕緣多晶矽閘極1020。
雖然已描繪、描述且藉由參考本發明之實例實施例界定本發明之實施例，但此等參考不暗示對於本發明之一限制，且無法推斷此等限制。如在相關技術中且具有本發明之益處之一般技術者將想到，可 在形式及功能上對所揭示之標的進行大幅修改、替代及等效物。本發明所描繪及描述之實施例僅係實例，且並不窮盡本發明之範疇。

Claims (12)

  1. 一種用於在一半導體積體電路晶粒上形成絕緣多晶矽閘極(insulated polysilicon gates)之方法，該方法包括以下步驟：藉由以下形成一環形(ring-shaped)絕緣多晶矽閘極陣列：將一第一介電質沈積於一半導體基板之一面(face)上；在該第一介電質中，建立(creating)複數個溝渠向下至該半導體基板之一面；將一間隔物薄膜沈積於該第一介電質上，包含該等溝渠之每一者之壁及一底部；從該第一介電質之一面及曝露該半導體基板之該面之該等溝渠之每一者之該底部移除該間隔物薄膜之部分，其中僅間隔物薄膜保留於該等溝渠之該等壁上；將一第二介電質沈積於該第一介電質上方(over)及該等溝渠之該等壁上之該等間隔物薄膜之間，且足夠填充由其等之間所定義之一間隔；移除該第一介電質及該第二介電質之一部分直至該等間隔物薄膜之實質上平坦頂部部分曝露於該第一介電質與該第二介電質之間；移除在該第一介電質與該第二介電質之間之該等間隔物薄膜直至該半導體基板之該曝露面，藉此在其中留下一環形間隔物薄膜寬度通道(spacer-film-width channels)陣列，各間隔物薄膜寬度通道具有等於該經移除之間隔物薄膜之一厚度之一橫向寬度；生長閘極氧化物於該環形間隔物薄膜寬度通道陣列之底部之該半導體基板之曝露面上；將多晶矽沈積於該第一介電質及該第二介電質之上部面(upper faces)上，且沈積至該環形間隔物薄膜寬度通道陣列中，使得各間隔物薄膜寬度通道完全填充多晶矽直到該通道的一全部高度(full height)之上；移除在該第一介電質及該第二介電質之該等上部面(upper face)上之該多晶矽的部分，且移除在該經完全填充之環形間隔物薄膜寬度通道陣列中之該多晶矽的頂部部分，使得多晶矽之移除減少完全填充的各間隔物膜寬度通道至僅部分被填充，其中在該各間隔物薄膜寬度通道中之剩餘之該多晶矽之頂部面係位於該第一介電質及該第二介電質之該等上部面之下(below)；及從該半導體基板之該面移除該第一介電質及該第二介電質，留下其上之一環形多晶矽閘極陣列，各自由一相應閘極氧化物絕緣；及蝕刻延伸穿過該環形多晶矽閘極陣列之一區域，以將該環形多晶矽閘極陣列分開為用於一絕緣閘極電晶體陣列之一獨立線形(line-shaped)多晶矽閘極陣列。
  2. 如請求項1之方法，其中沈積該第一介電質之該步驟包括：在該半導體基板之該面上將該第一介電質沈積至自約5奈米至約1000奈米之一厚度的步驟。
  3. 如請求項1之方法，其中建立該複數個溝渠之該步驟包括：在該第一介電質中建立具有自約5奈米至約1000奈米之一寬度之該至少一個溝渠的步驟。
  4. 如請求項1之方法，其中沈積該間隔物薄膜之該步驟包括：將該間隔物薄膜沈積至自約5奈米至約1000奈米之一厚度的步驟。
  5. 如請求項1之方法，其中沈積該第二介電質之該步驟包括：將該第二介電質沈積至自約5奈米至約1000奈米之一厚度的步驟。
  6. 如請求項1之方法，其中該多晶矽及該等閘極氧化物之寬度為自約5奈米至約500奈米。
  7. 如請求項1之方法，其中該間隔物薄膜包括二氧化矽。
  8. 如請求項1之方法，其中該第一介電質包括氮化矽。
  9. 如請求項1之方法，其中該第二介電質包括氮化矽。
  10. 如請求項1之方法，其中蝕刻延伸穿過該環形多晶矽閘極陣列之一區域，以將該環形多晶矽閘極陣列分開為一獨立線形多晶矽閘極陣列之該步驟包括：執行一反應性離子蝕刻(RIE)。
  11. 如請求項10之方法，其中該RIE為侵蝕性(aggressive)。
  12. 如請求項1之方法，其中移除在該第一介電質及該第二介電質之該等上部面上之該多晶矽的部分且移除在該至少兩個間隔物薄膜寬度通道中之該多晶矽的頂部部分，使得在該至少兩個間隔物薄膜寬度通道中之剩餘之該多晶矽之頂部面位於該第一介電質及該第二介電質之該等上部面之下之步驟包括蝕刻在該至少兩個間隔物薄膜寬度通道中之該多晶矽至低於該第一介電質及該第二介電質之該等上部面之一深度。
TW103108556A 2013-03-15 2014-03-12 啟用間隔物之多晶矽閘極 TWI625860B (zh)

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