TWI624056B - 連接成二極體之雙極接面電晶體及包含此連接成二極體之雙極接面電晶體的電子電路 - Google Patents
連接成二極體之雙極接面電晶體及包含此連接成二極體之雙極接面電晶體的電子電路 Download PDFInfo
- Publication number
- TWI624056B TWI624056B TW103125778A TW103125778A TWI624056B TW I624056 B TWI624056 B TW I624056B TW 103125778 A TW103125778 A TW 103125778A TW 103125778 A TW103125778 A TW 103125778A TW I624056 B TWI624056 B TW I624056B
- Authority
- TW
- Taiwan
- Prior art keywords
- bipolar junction
- junction transistor
- type
- diode
- region
- Prior art date
Links
- 238000002955 isolation Methods 0.000 claims description 17
- 239000012535 impurity Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 7
- 230000006870 function Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
- H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
- H01L27/0652—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
- H01L27/0664—Vertical bipolar transistor in combination with diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41708—Emitter or collector electrodes for bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/7302—Bipolar junction transistors structurally associated with other devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/10—DRAM devices comprising bipolar components
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Bipolar Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
Abstract
一種連接成二極體之雙極接面電晶體包括具有第一導電性的共集極區;具有第二導電性的共基極區,設置於共集極區上;以及具有第一導電性的複數個射極區,設置於共基極區上,配置成互相隔開且配置成具有島形狀。
Description
本申請案主張2014年2月10日在韓國智慧財產局提出申請之第10-2014-0014897號案的優先權,其完整內容係以參照的方式合併於本文中。
本揭露的各種實施例係關於雙極接面電晶體及包含此雙極接面電晶體的電子電路,以及更尤關於連接成二極體之雙極接面電晶體及包含此連接成二極體之雙極接面電晶體的電子電路。
施加至積體電路的電源電壓可因各種因素而變。電源電壓的變動可能影響積體電路的操作電流,且甚至可能使積體電路故障。因此,設計出不管電源電壓變動而產生固定電壓位準或固定電流量的參考電壓產生器或參考電流產生器,是很重要的。將參考電壓產生器或參考電流產生器的溫度靈敏度最小化,也很是重要的。
可藉由基於矽材料的能隙電壓產生固定電壓而獲得參考電壓。一般而言,參考電壓電路可包括一對
雙極接面電晶體,其具有不同電流密度並且並聯耦接。在此種情況下,當每一個雙極接面電晶體的射極-基極電壓具有正溫度係數時,這對雙極接面電晶體的射極-基極電壓之間的電壓差可具有負溫度係數。若可將正溫度係數及負溫度係數適度控制成具有相同的絕對值,則不管溫度變動,參考電壓電路可產生固定參考電壓。已知這參考電壓接近矽材料在絕對溫度為零(0)度(0K)時的能隙電壓。還有,這參考電壓電路被稱為能隙參考(BGR)電路。已知BGR電路對溫度變動具有穩定性,並且係廣泛用於積體電路中。也就是說,若可將雙極接面電晶體的集極電阻值適度控制成抵銷雙極接面電晶體的正溫度係數及負溫度係數,則不管溫度變動,BGR電路可產生穩定且固定的參考電壓。然而,若在BGR電路中運用雙極接面電晶體,則可能降低BGR電路的積體密度。
各種實施例係關於連接成二極體之雙極接面電晶體及包含此連接成二極體之雙極接面電晶體的電子電路。
根據實施例,連接成二極體之雙極接面電晶體可包括具有第一導電性的共集極區;具有第二導電性的共基極區,設置於共集極區上;以及具有第一導電性的複數個射極區,設置於共基極區上,配置成互相隔開且配置成具有島形狀。
根據實施例,電子電路可包括連接成二極體之雙極接面電晶體。此連接成二極體之雙極接面電晶體
可包括具有第一導電性的共集極區;具有第二導電性的共基極區,設置於共集極區上;以及具有第一導電性的複數個射極區,設置於共基極區上,配置成互相隔開且配置成具有島形狀。
100‧‧‧連接成二極體之雙極接面電晶體
110‧‧‧基板
120‧‧‧N型共集極區
122‧‧‧N型集極接觸區
124‧‧‧N型集極接觸區
130‧‧‧P型共基極區
132‧‧‧P型基極接觸區
134‧‧‧P型基極接觸區
141‧‧‧N型射極區
142‧‧‧N型射極區
143‧‧‧N型射極區
144‧‧‧N型射極區
145‧‧‧N型射極區
146‧‧‧N型射極區
147‧‧‧N型射極區
148‧‧‧N型射極區
149‧‧‧N型射極區
150‧‧‧隔離層
191‧‧‧雙極接面電晶體
192‧‧‧雙極接面電晶體
193‧‧‧雙極接面電晶體
194‧‧‧雙極接面電晶體
195‧‧‧雙極接面電晶體
196‧‧‧雙極接面電晶體
197‧‧‧雙極接面電晶體
198‧‧‧雙極接面電晶體
199‧‧‧雙極接面電晶體
200‧‧‧連接成二極體之雙極接面電晶體
220‧‧‧N型共集極區
230‧‧‧P型共基極區
241‧‧‧N型射極區
242‧‧‧N型射極區
243‧‧‧N型射極區
244‧‧‧N型射極區
245‧‧‧N型射極區
246‧‧‧N型射極區
247‧‧‧N型射極區
248‧‧‧N型射極區
249‧‧‧N型射極區
300‧‧‧連接成二極體之雙極接面電晶體
310‧‧‧基板
320‧‧‧P型共集極區
322‧‧‧P型集極接觸區
324‧‧‧P型集極接觸區
330‧‧‧N型共基極區
332‧‧‧N型基極接觸區
334‧‧‧N型基極接觸區
341‧‧‧P型射極區
342‧‧‧P型射極區
343‧‧‧P型射極區
344‧‧‧P型射極區
345‧‧‧P型射極區
346‧‧‧P型射極區
347‧‧‧P型射極區
348‧‧‧P型射極區
349‧‧‧P型射極區
350‧‧‧隔離層
391‧‧‧雙極接面電晶體
392‧‧‧雙極接面電晶體
393‧‧‧雙極接面電晶體
394‧‧‧雙極接面電晶體
395‧‧‧雙極接面電晶體
396‧‧‧雙極接面電晶體
397‧‧‧雙極接面電晶體
398‧‧‧雙極接面電晶體
399‧‧‧雙極接面電晶體
400‧‧‧連接成二極體之雙極接面電晶體
420‧‧‧P型共集極區
430‧‧‧N型共基極區
441‧‧‧P型射極區
442‧‧‧P型射極區
443‧‧‧P型射極區
444‧‧‧P型射極區
445‧‧‧P型射極區
446‧‧‧P型射極區
447‧‧‧P型射極區
448‧‧‧P型射極區
449‧‧‧P型射極區
500‧‧‧電子電路
510‧‧‧運算放大器
521‧‧‧電阻器
522‧‧‧電阻器
523‧‧‧電阻器
600‧‧‧電子電路
610‧‧‧運算放大器
621‧‧‧電阻器
622‧‧‧電阻器
623‧‧‧電阻器
A‧‧‧節點
B‧‧‧節點
C‧‧‧集極節點
E1‧‧‧第一射極節點
E2‧‧‧第二射極節點
L‧‧‧接觸面
各種實施例將鑑於附圖及附隨的詳細說明而變得更加明顯,其中:第1圖是例示根據實施例之連接成二極體之雙極接面電晶體的布局圖;第2圖是沿著第1圖之線I-I’而取的剖面圖;第3圖是第1圖中所示連接成二極體之雙極接面電晶體的等效電路圖;第4圖是例示根據實施例之連接成二極體之雙極接面電晶體的布局圖;第5圖是根據實施例之連接成二極體之雙極接面電晶體的布局圖;第6圖是沿著第5圖之線II-II’而取的剖面圖;第7圖是第5圖中所示連接成二極體之雙極接面電晶體的等效電路圖;第8圖是例示根據實施例之連接成二極體之雙極接面電晶體的布局圖;第9圖是例示根據實施例之包含連接成二極體之雙極接面電晶體的電子電路的電路圖;以及
第10圖是例示根據實施例之包含連接成二極體之雙極接面電晶體的電子電路的電路圖。
以下的實施例可提供連接成二極體之雙極接面電晶體,並且每一個連接成二極體之雙極接面電晶體都可包括共用單一共集極區的複數個垂直雙極接面電晶體、以及附有複數個分離射極區的單一共基極區。這些連接成二極體之雙極接面電晶體可使用來實現用於在記憶體裝置或非記憶體裝置中產生參考電壓的電路。記憶體裝置可包括動態隨機存取記憶體(DRAM)裝置、靜態隨機存取記憶體(SRAM)裝置、快閃記憶體裝置、磁性隨機存取記憶體(MRAM)裝置、可相變隨機存取記憶體(PcRAM)裝置、電阻性隨機存取記憶體(ReRAM)裝置或鐵電式隨機存取記憶體(FeRAM)裝置。非記憶體裝置可包括運用運算放大器(OP-AMPs)、多級放大器、感測放大器或諸如此類的邏輯裝置。
在以下的實施例中,將了解的是,當稱一元件為置於另一元件「上」、「上方」、「上面」、「底下」、「下方」或「下面」時,其可直接接觸另一個元件、或也可在其之間出現至少一個中介元件。從而,本文中所用「上」、「上方」、「上面」、「底下」、「下方」、「下面」及諸如此類的術語,目的僅在於說明特定實施例,並且用意不在於限制其它實施例。
請參閱第1及2圖,根據實施例的連接成二極體之雙極接面電晶體100可包括複數個並聯耦接的
N-P-N型雙極接面電晶體。該複數個雙極接面電晶體每一者都可具有連接成二極體之結構,其中雙極接面電晶體的基極區和集極區係互相電耦接。具體而言,可將N型共集極區120設置在基板110上方。可將P型共基極區130及N型集極接觸區122與124設置在N型共集極區120上方。N型集極接觸區122與124的雜質濃度可大於N型共集極區120的雜質濃度。可藉由N型共集極區120圍繞P型共基極區130。可在P型共基極區130上方設置複數個N型射極區,例如九(9)個N型射極區141至149,以及P型基極接觸區132與134。N型射極區141至149可在與基板110頂部表面平行之一個方向排列,並且可互相隔開而具有島形狀。P型基極接觸區132與134的雜質濃度可大於P型共基極區130的雜質濃度。
可藉由設置在基板130中的隔離層150,使N型集極接觸區122與124、P型基極接觸區132與134、以及N型射極區141至149互相隔開。也就是說,可在N型集極接觸區122和124、P型基極接觸區132和134、以及N型射極區141至149之間設置隔離層150。例如,隔離層150可為溝槽隔離層。隔離層150可具有約300奈米的厚度。N型集極接觸區122與124、P型基極接觸區132與134、以及N型射極區141至149的深度可為隔離層150厚度之約20%至約40%。例如,當隔離層150的厚度為約300奈米時,N型集極接觸區122與124、P型基極接觸區132與134、以及N型射極區141至149
的深度可為約60奈米至約120奈米。例如,N型射極區141至149每一者與P型共基極區130之間的接觸面積可實質相等。含N型射極區141至149的垂直雙極接面電晶體每一者的電流驅動能力,都可取決於N型射極區141至149每一者與P型共基極區130之間接觸面L的面積。因此,含N型射極區141至149之垂直雙極接面電晶體每一者的電流驅動能力都可實質相等。
可將N型射極區141至149其中一者,例如N型射極區141,電耦接至第一射極節點E1,並且可將其它的N型射極區141至149電耦接至第二射極節點E2。例如,可將耦接至第一射極節點E1之射極區141設置於N型射極區141至149的中央,以便改善含N型射極區141至149之垂直雙極接面電晶體的匹配特性。可將N型集極接觸區122與124以及P型基極接觸區132與134電耦接至集極節點C以實現連接成二極體之結構。
請參閱第3圖,可將九個(9)雙極接面電晶體191至199的所有集極全都電耦接至集極節點C。雙極接面電晶體191至199每一者都可具有互相耦接之集極和基極。因此,雙極接面電晶體191至199每一者都可作用成二極體型雙極接面電晶體。也就是說,可將雙極接面電晶體191至199的所有基極和集極全都耦接至集極節點C。可將雙極接面電晶體191的射極電耦接至第一射極節點E1,以及可將剩餘雙極接面電晶體192至199的射極電耦接至第二射極節點E2。如參照第1及2圖所述,雙極接面電晶體191至199全部都可共用單一基極
(即P型共基極區120)、以及單一集極(即N型共集極區130)。雙極接面電晶體191至199可分別包括九(9)個分離射極,亦即射極區141至149。
請參閱第4圖,根據實施例的連接成二極體之雙極接面電晶體200可包括並聯連接的複數個N-P-N型雙極接面電晶體,且該等N-P-N型雙極接面電晶體每一者都可作用成二極體型雙極接面電晶體,二極體型雙極接面電晶體的基極區及集極區係互相電耦接。也就是說,可在N型共集極區220中設置P型共基極區230,且複數個N型射極區(例如九(9)個N型射極區241至249)可在P型共基極區230中設置成互相隔開。可將N型射極區241至249設置成陣列。例如,N型射極區241至249可排列在與第一方向平行的三列以及與第二方向平行的三行。根據本實施例的連接成二極體之雙極接面電晶體200可與參照第2及3圖所述的連接成二極體之雙極接面電晶體100相同,除了在於N型射極區241至249係設置成陣列。
請參閱第5及6圖,根據實施例的連接成二極體之雙極接面電晶體300可包括複數個並聯耦接的P-N-P型雙極接面電晶體。此複數個雙極接面電晶體每一者都可具有連接成二極體之結構,其中雙極接面電晶體的基極區和集極區係互相電耦接。具體而言,可在基板310上方設置P型共集極區320。當基板310為P型基板時,基板310可充當P型共集極區320。可在P型共集極區320上方設置N型共基極區330及P型集極接
觸區322與324。P型集極接觸區322與324的雜質濃度可大於P型共集極區320的雜質濃度。可藉由P型共集極區320圍繞N型共基極區330。可在N型共基極區330上方設置複數個P型射極區(例如九(9)個P型射極區341至349)以及N型基極接觸區332與334。P型射極區341至349可在與基板310之頂部表面平行的一個方向排列,並且可互相隔開而具有島形狀。N型基極接觸區332與334的雜質濃度可大於N型共基極區330的雜質濃度。
可藉由設置在基板330中的隔離層350使P型集極接觸區322與324、N型基極接觸區332與334、以及P型射極區341至349互相隔開。也就是說,可在P型集極接觸區322和324、N型基極接觸區332和334、以及P型射極區341至349之間設置隔離層350。例如,隔離層350可為溝槽隔離層。隔離層350可具有約300奈米的厚度。P型集極接觸區322與324、N型基極接觸區332與334、以及P型射極區341至349的深度可為隔離層350厚度的約20%至約40%。例如,當隔離層350具有約300奈米的厚度時,P型集極接觸區322和324、N型基極接觸區332和334、以及P型射極區341至349可具有約60奈米至約120奈米的深度。例如,P型射極區341至349每一者與N型共基極區330之間的接觸面積可實質相等。含P型射極區341至349之垂直雙極接面電晶體每一者的電流驅動能力都可取決於P型射極區341至349每一者與N型共基極區330之間接觸面L的面積。因此,含P型射極區341至349之垂直雙極接面電晶體每一者的電流驅動能力都可實質相等。
可將P型射極區341至349其中一者,例如P型射極區341,電耦接至第一射極節點E1,並且可將其它的P型射極區341至349電耦接至第二射極節點E2。例如,可將耦接至第一射極節點E1之射極區341設置於P型射極區341至349的中央,以便改善含P型射極區341至349之垂直雙極接面電晶體的匹配特性。可將P型集極接觸區322與324以及N型基極接觸區332與334電耦接至集極節點C以實現連接成二極體之結構。
請參閱第7圖,可將九個(9)雙極接面電晶體391至399的所有集極全都電耦接至集極節點C。雙極接面電晶體391至399每一者都可具有互相耦接之集極和基極。因此,雙極接面電晶體391至399每一者都可作用成二極體型雙極接面電晶體。也就是說,可將雙極接面電晶體391至399的所有基極和集極全都耦接至集極節點C。可將雙極接面電晶體391的射極電耦接至第一射極節點E1,以及可將剩餘雙極接面電晶體392至399的射極電耦接至第二射極節點E2。如參照第5及6圖所述,雙極接面電晶體391至399全部都可共用單一基極(即N型共基極區320)、以及單一集極(即P型共集極區330)。雙極接面電晶體391至399可分別包括九(9)個分離射極,即射極區341至349。
請參閱第8圖,根據實施例的連接成二極體之雙極接面電晶體400可包括並聯耦接的複數個P-N-P型雙極接面電晶體,且P-N-P型雙極接面電晶體每一者都可作用成二極體型雙極接面電晶體,此二極體型雙極
接面電晶體的基極區和集極區係互相電耦接。也就是說,可在P型共集極區420中設置N型共基極區430,且複數個P型射極區(例如九(9)個P型射極區441至449)可設置在N型共基極區430中而互相隔開。可將P型射極區441至449設置成陣列。例如,P型射極區441至449可排列在與第一方向平行的三列以及與第二方向平行的三行。根據本實施例的連接成二極體之雙極接面電晶體400可與參照第5及6圖所述的連接成二極體之雙極接面電晶體300相同,除了P型射極區441至449係設置成陣列。
請參閱第9圖,電子電路500可為能隙參考(BGR)電路。電子電路500可包括三個電阻器521、522和523、運算放大器510、以及連接成二極體之雙極接面電晶體100。連接成二極體之雙極接面電晶體100可為參照第1、2及3圖所述者。在將電源電壓VDD施加至N-P-N型雙極接面電晶體191至199的集極時,集極電流可流經N-P-N型雙極接面電晶體191至199。結果,可在N-P-N型雙極接面電晶體191的第一射極節點E1與基極(即電源電壓VDD)之間產生第一射極-基極電壓VBE1,且可在N-P-N型雙極接面電晶體192至199的第二射極節點E2與基極(即電源電壓VDD)之間產生第二射極-基極電壓VBE2。
可將雙極接面電晶體191的第一射極節點E1耦接至電阻器521於節點A的第一節點,且可將雙極接面電晶體192至199的第二射極節點E2耦接至電阻器
523的第一節點。可於節點A將電阻器521的第一節點與運算放大器510的正輸入節點互相耦接。可於節點B將電阻器523的第二節點、電阻器522的第一節點、以及運算放大器510的負輸入節點共同電耦接。可將電阻器521與522的第二節點電耦接至運算放大器510的輸出節點Vout。
運算放大器510可正規化節點A與B的電壓,以透過其輸出節點Vout將能隙電壓輸出。可將能隙電壓(亦即能隙參考電壓VREF)表示成下列的方程式1。
在方程式1中,「VDD」表示電源電壓,「VBE2」表示介於雙極接面電晶體192至199之第二射極節點E2與基極之間的電壓,「R2」表示電阻器522的電阻值、「R3」表示電阻器523的電阻值,「VT」表示代表正溫度係數的「kT/q」,以及「n」表示並聯耦接至第二射極節點E2的雙極接面電晶體192至199的數量。
由方程式1可看出的是,可藉由將具有負溫度係數的電壓分量VBE2加至具有正溫度係數的電壓分量VT而獲得能隙參考電壓VREF。在此種情況下,當適度調整電阻值R2及R3使得負溫度係數及正溫度係數具有相等的絕對值時,不管溫度變動,能隙參考電壓VREF可具有固定值。
請參閱第10圖,電子電路600可為能隙參考(BGR)電路。電子電路600可包括三個電阻器621、622和623、運算放大器610、以及連接成二極體之雙極接面電晶體300。連接成二極體之雙極接面電晶體300可為參照第5、6及7圖所述者。可將雙極接面電晶體391至399的所有集極和基極都電耦接至接地電壓VSS。於第一射極節點E1與接地電壓VSS之間施加偏壓時,第一集極電流可流經雙極接面電晶體391,以在P-N-P型雙極接面電晶體391的第一射極節點E1與基極、接地電壓VSS之間產生第一射極-基極電壓(VBE1)。再者,於第二射極節點E2與接地電壓VSS之間施加偏壓時,第二集極電流可流經雙極接面電晶體392至399,以在P-N-P型雙極接面電晶體392至399的第二射極節點E2與基極(即接地電壓VSS)之間產生第二射極-基極電壓(VBE2)。
可將雙極接面電晶體391的第一射極節點E1耦接至電阻器621於節點A的第一節點,且可將雙極接面電晶體392至399的第二射極節點E2耦接至電阻器623的第一節點。可於節點A將電阻器621的第一節點與運算放大器610的正輸入節點互相耦接。可於節點B將電阻器623的第二節點、電阻器622的第一節點、以及運算放大器610的負輸入節點共同電耦接。可將電阻器621與622的第二節點電耦接至運算放大器610的輸出節點Vout。
運算放大器610可正規化節點A與B的電壓,以透過其輸出節點Vout將能隙電壓輸出。可將能隙電壓(即能隙參考電壓VREF)表示成下列的方程式2。
在方程式2中,「VBE2」表示介於雙極接面電晶體392至399之第二射極節點E2與基極之間的電壓,「R2」表示電阻器622的電阻值、「R3」表示電阻器623的電阻值,「VT」表示代表正溫度係數的「kT/q」,以及「n」表示並聯耦接至第二射極節點E2的雙極接面電晶體392至399的數量。
由方程式2可看出的是,可藉由將具有負溫度係數的電壓分量VBE2加至具有正溫度係數的電壓分量VT而獲得能隙參考電壓VREF。在此種情況下,當適度調整電阻值R2及R3使得負溫度係數及正溫度係數具有相等的絕對值時,不管溫度變動,能隙參考電壓VREF可具有固定值。
為了例示的目的,已將實施例揭示於上述說明。所屬領域技術人員將了解各種修改、增添及取代是可行的。
Claims (16)
- 一種連接成二極體之雙極接面電晶體,包含:具有第一導電性的共集極區;具有第二導電性的共基極區,設置於該共集極區上;以及具有該第一導電性的複數個射極區,設置於該共基極區上,配置成互相隔開,並且配置成具有島形狀,其中該共集極區及該共基極區係電耦接至集極節點。
- 如請求項1之連接成二極體之雙極接面電晶體,其中該複數個射極區係配置成於一個方向。
- 如請求項2之連接成二極體之雙極接面電晶體,其中該複數個射極區之第一射極區係耦接至第一射極節點,而該複數個射極區之其他射極區則耦接至第二射極節點。
- 如請求項3之連接成二極體之雙極接面電晶體,其中該第一射極區係設置於該複數個射極區的中央。
- 如請求項2之連接成二極體之雙極接面電晶體,更包含具有該第二導電性的基極接觸區,設置於該共基極區上。
- 如請求項5之連接成二極體之雙極接面電晶體,其中該基極接觸區的雜質濃度大於該共基極區之雜質濃度。
- 如請求項5之連接成二極體之雙極接面電晶體,其中該基極接觸區包括第一基極接觸區和第二基極接觸區;以及 其中該複數個射極區係設置於該第一與第二基極接觸區之間。
- 如請求項2之連接成二極體之雙極接面電晶體,更包含具有該第一導電性的集極接觸區,設置於該共集極區上。
- 如請求項8之連接成二極體之雙極接面電晶體,其中該集極接觸區的雜質濃度大於該共集極區的雜質濃度。
- 如請求項8之連接成二極體之雙極接面電晶體,其中該集極接觸區包括第一基極接觸區和第二基極接觸區;以及其中該複數個射極區係設置於該第一與第二基極接觸區之間。
- 如請求項1之連接成二極體之雙極接面電晶體,更包含設置於該複數個射極區之間的隔離層。
- 如請求項11之連接成二極體之雙極接面電晶體,其中該複數個射極區具有該隔離層厚度的約20%至約40%的深度。
- 如請求項1之連接成二極體之雙極接面電晶體,其中該第一導電性為N型導電性,並且該第二導電性為P型導電性。
- 如請求項1之連接成二極體之雙極接面電晶體,其中該第一導電性為P型導電性,並且該第二導電性為N型導電性。
- 如請求項1之連接成二極體之雙極接面電晶體,其中 該複數個射極區係排列在與第一方向平行的列以及與垂直於該第一方向之第二方向平行的行。
- 如請求項1之連接成二極體之雙極接面電晶體,其中介於該複數個射極區之每一者與該共基極區之間的接觸面積係實質相等。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020140014897A KR102146871B1 (ko) | 2014-02-10 | 2014-02-10 | 다이오드 연결형 바이폴라 접합 트랜지스터 및 이를 이용한 전자회로 |
??10-2014-0014897 | 2014-02-10 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201532270A TW201532270A (zh) | 2015-08-16 |
TWI624056B true TWI624056B (zh) | 2018-05-11 |
Family
ID=53775616
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW103125778A TWI624056B (zh) | 2014-02-10 | 2014-07-29 | 連接成二極體之雙極接面電晶體及包含此連接成二極體之雙極接面電晶體的電子電路 |
Country Status (3)
Country | Link |
---|---|
US (2) | US9490251B2 (zh) |
KR (1) | KR102146871B1 (zh) |
TW (1) | TWI624056B (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8582359B2 (en) * | 2010-11-16 | 2013-11-12 | Zeno Semiconductor, Inc. | Dual-port semiconductor memory and first-in first-out (FIFO) memory having electrically floating body transistor |
US10533324B2 (en) * | 2017-11-30 | 2020-01-14 | Alabama Metal Industries Corporation | Below top of wall ventilation screed device and assembly |
CN108281480B (zh) * | 2018-02-09 | 2022-03-04 | 哈尔滨工业大学 | 一种同时产生电离和位移缺陷信号的器件及其制备方法 |
US11923442B2 (en) * | 2019-07-26 | 2024-03-05 | Texas Instruments Incorporated | Bipolar transistor with segmented emitter contacts |
CN110600544A (zh) * | 2019-09-04 | 2019-12-20 | 山东奥天电子科技有限公司 | 高性能、宽安全工作区、高可靠性晶体管 |
US11290666B2 (en) * | 2020-05-20 | 2022-03-29 | Pixart Imaging Incorporation | Multi-beta pixel circuit and image sensor circuit using same |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6225867B1 (en) * | 1997-12-23 | 2001-05-01 | Nortel Networks Limited | Protection scheme for multi-transistor amplifiers |
TW200536259A (en) * | 2004-04-23 | 2005-11-01 | Faraday Tech Corp | Bandgap reference circuit |
US7847374B1 (en) * | 2007-07-06 | 2010-12-07 | Chih-Hsin Wang | Non-volatile memory cell array and logic |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3612089B2 (ja) * | 1994-03-22 | 2005-01-19 | 株式会社ルネサステクノロジ | バンドギャップ基準電源装置 |
JP3367500B2 (ja) * | 2000-03-15 | 2003-01-14 | 日本電気株式会社 | 半導体装置 |
JP2003258105A (ja) * | 2002-02-27 | 2003-09-12 | Ricoh Co Ltd | 基準電圧発生回路及びその製造方法、並びにそれを用いた電源装置 |
US20120068627A1 (en) * | 2010-09-20 | 2012-03-22 | Brooks Timothy W | Temperature compensated led constant current source |
CN102323847B (zh) * | 2011-07-29 | 2013-11-20 | 中国电子科技集团公司第二十四研究所 | 基于温度补偿的电压基准电路 |
-
2014
- 2014-02-10 KR KR1020140014897A patent/KR102146871B1/ko active IP Right Grant
- 2014-07-02 US US14/322,775 patent/US9490251B2/en active Active
- 2014-07-29 TW TW103125778A patent/TWI624056B/zh active
-
2016
- 2016-10-07 US US15/288,326 patent/US9806073B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6225867B1 (en) * | 1997-12-23 | 2001-05-01 | Nortel Networks Limited | Protection scheme for multi-transistor amplifiers |
TW200536259A (en) * | 2004-04-23 | 2005-11-01 | Faraday Tech Corp | Bandgap reference circuit |
US7847374B1 (en) * | 2007-07-06 | 2010-12-07 | Chih-Hsin Wang | Non-volatile memory cell array and logic |
Also Published As
Publication number | Publication date |
---|---|
TW201532270A (zh) | 2015-08-16 |
US20170025409A1 (en) | 2017-01-26 |
US9490251B2 (en) | 2016-11-08 |
KR102146871B1 (ko) | 2020-08-21 |
US20150228643A1 (en) | 2015-08-13 |
US9806073B2 (en) | 2017-10-31 |
KR20150094072A (ko) | 2015-08-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI624056B (zh) | 連接成二極體之雙極接面電晶體及包含此連接成二極體之雙極接面電晶體的電子電路 | |
JP4873442B2 (ja) | 半導体集積回路装置 | |
US6933769B2 (en) | Bandgap reference circuit | |
US20060046408A1 (en) | Semiconductor integrated device | |
US6310799B2 (en) | Negative resistance device | |
CN109196584A (zh) | 感测放大器构造 | |
US12072726B2 (en) | Voltage reference circuit and method for providing reference voltage | |
JP2007311448A5 (zh) | ||
US9536886B2 (en) | CMOS compatible resonant interband tunneling cell | |
JP2016134455A5 (zh) | ||
JP2538170B2 (ja) | 半導体装置 | |
JPS5842556B2 (ja) | 半導体記憶装置 | |
US4346458A (en) | I2 L Monolithically integrated storage arrangement | |
US9317053B2 (en) | Voltage regulator for a flash memory | |
JP5828877B2 (ja) | 半導体装置 | |
JPH08125122A (ja) | 半導体装置 | |
JPH0222856A (ja) | 電源回路及びその電源回路用の半導体集積回路装置 | |
US12088286B2 (en) | Temperature sensors | |
TW202201722A (zh) | 含有垂直堆疊主動絕緣體上覆矽裝置的帶隙參考電路 | |
US12119274B2 (en) | Latch-up test structure | |
US20210255656A1 (en) | Voltage reference circuit and method for providing reference voltage | |
US20230041116A1 (en) | Latch-up test structure | |
KR101716434B1 (ko) | 반도체 장치 | |
TWI503954B (zh) | 半導體裝置 | |
JP2002057219A (ja) | 半導体集積回路 |