TWI620257B - 引線接合墊系統及方法 - Google Patents

引線接合墊系統及方法 Download PDF

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Publication number
TWI620257B
TWI620257B TW104134289A TW104134289A TWI620257B TW I620257 B TWI620257 B TW I620257B TW 104134289 A TW104134289 A TW 104134289A TW 104134289 A TW104134289 A TW 104134289A TW I620257 B TWI620257 B TW I620257B
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Taiwan
Prior art keywords
width
copper trace
wire bonding
unplated
bonding pad
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TW104134289A
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English (en)
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TW201603154A (zh
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孫衛明
彼得 約瑟夫 二世 札帕帝
邵宏曉
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西凱渥資訊處理科技公司
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    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10—Electroplating with more than one layer of the same or of different metals
    • C25D5/12—Electroplating with more than one layer of the same or of different metals at least one layer being of nickel or chromium
    • C—CHEMISTRY; METALLURGY
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    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means
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    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/06—Wires; Strips; Foils
    • C25D7/0607—Wires
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Abstract

為了減少由高射頻(RF)損耗電鍍(諸如，Ni/Pd/Au電鍍)所引起之RF損耗，在一些實施例中，對焊料遮罩重組態以防止引線接合區域之各邊緣及側壁遭到電鍍。使引線接合區域之各邊緣及側壁未遭高RF損耗電鍍(諸如，Ni/Pd/Au電鍍)，便可為RF電流提供圍繞高電阻率材料流動之路徑，如此便減少了由高電阻率電鍍材料所引起之RF信號損耗。

Description

引線接合墊系統及方法
本發明大體而言係關於積體電路封裝之領域，且更特定言之，係關於射頻(RF)積體電路(IC)的封裝所使用之引線接合墊的形成系統及方法。
如一般熟習積體電路(IC)製造技術者已知，將矽或其他半導體晶圓製造成積體電路(IC)。IC接合且電連接至具有介電質層及金屬跡線之載體或基板，且封裝待用。表面電鍍材料電鍍至銅跡線之頂層上以在IC與基板之間提供電連接點，從而允許IC與外界介接。傳統上，鎳/金(Ni/Au)為RFIC產品之標準表面電鍍材料，且在某些情形下，RFIC引線接合至電鍍於基板之表面上之Ni/Au引線接合墊以形成RFIC與其封裝之電連接。然而，金價之升高增加了由Ni/Au表面電鍍所引起之封裝成本。
本發明揭示藉由使用用於RFIC產品之鎳/鈀/金(Ni/Pd/Au)表面電鍍材料來減少RFIC封裝之成本之系統及方法。為了降低成本，Ni/Pd/Au表面電鍍中之金層比Ni/Au表面電鍍中之金層薄。然而，歸因於薄的鈀層及薄的金層以及鎳之鐵磁性質，Ni/Pd/Au具有遠高於Ni/Au之射頻薄層電阻。此情形造成有效電流薄層厚度減少且RF信號上之電流擁擠增加，且在一些實施例中，可導致RF信號穿過Ni/Pd/Au 電鍍表面而產生之RF損耗大於RF信號穿過Ni/Au電鍍表面而產生之RF損耗。此等損耗可衝擊產品效能及良率。
本發明揭示用於減少由RFIC之較低成本之Ni/Pd/Au表面電鍍所引起的RF損耗之其他系統及方法。在設計佈局之一些實施例中，引線接合區域中之RF線路/跡線表面、邊緣及側壁可執行電鍍製程且因此以Ni/Pd/Au表面修飾層電鍍。歸因於對穿過遭電鍍之引線接合區域之RF電流之表皮效應及渦流效應，大部分RF電流在遭電鍍之引線接合區域之跡線邊緣及側壁上流動。因為大部分RF電流在跡線邊緣及側壁上流動，所以對該等跡線邊緣及該等側壁進行電鍍較多地造成RF損耗。為了減少RF損耗，一些實施例重組態焊料遮罩以覆蓋引線接合區域中之跡線邊緣及側壁，以使得該等跡線邊緣及該等側壁未以Ni/Pd/Au表面修飾層電鍍。在引線接合區域周圍未遭Ni/Pd/Au電鍍的銅跡線邊緣及側壁對Ni/Pd/Au引線接合墊周圍之RF電流提供低電阻路徑且因此減少由RFIC基板之Ni/Pd/Au表面電鍍所引起之RF信號損耗。
某些實施例係關於一種製造射頻積體電路(RFIC)模組之方法，該方法包括提供具有至少一個銅跡線之一基板，該銅跡線具有一引線接合表面。該方法進一步包括在該銅跡線之該接合表面正上方形成對於一引線接合墊之一焊料遮罩開口，該引線接合墊具有至少一條邊緣及至少一個側壁。該方法進一步包括：在該引線接合墊之該至少一條邊緣及該至少一個側壁正上方形成焊料遮罩；以一鎳層電鍍該銅跡線；以一鈀層電鍍該鎳層；及以一金層電鍍該鈀層以形成一鎳/鈀/金引線接合墊。該鎳/鈀/金引線接合墊之該至少一條邊緣及該至少一個側壁未遭該鎳層、該鈀層及該金層電鍍。
根據數個實施例，本發明係關於一種用於射頻積體電路(RFIC)模組之引線接合墊。該引線接合墊包括一鎳層，該鎳層電鍍於一銅跡線 之一引線接合表面上方，該銅跡線形成於一RFIC模組之一基板之一上表面上。該引線接合墊進一步包括：一鈀層，該鈀層電鍍於該鎳層上方；及一金層，該金層電鍍於該鈀層上方。該引線接合墊具有：一引線接合區域；與該引線接合區域鄰接之至少一條邊緣；及與該至少一條邊緣鄰接之至少一個側壁，該至少一條邊緣及該至少一個側壁未遭該鎳層、該鈀層及該金層電鍍。
根據各種實施例，一種用於製造射頻積體電路(RFIC)模組之設備包括：用於提供具有至少一個銅跡線之一基板之構件，該銅跡線具有一引線接合表面；及用於在該銅跡線之該接合表面正上方形成對於一引線接合墊之一焊料遮罩開口之構件，該引線接合墊具有至少一條邊緣及至少一個側壁。該設備進一步包括：用於在該引線接合墊之該至少一條邊緣及該至少一個側壁正上方形成焊料遮罩之構件；用於以一鎳層電鍍該銅跡線之構件；用於以一鈀層電鍍該鎳層之構件；及用於以一金層電鍍該鈀層以形成一鎳/鈀/金引線接合墊之構件。該鎳/鈀/金引線接合墊之該至少一條邊緣及該至少一個側壁未遭該鎳層、該鈀層及該金層電鍍。
出於概述本發明之目的，已在本文中描述本發明之某些態樣、優點及新穎特徵。應理解，未必可根據本發明之任何特定實施例達成所有此等優點。因此，可按照達成或最佳化如本文中所教示之一個優點或一群組之優點的方式來體現或實行本發明而未必達成如本文中所教示或建議之其他優點。
100‧‧‧積體電路(IC)模組
102‧‧‧射頻積體電路(RFIC)
104‧‧‧銅跡線/導體
106‧‧‧引線接合墊
106a‧‧‧引線接合墊
106b‧‧‧引線接合墊
108‧‧‧接合引線
110‧‧‧側壁
112‧‧‧邊緣
114‧‧‧引線接合區域
116‧‧‧基板
302‧‧‧鎳層
304‧‧‧鈀層
306‧‧‧金層
400‧‧‧射頻積體電路(RFIC)模組
402‧‧‧射頻積體電路(RFIC)
404‧‧‧銅跡線/導體
406‧‧‧引線接合墊
406a‧‧‧引線接合墊
406b‧‧‧引線接合墊
410‧‧‧側壁
412‧‧‧邊緣
414‧‧‧引線接合區域
416‧‧‧基板
602‧‧‧鎳層
604‧‧‧鈀層
606‧‧‧金層
圖1說明根據某些實施例的包含引線接合墊之例示性IC模組之放大部分。
圖2說明用於形成引線接合墊之例示性程序之流程圖。
圖3說明根據一實施例的圖1之IC模組上之Ni/Pd/Au引線接合墊的 橫截面。
圖4說明根據某些實施例的包含引線接合墊之例示性RFIC模組之放大部分。
圖5說明根據某些實施例的用於形成Ni/Pd/Au引線接合墊之例示性程序之流程圖。
圖6說明根據一實施例的圖4之RFIC模組上之Ni/Pd/Au引線接合墊的橫截面。
圖7為根據某些實施例的比較具有邊緣/側壁曝露表面及邊緣/側壁電鍍表面之跡線之RF損耗的曲線圖。
圖8A至圖8F說明具有曝露於電鍍之最小化之邊緣及側壁的引線接合區域之例示性佈局。
現將參看下文概述之圖式來描述系統及方法之特徵。遍及該等圖式，重複使用元件符號以指示所參考之元件之間的一致性。該等圖式、相關聯之描述及具體實施經提供以說明本發明之實施例且並不限於本發明之範疇。
引線接合為一種用於將電路裝置(例如，積體電路(IC)晶粒)連接至封裝之下一層級之技術。此等電路裝置大體包含複數個小的導電導線/墊，此等導電導線/墊例如藉由球形接合、楔形接合或類似者電連接至嵌入於裝置封裝或基板中之導體上之引線接合墊。該基板上之引線接合墊在該IC與該基板之間提供電連接，從而允許該IC與外界介接。在任一類型之引線接合中，使用熱、壓力及超音波能量之某一組合使引線在兩端附接以形成焊接。
複數個銅圖案形成於電連接至該等電路圖案之基板上，且填料(諸如，介電質)填充於該等銅圖案之間以使得該銅圖案之上表面曝露。然而，裸的銅不易焊接或接合且需要以便於焊接或接合之材料電 鍍。不應為可焊接/接合之區域以一材料覆蓋以抵抗電鍍。大體而言，焊料遮罩指充當遮罩且防止電鍍材料黏接至所遮罩之銅跡線之聚合物塗層。表面電鍍材料電鍍至所曝露之銅跡線之頂層上以提供引線接合墊。在一些應用中，引線接合墊適合於在主動電路正上方進行引線接合以避免損壞易碎裝置且減低電源積體電路之金屬電阻。
圖1說明根據一實施例的IC模組100之一部分，該IC模組100包含IC 102、基板116、銅跡線104、引線接合墊106a及106b，以及接合引線108。該IC經由引線108而引線接合至引線接合墊106。在所說明之實施例中，引線接合墊106a為6引線式引線接合墊且引線接合墊106b為3引線式引線接合墊。在其他實施例中，可附接至引線接合墊106的引線108的數目可以不同。引線接合墊106包含接合區域114、側壁110及邊緣112。
圖2說明用於形成引線接合墊之例示性程序200之流程圖。結合圖1中所說明之實施例來描述程序200。狀態202始於以介電質層及導體104(包括在基板116之上表面上之跡線104)形成基板116，以形成電路路徑，如一般熟習半導體製造技術者已知。
在狀態204處，程序200將焊料遮罩塗覆至將保持未遭電鍍材料電鍍之IC模組100之彼等區域，如一般熟習半導體製造技術者已知。焊料遮罩開口界定該電鍍材料將黏接至的該等區域。在一些實施例中，該焊料遮罩開口將引線接合墊106之引線接合區域114、側壁110及邊緣112曝露於該電鍍材料。在其他實施例中，跡線104及引線接合墊106之引線接合區域114、側壁110及邊緣112可執行電鍍製程。
在狀態206處，以該電鍍材料電鍍銅跡線104之所曝露之區域(未遭焊料遮罩覆蓋)，以形成引線接合墊106，如一般熟習半導體製造技術者已知。
在一實施例中，該電鍍材料為鎳/金(Ni/Au)。在狀態206處，鎳 層電鍍於銅跡線104上方且金層電鍍於該鎳層上方。電鍍技術之實例包括(例如)浸漬電鍍沈積、電解電鍍、無電極電鍍及類似者。
在一實施例中，該銅跡線之厚度介於約5微米與約50微米之間，且較佳為約20微米。Ni/Au電鍍中之鎳層之厚度介於約2.5微米與約7.6微米之間，且更佳介於約5微米與約7微米之間。金層之厚度為約0.7 +/- 0.2微米，且更佳為約0.5 +/- 0.1微米。
傳統上，Ni/Au為用於射頻積體電路(RFIC)產品之標準表面電鍍材料。射頻(RF)為在約30kHz至約300GHz之範圍中的振盪速率。在一實施例中，RFIC 102引線接合至電鍍於基板116之表面上之Ni/Au引線接合墊106以形成RFIC 102與其封裝之電連接。然而，金價之升高增加了由Ni/Au表面電鍍所引起之封裝成本。
為了減少封裝成本，將鎳/鈀/金(Ni/Pd/Au)電鍍材料用於形成RFIC之引線接合墊。在一實施例中，RFIC 102引線接合至電鍍於基板116之表面上之Ni/Pd/Au引線接合墊106以形成RFIC 102與其封裝之電連接。Ni/Pd/Au電鍍使用少於Ni/Au電鍍材料的金，且，隨著金價升高，Ni/Pd/Au電鍍之成本有利地低於Ni/Au電鍍材料。
圖3說明根據一實施例的基板116之表面上之Ni/Pd/Au引線接合墊106的橫截面。Ni/Pd/Au引線接合墊106包含鎳層302、鈀層304及金層306。
參看圖2及圖3，在狀態206處，鎳層302電鍍於銅跡線104上方；鈀層304電鍍於鎳層302上方；且金層306電鍍於鈀層304上方。電鍍技術之實例包括(例如)浸漬電鍍沈積、電解電鍍、無電極電鍍及類似者。
在圖3中所說明之一實施例中，銅跡線104之高度HCu介於約5微米與約50微米之間，且較佳為20微米。鎳層302之高度HNi介於約2.5微米與約7.6微米之間，且更佳介於約5微米與約7微米之間。鈀層304之 高度HPd為約0.09 +/- 0.06微米，且更佳為約0.1 +/- 0.01微米。金層306之高度HAu為約0.10 +/- 0.05微米，且更佳為約0.1 +/- 0.01微米。
然而，歸因於薄的鈀層304、薄的金層306及鎳層302之鐵磁性質，Ni/Pd/Au電鍍表面在射頻下具有高於Ni/Au電鍍表面的薄層電阻。薄層電阻適用於二維系統，其中，諸如用於半導體之表面修飾電鍍之薄膜被視為二維實體。其類似於三維系統中之電阻率。在使用術語「薄層電阻」時，電流必須沿著薄層之平面流動，而非垂直於薄層之平面。
在上文描述之Ni/Au引線接合墊實施例中，Ni/Au之薄層電阻在2GHz下為約30mΩ/sq，而在上文描述且圖3中說明之Ni/Pd/Au引線接合墊實施例中，Ni/Pd/Au之薄層電阻在2GHz下為約150mΩ/sq。因此，在一實施例中，藉由以Ni/Pd/Au電鍍材料代替Ni/Au電鍍材料來電鍍引線接合墊106可導致額外的RF損耗。而此情形可衝擊產品效能及良率。在一些實施例中，Ni/Pd/Au電鍍表面可潛在地將RF損耗增加約0.1dB至約0.4dB，或等效地，將功率效率衝擊約1%至約4%。
另外，振盪信號經受表皮效應。表皮效應為交流電流將自身分配於導體內以使得導體表面附近的電流密度高於導體核心處之電流密度的趨勢。亦即，電流傾向於在稱作表皮深度之平均深度處在導體之表皮處流動。表皮效應引起導體之有效電阻隨著電流頻率而增加，此係因為導體的許多部分攜載極少電流。表皮效應係歸因於由交流電流誘發之渦流。舉例而言，隨著信號之頻率增加至RF頻率，表皮深度降低。另外，渦流亦引起交流RF電流在導體之邊緣處擁擠。因此，RF電流之大部分在導體104之邊緣及側壁上行進。
圖4說明根據一實施例的RFIC模組400之放大部分，該RFIC模組400包含RFIC 402、基板416、銅跡線404、引線接合墊406及接合引線108。RFIC 402經由接合引線108引線接合至引線接合墊406。在所說 明之實施例中，引線接合墊406a為6引線式引線接合墊且引線接合墊406b為3引線式引線接合墊。在其他實施例中，可附接至引線接合墊406的引線108的數目可以不同(諸如，1個、2個、3個、4個、5個或多於6個)。引線接合墊406包含接合區域414、側壁410及邊緣412。
為了減少RF信號損耗，可藉由製造程序將Ni/Pd/Au引線接合墊406限於接合區域414內，從而使側壁410及邊緣412未遭Ni/Pd/Au電鍍材料電鍍。大部分RF電流穿過未被電鍍的邊緣及側壁，此等未被電鍍的邊緣及側壁圍繞著遭電鍍之引線接合區域414，而不再如圖1及圖3所說明地穿過遭電鍍的邊緣412及側壁410。因此，RF損耗減少。
圖5說明根據一實施例的用於形成Ni/Pd/Au引線接合墊406之例示性程序500之流程圖。結合圖4中所說明之實施例來描述程序500。在狀態502處，以介電質層及導體404(包括在基板416之上表面上之跡線404)形成基板416，以形成電路路徑，如一般熟習半導體製造技術者已知。
在狀態503處，在一實施例中，重組態焊料遮罩以使其覆蓋引線接合墊406之邊緣412及側壁410。在另一實施例中，重組態焊料遮罩以使其覆蓋跡線404、及引線接合墊406之邊緣412及側壁410。焊料遮罩開口覆蓋引線接合區域414，如此，引線接合區域414便可執行電鍍製程，但邊緣412及側壁410不可執行電鍍製程。在一實施例中，焊料遮罩對邊緣412之覆蓋寬度應至少寬於焊料遮罩開口對準容差。在另一實施例中，焊料遮罩對邊緣412之覆蓋寬度為約10微米至200微米，且較佳為50微米至100微米。
在狀態504處，程序500將所重組態之焊料遮罩塗覆至RFIC模組400，如一般熟習半導體製造技術者已知。
在狀態506處，程序500以Ni/Pd/Au電鍍材料電鍍RFIC模組400以形成引線接合墊406，如一般熟習半導體製造技術者已知。電鍍技術 之實例包括(例如)浸漬電鍍沈積、電解電鍍、無電極電鍍及類似者。
圖6說明根據一實施例的基板416之表面上之Ni/Pd/Au引線接合墊406之橫截面圖。Ni/Pd/Au引線接合墊406包含鎳層602、鈀層604及金層606。如圖6中所說明，Ni/Pd/Au引線接合墊406之邊緣412及側壁410未遭Ni/Pd/Au電鍍。
參看圖5及圖6，鎳層602電鍍於銅跡線404上方，鈀層604電鍍於鎳層602上方，且金層606電鍍於鈀層604上方。電鍍技術之實例包括(例如)浸漬電鍍沈積、電解電鍍、無電極電鍍及類似者。
在圖6中所說明之一實施例中，銅跡線404之高度HCu介於約5微米與約50微米之間，且較佳為20微米。鎳層602之高度HNi介於約2.5微米與約7.6微米之間，且更佳介於約5微米與約7微米之間。鈀層604之高度HPd為約0.09 +/- 0.06微米，且更佳為約0.1 +/- 0.01微米。金層606之高度HAu為約0.10 +/- 0.05微米，且更佳為約0.1 +/- 0.01微米。
圖7為根據一實施例的比較具有邊緣/側壁曝露表面及邊緣/側壁電鍍表面之跡線之RF損耗的曲線圖700。曲線圖700展示沿著y軸(即，垂直軸)以分貝(dB)為單位表達之功率損耗及沿著x軸(即，水平軸)以千兆赫茲(GHz)為單位表達之頻率。RF信號之功率損耗在範圍為約1.40GHz至約2.25GHz之頻率下按照10log10[RF功率輸出/RF功率輸入]計算。
曲線圖700包含線710、線720、線730、線740及線750，其表示穿過RFIC基板上之各種跡線之RF信號的功率損耗。線710指示穿過裸的銅跡線(無表面修飾層)之RF信號之RF功率損耗。如點715所指示，在約1.9GHz下，功率損耗為約0.614dB。
線720指示穿過包含Ni/Au接合墊且Ni/Au接合墊之各邊緣及側壁未遭電鍍的銅跡線之RF信號之功率損耗，而線730指示穿過包含Ni/Au接合墊且穿過Ni/Au接合墊之各邊緣及側壁以Ni/Au電鍍材料電 鍍的銅跡線之功率損耗。線720上之點725指示在約1.9GHz下之功率損耗為約0.729dB，且線730上之點735指示在約1.9GHz下之功率損耗為約0.795dB。
線740指示穿過Ni/Pd/Au接合墊且Ni/Pd/Au接合墊之各邊緣及側壁未遭電鍍的銅跡線之RF信號之功率損耗，而線750指示穿過Ni/Pd/Au接合墊且Ni/Pd/Au接合墊之各邊緣及側壁以Ni/Pd/Au電鍍材料電鍍的銅跡線之功率損耗。線740上之點745指示在約1.9GHz下之功率損耗為約0.923dB，且線750上之點755指示在約1.9GHz下之功率損耗為約1.191dB。
參看圖7中所說明之實施例，裸的銅跡線(線710)的功率損耗最小，而包含Ni/Pd/Au接合墊且接合墊的邊緣及側壁被電鍍之跡線(線750)的功率損耗最大。跡線在包含Ni/Au接合墊的情況下(線720、線730)所產生的RF信號功率損耗小於其在包含Ni/Pd/Au接合墊的情況下(線740、線750)所產生的功率損耗。比較包含Ni/Au接合墊之跡線，邊緣及側壁曝露之跡線(線720)所產生的功率損耗小於邊緣及側壁被電鍍之跡線(線730)所產生的功率損耗。類似地，對於具有Ni/Pd/Au接合墊的跡線，其中邊緣及側壁曝露的跡線(線740)所產生的RF信號功率損耗小於邊緣及側壁被電鍍的跡線(線750)所產生的功率損耗。如箭頭760所指示，在一實施例中，對於RF信號通過Ni/Pd/Au接合墊所產生的RF功率損耗而言，Ni/Pd/Au接合墊的邊緣及側壁未遭Ni/Pd/Au電鍍材料電鍍的情況比其邊緣及側壁遭到了Ni/Pd/Au電鍍的情況小約0.26dB。
在一實施例中，為了能成功對引線建立可靠的接合連接，接受程序500處理並被電鍍的引線接合區域414存在最小寬度要求。上文描述之圖4及圖6說明適配於具有均一寬度的銅跡線404內之引線接合墊406的實施例。換言之，遭電鍍的引線接合區域414之寬度及未遭電鍍 的邊緣412及側壁410之寬度不超出引線接合墊406區域中的跡線404與引線接合墊406之相鄰跡線404各區域的均一寬度。
圖8A至圖8F說明引線接合墊之例示性佈局，其中，遭電鍍的接合區域414之最小寬度及至少一個未遭電鍍邊緣412之寬度超出引線接合墊406區域中之跡線404與引線接合墊406之相鄰跡線404各區域的均一寬度。在一實施例中，若在用焊料遮罩覆蓋引線接合墊406之邊緣412從而使引線接合墊406之邊緣412不被電鍍之後，引線接合區域414不滿足最小大小要求，則可藉由曝露最小邊緣來按比例增加跡線404之寬度，以滿足大小要求。
圖8A至圖8D說明引線接合墊406的例示性佈局，其中曝露的邊緣412及側壁410圍繞著引線接合墊406。在一實施例中，若在用焊料遮罩覆蓋引線接合墊406之邊緣412從而使引線接合墊406之邊緣412保持不被電鍍之後，引線接合區域414不滿足最小大小要求，則可藉由曝露最小邊緣以使跡線404之寬度變形，以滿足引線接合區域414之大小要求。換言之，該引線接合區域之佈局滿足由基板技術設計規則設定之最小尺寸或大於該最小尺寸，同時，該引線接合區域之佈局使包含接合區域之銅跡線內的邊緣及側壁遭電鍍的程度降到最小。因此，RF電流在遭電鍍的高電阻邊緣及側壁上流過的距離最小。在圖8A至圖8D中，跡線404的寬度在引線接合墊406之區域中展開，以容納引線接合區域414。另外，跡線404展開後，便可在焊料遮罩製程期間讓引線接合墊406維持邊緣412及側壁410的被覆蓋狀態(未說明)，如此又可讓完成後的引線接合墊406將沿著引線接合墊406之整個周邊的邊緣412及側壁410維持被曝露狀態。
圖8E及圖8F說明若干例示性佈局圖，其中跡線404包含引線接合墊406，但電路佈局的相關事項限制了墊的大小並且防止了邊緣412在遮罩製程期間由焊料遮罩覆蓋。在一實施例中，跡線404隨引線接合 墊406變形以容納引線接合區域414。在另一實施例中，跡線404在引線接合墊406之區域中變形以容納引線接合區域414。在圖8E中，跡線404隨一個引線接合墊406變形以容納一3引線式引線接合區域414。在圖8F中，跡線404隨兩個引線接合墊406變形以容納兩個2引線式引線接合區域414。因此，跡線404的變形可讓遭電鍍的邊緣及側壁的長度為最小，或換言之，可讓未遭電鍍的邊緣及側壁之長度最大，從而減少RF損耗並將引線接合墊之可接合區域維持在所要求的水準。
為節約成本，在一些實施例中，將Ni/Pd/Au代替Ni/Au電鍍至RFIC模組之基板之表面跡線上以形成引線接合區域。然而，Ni/Pd/Au的RF薄層電阻高於Ni/Au的RF薄層電阻，因此，信號穿過Ni/Pd/Au引線接合區域所產生的RF損耗高於信號穿過Ni/Au引線接合區域所產生的RF損耗。為了減少由高RF損耗電鍍(諸如，Ni/Pd/Au電鍍)所引起之RF損耗，在一些實施例中，對焊料遮罩重組態以防止引線接合區域之各邊緣及側壁遭電鍍。使引線接合區域之各邊緣及側壁未遭高RF損耗電鍍(諸如，Ni/Pd/Au電鍍)，便可為RF電流提供流經低電阻率材料之路徑，如此便減少了由高電阻率電鍍材料所引起之RF信號損耗。
雖然所描述之實施例係關於Ni/Pd/Au的表面電鍍，但所揭示之系統及方法適用於任何一種高RF損耗的表面電鍍，諸如，屬Sn、Pb、鐵磁性材料之其他表面及類似者。
除非上下文另有規定，否則遍及[實施方式]及[申請專利範圍]，將以包括性意義而非排他性意義或詳盡意義(亦即，以「包括，但不限於」之意義)來解釋字「包含」及類似者。如本文中一般使用之字「耦接」或「連接」指兩個或多個元件可直接連接，或藉由一或多個中間元件連接。此外，字「本文中」、「上文」、「下文」及類似意思之字在用於本申請案時應指本申請案之全部而非本申請案之任何特定部 分。在上下文允許的情況下，使用單數或複數之上述[實施方式]中之字亦可分別包括複數或單數。關於兩個或兩個以上項目之清單，字「或」涵蓋字之下列全部解釋：清單中之任何項目、清單中之所有項目及清單中之項目之任何組合。
此外，除非另有特別說明或如使用時在上下文內以其他方式理解，本文中使用之諸如「能」、「可」、「例如」、「舉例而言」、「諸如」及類似者以及其他之條件語言大體而言意欲傳達：某些實施例包括而其他實施例不包括某些特徵、元件及/或狀態。因此，此條件語言大體而言並不意欲暗示：一或多個實施例在任何情形下均需要特徵、元件及/或狀態，或一或多個實施例有必要包括用於在具有或不具有作者輸入或提示之情形下決定此等特徵、元件及/或狀態是否包括於任何特定實施例中或是待執行於任何特定實施例中之邏輯。
上述[實施方式]並不意欲為詳盡的或並不意欲將本發明限於上文揭示之精確形式。如一般熟習相關技術者將認識到，雖然上文出於說明之目的而描述了本發明之特定實施例及實例，但是在本發明之範疇內可作出各種等效修改。舉例而言，雖然以給定次序呈現程序或區塊，但替代實施例可按不同次序執行具有步驟之常式或使用具有區塊之系統，且可刪除、移動、添加、細分、組合及/或修改一些程序或區塊。可按各種不同方式實施此等程序或區塊中之每一者。且，雖然有時將程序或區塊展示為相繼執行的，但可改為並行執行此等程序或區塊，或可在不同時間執行此等程序或區塊。
本文中所提供的本發明之教示可應用於其他系統，未必為上文描述之系統。可組合上文描述之各種實施例之元件及動作以提供其他實施例。
雖然已描述了本發明之某些實施例，但是此等實施例僅作為實例而呈現，且並非意欲限制本發明之範疇。實際上，可按各種其他形 式體現本文中所描述之新穎方法及系統；此外，可對本文中所描述之方法及系統之形式進行各種省略、替代及改變，而不背離本發明之精神。隨附[申請專利範圍]及其等效物意欲涵蓋落入本發明之範疇及精神內之此類形式或修改。

Claims (23)

  1. 一種用於製造一射頻積體電路(RFIC)模組之方法，該方法包含：電鍍一鎳層於一銅跡線之一頂表面之一部分上方，該銅跡線包括至少一側壁且形成於一基板上；電鍍一鈀層於該鎳層上方；及電鍍一金層於該鈀層上方，該鎳層、該鈀層及該金層形成一引線接合墊，該引線接合墊覆蓋該銅跡線之一電鍍部分並留下該銅跡線之一未電鍍部分，該銅跡線之該未電鍍部分包括實質上平行於該引線接合墊之該頂表面之一部分，該頂表面之該未電鍍部分之一寬度自該引線接合墊之一周邊延伸至該側壁且為至少約50微米，該未電鍍部分以沿該銅跡線形成一未電鍍路徑且經組態以在該射頻積體電路模組之操作期間傳導射頻(RF)電流並減少射頻功率損耗。
  2. 如請求項第1項之方法，其中該鎳層介於約1微米與約10微米之間。
  3. 如請求項第1項之方法，其中該鈀層介於約0.01微米與約1微米之間。
  4. 如請求項第1項之方法，其中該金層介於約0.01微米與約1微米之間。
  5. 如請求項第1項之方法，其中該銅跡線之該未電鍍部分係不含該鎳層、該鈀層及該金層。
  6. 如請求項第1項之方法，其進一步包含形成該銅跡線以自一第一寬度轉換至大於該第一寬度之一第二寬度，使得具有該第二寬度之該銅跡線之一部分容納該引線接合墊，使得該銅跡線之至少該側壁不含該鎳層、該鈀層及該金層，以於該銅跡線上維持 該未電鍍路徑來傳導該射頻電流。
  7. 如請求項第1項之方法，其進一步包含形成該銅跡線以自一第一寬度轉換至大於該第一寬度之一第二寬度，該第二寬度至少與該引線接合墊之一最小寬度一樣大以容納引線接合連接並沿該銅跡線之至少該側壁維持該未電鍍路徑來傳導該射頻電流。
  8. 如請求項第1項之方法，其中該頂表面之該未電鍍部分之該寬度為約50微米至約100微米。
  9. 一種用於製造一射頻積體電路(RFIC)模組之方法，該方法包含施加電鍍材料於一銅跡線之一頂表面之一部分上方，該銅跡線包括至少一側壁且形成於一基板上，該電鍍材料形成一引線接合墊，該引線接合墊覆蓋該銅跡線之一電鍍部分並留下該銅跡線之一未電鍍部分，該銅跡線之該未電鍍部分包括實質上平行於該引線接合墊之該頂表面之一部分，該頂表面之該未電鍍部分之一寬度自該引線接合墊之一周邊延伸至該側壁且為至少約50微米，該未電鍍部分以沿該銅跡線形成一未電鍍路徑且經組態以在該射頻積體電路模組之操作期間傳導射頻(RF)電流並減少射頻功率損耗。
  10. 如請求項第9項之方法，其中在射頻頻率上該電鍍材料之表面電阻係高於鎳/金電鍍層之表面電阻。
  11. 如請求項第9項之方法，其中該射頻積體電路模組操作在約30kHz至300GHz之頻率。
  12. 如請求項第9項之方法，其中該電鍍材料係使用一浸漬電鍍沈積技術、一電解電鍍技術及一無電極電鍍技術之一或多者而被電鍍。
  13. 如請求項第9項之方法，其中該基板進一步包括多於一側壁且該未電鍍部分包括該多於一側壁。
  14. 如請求項第9項之方法，其進一步包含形成該銅跡線以自一第一寬度轉換至大於該第一寬度之一第二寬度，使得具有該第二寬度之該銅跡線之一部分容納該引線接合墊，使得該銅跡線之至少該側壁不含電鍍材料，以於該銅跡線上維持該未電鍍路徑來傳導該射頻電流。
  15. 如請求項第9項之方法，其進一步包含形成該銅跡線以自一第一寬度轉換至大於該第一寬度之一第二寬度，該第二寬度至少與該引線接合墊之一最小寬度一樣大以容納引線接合連接並沿該銅跡線之至少該側壁維持該未電鍍路徑來傳導該射頻電流。
  16. 如請求項第9項之方法，其中該電鍍材料包括鎳/鈀/金(Ni/Pd/Au)。
  17. 如請求項第9項之方法，其中該電鍍材料包括鎳/金(Ni/Au)。
  18. 如請求項第9項之方法，其中該頂表面之該未電鍍部分之該寬度為約50微米至約100微米。
  19. 一種用於製造一射頻積體電路(RFIC)模組之方法，該方法包含：電鍍一鎳層於一銅跡線之一頂表面之一部分上方，該銅跡線包括至少一側壁且形成於一基板上；及電鍍一金層於該鎳層上方，該鎳層及該金層形成一引線接合墊，該引線接合墊覆蓋該銅跡線之一電鍍部分並留下該銅跡線之一未電鍍部分，該銅跡線之該未電鍍部分包括實質上平行於該引線接合墊之該頂表面之一部分，該頂表面之該未電鍍部分之一寬度自該引線接合墊之一周邊延伸至該側壁且為至少約50微米，該未電鍍部分以沿該銅跡線形成一未電鍍路徑且經組態以在該RFIC模組之操作期間傳導射頻(RF)電流並減少RF功率損耗。
  20. 如請求項第19項之方法，其進一步包含形成該銅跡線以自一第 一寬度轉換至大於該第一寬度之一第二寬度，使得具有該第二寬度之該銅跡線之一部分容納該引線接合墊，使得該銅跡線之至少該側壁不含該鎳層及該金層，以於該銅跡線上維持該未電鍍路徑來傳導該射頻電流。
  21. 如請求項第19項之方法，其進一步包含形成該銅跡線以自一第一寬度轉換至大於該第一寬度之一第二寬度，該第二寬度至少為該引線接合墊之一最小寬度一樣大以容納引線接合連接並沿該銅跡線之至少該側壁維持該未電鍍路徑來傳導該RF電流。
  22. 如請求項第19項之方法，其中該引線接合墊之尺寸係由用於該基板之一基板技術之設計規則來設定以實現可靠之引線接合。
  23. 如請求項第19項之方法，其中該頂表面之該未電鍍部分之該寬度為約50微米至約100微米。
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