TWI606584B - 半導體裝置與其形成方法 - Google Patents

半導體裝置與其形成方法 Download PDF

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TWI606584B
TWI606584B TW104141054A TW104141054A TWI606584B TW I606584 B TWI606584 B TW I606584B TW 104141054 A TW104141054 A TW 104141054A TW 104141054 A TW104141054 A TW 104141054A TW I606584 B TWI606584 B TW I606584B
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dielectric layer
gate
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source
forming
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TW201709519A (zh
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呂志偉
李忠儒
陳海清
黃建樺
包天一
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台灣積體電路製造股份有限公司
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Description

半導體裝置與其形成方法
本揭露關於半導體裝置之形成方法，更特別關於解決覆蓋誤差的方法與其形成之結構。
半導體積體電路(IC)產業已快速成長一段時日。IC材料與設計的技術進步，使每一代的IC比前一代的IC更小且其電路更複雜。新一代的IC具有較大的功能密度(比如固定晶片面積中的內連線元件數目)，與較小的尺寸(比如製程形成的最小構件或連線)。製程尺寸縮小往往有利於增加製程效率並降低相關成本。製程尺寸縮小亦會增加製程複雜度，但製程尺寸縮小的優點顯而易見，因此需要更小的IC製程尺寸。
舉例來說，場效電晶體(FET)通常班含源極與汲極(S/D)結構於閘極堆疊的相反兩側上。閘極間隔物圍繞並保護閘極堆疊，並提升閘極堆疊的電性效能。然而閘極間隔物常常損傷於後續製程中，比如中後段製程。舉例來說，光微影與蝕刻製程係用以定義及蝕刻用於S/D與閘極通孔(或插塞)之孔洞。由於光微影的覆蓋誤差，孔洞有時會對不準下方的目標。如此一來，蝕刻製程不只移除目標材料，還會移除部份的閘極間隔物。這會劣化閘極堆疊效能、造成S/D通孔與閘極堆疊短路、還會造成其他可信度問題與缺陷於IC裝置中。
本揭露一實施例提供之半導體裝置的形成方法，包括：提供前驅物，且前驅物包括：基板；閘極堆疊，位於基板上；第一介電層，位於閘極堆疊上；閘極間隔物，位於閘極堆疊之側壁與第一介電層之側壁上；以及多個源極與汲極接點位於閘極堆疊之相對兩側上；使閘極間隔物凹陷以至少露出第一介電層之部份側壁，但未露出閘極堆疊之側壁；以及形成間隔物保護層於凹陷的閘極間隔物、第一介電層、與源極與汲極接點上。
本揭露一實施例提供之半導體裝置的形成方法，包括：提供前驅物，且前驅物包括：基板；閘極堆疊，位於基板上；第一介電層，位於閘極堆疊上；閘極間隔物，位於閘極堆疊之側壁以及第一介電層之側壁上；以及多個源極與汲極接點位於閘極堆疊之相對兩側上；使閘極間隔物凹陷以至少露出第一介電層之部份側壁，但不露出閘極堆疊的側壁；使源極與汲極接點凹陷至低於第一介電層的上表面；以及形成間隔物保護層於第一介電層、凹陷後的閘極間隔物、與凹陷後的源極與汲極接點上。
本揭露一實施例提供之半導體裝置，包括：基板；閘極堆疊，位於基板上；閘極間隔物，位於閘極堆疊之側壁上；多個源極與汲極接點，且閘極堆疊與閘極間隔物隔開源極與汲極接點；間隔物保護層，位於部份閘極間隔物上；閘極通孔，位於閘極堆疊上並電性連接至閘極堆疊；以及多個源極與汲極通孔，位於源極與汲極接點上並電性連接至源極與汲極接點。
10‧‧‧方法
12、14、16、18、20、22、24、26、28、30、32、34‧‧‧步驟
100‧‧‧半導體裝置
102‧‧‧基板
104‧‧‧S/D區
106‧‧‧通道區
108‧‧‧閘極堆疊
110、122‧‧‧介電層
110’、112’、118’‧‧‧上表面
112‧‧‧閘極間隔物
114、124‧‧‧CESL
116、126‧‧‧ILD
118‧‧‧S/D接點
120‧‧‧間隔物保護層
128a、128b、130a、130b‧‧‧孔洞
132‧‧‧金屬
134a、134b‧‧‧S/D通孔
136a、136b‧‧‧閘極通孔
第1A與1B圖係本揭露多種實施例中，形成半導體裝置之方法的流程圖。
第2A、2B、2C、2D、2E、2F、2G、2H、2I、2J、2K、與2L圖係一實施例中，依據第1A與1B圖中的方法形成之半導體裝置的部份剖視圖。
下述內容提供的不同實施例可實施本發明的不同結構。特定構件與排列的實施例係用以簡化本發明而非侷限本發明。舉例來說，形成第一構件於第二構件上的敘述包含兩者直接接觸，或兩者之間隔有其他額外構件而非直接接觸。此外，本發明之多種實例將重複標號及/或符號以簡化並清楚說明。不同實施例中具有相同標號的元件並不必然具有相同的對應關係及/或排列。
此外，空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。
本揭露關於半導體裝置與其形成方法。更特別的是，本揭露關於具有閘極間隔物與位於其上之保護層的半導體裝置。本揭露的目的之一係於源極、汲極、與閘極之通孔蝕刻 製程時，保護閘極間隔物。在現有的光微影製程中，即使不是不可能也難以避免覆蓋誤差。通孔蝕刻製程通常亦移除部份的閘極間隔物，這將劣化閘極電性效能、造成源極與汲極通孔與閘極短路、以及造成其他問題。本揭露解決這些問題，並在製作裝置與製程控制上提供立即的好處。
第1A與1B圖係本揭露多種實施例中，形成具有間隔物保護層於閘極間隔物上之半導體裝置100的方法10其流程圖。方法10僅用以舉例，而非在申請專利範圍外侷限本揭露。在方法10之前、之中、與之後可進行額外步驟。在其他實施例中，下述方法的某些步驟可置換、省略、或改變其操作順序。下述方法10將搭配第2A至2L圖說明，而第2A至2L圖係半導體裝置100於製程之多種階段中的剖視圖。
半導體裝置100僅用以舉例說明，而非限制本揭露之實施例至任何裝置數目、任何區域數目、或任何結構或區喻的設置方式。此外，第2A至2L圖中的半導體裝置100可為IC或部份IC製程的中間裝置。上述IC可為靜態隨機存取記憶體(SRAM)及/或邏輯電路，被動構件如電阻、電容、或電感，或主動構件如p型場效電晶體(pFET)、n型FET(nFET)、多重閘極FET如FinFET、金氧半場效電晶體(MOSFET)、互補式金氧半(CMOS)電晶體、雙極電晶體、高電壓電晶體、高頻電晶體、其他記憶單元、或上述之組合。
在方法10之步驟12中，提供半導體裝置10之前驅物如第2A圖所示。為方便說明，半導體裝置100之前驅物又稱作半導體裝置100。如第2A圖所示，半導體裝置100包含基板102 與多種結構形成其上。基板102包含多種S/D(源極與汲極)區104，以及夾設於S/D區104之間的通道區106。半導體裝置100亦包含與通道區106相鄰的多個閘極堆疊108，位於每一閘極堆疊108上的介電層110、以及位於每一閘極堆疊108之側壁上及個別介電層110之側壁上的閘極間隔物112。在此實施例中，半導體裝置100亦包含基板102及閘極間隔物112之側壁上的CESL(接點蝕刻停止層)114，以及位於CESL 114上的ILD層116。半導體裝置100更包含位於S/D區104上的S/D接點118，其電性連接至S/D區104。半導體裝置100之多種結構(或構件)將進一步說明如下。
在此實施例中，基板102為矽基板。在其他實施例中，基板102包含其他半導體元素如鍺，半導體化合物如碳化矽、砷化鎵、砷化銦、或磷化銦，或半導體合金如碳化矽鍺、磷化鎵砷、或磷化鎵銦。在實施例中，基板102可包含絕緣層上矽(SOI)基板，其可具有應力源以增加效能，且基板102可包含磊晶區、隔離區、掺雜區、及/或其他合適結構或層狀物。
S/D區104可包含重掺雜S/D(HDD)、輕掺雜S/D(LDD)、隆起區、應力區、磊晶成長區、及/或其他合適結構。S/D區104之形成方法可為蝕刻與磊晶、環形佈植、S/D佈植、S/D活化、及/或其他合適製程。在一實施例中，S/D區104可進一步包含矽化物。舉例來說，矽化物的形成製程可包含沉積金屬層、回火金屬層使其與矽反應形成矽化物、以及接著移除未反應的金屬層。在一實施例中，基板102包含鰭狀主動區以形成多重閘極FET如FinFET。在此實施例中，S/D區104與通道區 106可形成於鰭狀物之上或之中。
通道區106可夾設於一對S/D區104之間。當半導體裝置100開啟時，通道區106可導通對應之S/D區104之間的電流。
閘極堆疊108與通道區106相鄰。閘極堆疊108為多層結構。在一實施例中，閘極堆疊108包含界面層、閘極介電層、功函數層、與金屬填充層。界面層可包含介電材料如氧化矽(SiO2)或氮氧化矽(SiON)，且其形成方法可為化學氧化、熱氧化、原子層沉積(ALD)、化學氣相沉積(CVD)、及/或其他合適方法。閘極介電層可包含高介電常數介電層如氧化鉿(HfO2)、氧化鋯(ZrO2)、氧化鑭(La2O3)、氧化鈦(TiO2)、氧化釔(Y2O3)、鈦酸鍶(SrTiO3)、其他合適金屬氧化物、或上述之組合，且其形成方法可為ALD及/或其他合適方法。功函數層可為p型或n型的功函數層。P型功函數層可包含但不限於氮化鈦(tiN)、氮化鉭(TaN)、釕(Ru)、鉬(Mo)、鎢(W)、鉑(Pt)、或上述之組合。n型功函數層包含但不限於鈦(Ti)、鋁(Al)、碳化鉭(TaC)、氮化鉭碳(TaCN)、氮化鉭矽(TaSiN)、或上述之組合。功函數層可包含多個層狀物，且其沉積方法可為CVD、PVD、及/或其他合適製程。金屬填充層包含鋁(Al)、鎢(W)、鈷(Co)、銅(Cu)、及/或其他合適材料。金屬填充層之形成方法可為CVD、PVD、電鍍、及/或其他合適製程。閘極堆疊108之形成方法可為閘極優先製程或閘極後製製程(如閘極取代製程)。
介電層110位於閘極堆疊108上。在一實施例中，介電層110包含金屬氧化物、金屬氮化物、或其他合適介電材 料。舉例來說，金屬氧化物可為氧化鈦(TiO2)、氧化鋁(Al2O3)、或其他金屬氧化物。舉例來說，金屬氮化物可為(TiN)、氮化鋁(AlN)、氮氧化鋁(AlON)、氮化鉭(TaN)、或其他金屬氮化物。介電層110形成於閘極堆疊108上的方法可為一或多道沉積與蝕刻製程。
閘極間隔物112可為單層或多層結構。在一實施例中，間隔物112包含低介電常數(比如k<7)之介電材料。在某些實施例中，閘極間隔物112包含介電材料如氧化矽(SiO2)、氮化矽(SiN)、氮氧化矽(SiON)、其他介電材料、或上述之組合。在一例中，閘極間隔物112之形成方法為毯覆性地沉積第一介電層(如具有一致厚度之SiO2層)於半導體裝置100上以作為襯墊層，以及沉積第二介電層(如SiN層)於第一介電層上以作為D-形間隔物，接著非等向蝕刻移除部份上述介電層以形成閘極間隔物112。在此實施例中，閘極間隔物112位於閘極堆疊108之側壁上與介電層110上，以達多種目的。舉例來說，上述結構在多種製程中可保護閘極堆疊108，在S/D區104形成於基板102中時產生抵消，以及幫助改善閘極堆疊108之電性效能。
CESL 114可包含介電材料如氮化矽(SiN)、氧化矽(SiO2)、氮氧化矽(SiON)、及/或其他材料。CESL 114之形成方法可為電漿增強CVD(PECVD)製程及/或其他合適的沉積或氧化製程。ILD層116可包含四甲氧基矽烷(TEOS)氧化物、未掺雜之矽酸鹽玻璃、或掺雜的氧化矽如硼磷矽酸鹽玻璃(BPSG)、熔融氧化矽玻璃(FSG)、磷矽酸鹽玻璃(PSG)、硼掺雜之矽玻璃(BSG)、及/或其他合適介電材料。ILD層116之沉積方法可為 PECVD製程、可流動CVD(FCVD)製程、或其他合適沉積技術。在一實施例中，CESL 114係沉積於基板102上並覆蓋基板102上的多種結構。且ILD層116係沉積於CESL 114上。接著，回蝕刻ILD層116與CESL 114以移除其對應S/D區104上的部份，留下開口以沉積S/D接點118。如此一來，部份的CESL 114保留於閘極間隔物112之側壁上。
S/D接點118位於S/D區104上，並電性連接S/D區104。S/D接點118之間隔有結構如閘極堆疊108、閘極間隔物112、與CESL 114。在一實施例中，S/D接點118包含金屬如鋁(Al)、鎢(W)、銅(Cu)、鈷(Co)、上述之組合、或其他合適導電材料。在一實施例中，S/D接點之沉積方法為合適製程如CVD、PVD、電鍍、及/或其他合適製程。在沉積S/D接點之金屬後，可進行化學機械拋光(CMP)製程以平坦化半導體裝置100的上表面。如此一來，多種層狀物如介電層110、閘極間隔物112、與S/D接點118具有共平面的表面。如第2A圖所示之此實施例中，介電層110之上表面110’、閘極間隔物112之上表面112’、與S/D接點118之上表面118’實質上共平面。
在方法10之步驟14(見第1A圖)中，使閘極間隔物112凹陷。如第2B圖所示之此實施例中，步驟14使閘極間隔物112與CESL 114凹陷。在實施例中，步驟14可為乾蝕刻、濕蝕刻、或其他合適蝕刻製程。舉例來說，乾蝕刻製程可採用含氧氣體、含氟氣體(如CF4、SF6、CH2F2、CHF3、及/或C2F6)、含溴氣體(如HBr及/或CHBr3)、含碘氣體、其他合適氣體及/或電漿、及/或上述之組合。舉例來說，濕蝕刻製程可包含下述物 質中的蝕刻：稀氫氟酸(DHF)、氫氧化鉀(KOH)溶液、氨、含氫氟酸(HF)、硝酸(HNO3)、及/或醋酸(CH3COOH)的溶液、或其他合適的濕蝕刻品。在此實施例中，可調整蝕刻製程以選擇性地移除部份的閘極間隔物112與CESL 114，但實質上不影響介電層110、ILD層116、與S/D接點118。此外，閘極間隔物112凹陷後露出介電層110之側壁，但不露出出閘極堆疊108之側壁。換言之，閘極間隔物112之回蝕刻深度小於或等於介電層110之深度(沿著z方向)。在一實施例中，閘極間隔物112凹陷後完全露出介電層110之側壁。如第2B圖所示，閘極間隔物112之上表面112'低於介電層110之上表面110'與S/D接點118之上表面118'。
在方法10之步驟16中(見第1A圖)，使S/D接點118凹陷。如第2C圖所示，S/D接點118之上表面118'凹陷至低於介電層110的上表面110'。在此實施例中，S/D接點118之上表面118'亦低於閘極間隔物112之上表面112'。在其他實施例中，S/D接點118之上表面118'高於閘極間隔物112之上表面112'或與其等高。在另一實施例中，S/D接點118之上表面118'凹陷至低於介電層110之下表面。S/D接點之凹陷方法可為乾蝕刻、濕蝕刻、反應性離子蝕刻、或其他合適蝕刻方法。此外，可調整蝕刻製程以選擇性地移除部份S/D接點118，但實質上不影響半導體裝置的其他結構。在一實施例中，可視情況進行步驟16，比如在步驟18前可使(或不使)S/D接點凹陷。
在方法10之步驟18中(見第1A圖)，形成間隔物保護層120於半導體裝置100上。如第2D圖所示，間隔物保護層120 覆蓋多種結構如介電層110、閘極間隔物112、CESL 114、ILD層116、與S/D接點118的上表面。在此實施例中，間隔物保護層120係順應性的層狀物，比如具有實質上順應性的厚度(在x-z平面)。在多種實施例中，間隔物保護層120之厚度介於約10Å至約200Å之間。間隔物保護層120可包含金屬氧化物、金屬氮化物、或其他合適介電材料。舉例來說，金屬氧化物可為氧化鈦(TiO2)、氧化鋁(Al2O3)、或其他金屬氧化物。舉例來說，金屬氮化物可為氮化鈦(TiN)、氮化鋁(AlN)、氮氧化鋁(AlON)、氮化鉭(TaN)、或其他金屬氮化物。在多種實施例中，間隔物保護層120包含的材料不同於介電層110的材料。間隔物保護層120的形成方法可為ALD、PVD、CVD、或其他合適的沉積方法。
在方法10之步驟20中(見第1A圖)，形成另一介電層122於間隔物保護層120上。如第2E圖所示，介電層122係沉積於半導體裝置100上並填入半導體裝置100上的多種溝槽中。介電層122可包含金屬氧化物(如TiO2或Al2O3)、金屬氮化物(如TiN、AlN、AlON、或TaN)、或其他合適介電材料。在多種實施例中，介電層122包含的材料不同於間隔物保護層120。此外，介電層110與122可為相同或不同材料。介電層122之沉積方法可為PVD、CVD、或其他沉積方法。
在方法10之步驟22中(見第1A圖)，使介電層122與間隔物保護層120凹陷以露出介電層110。如第2F圖所示，使介電層122凹陷，並移除介電層110上的部份間隔物保護層120。在一實施例中，步驟22包含CMP製程以凹陷多種層狀物。在另 一實施例中，此製程亦移除部份ILD層116與部份介電層110。在另一實施例中，S/D接點118並未凹陷(即省略步驟16)，而步驟22亦可移除部份S/D接點118。在又一實施例中，部份間隔物保護層120保留於介電層110之側壁(沿著z方向)上。在多種實施例中，步驟22實質上不影響閘極間隔物112上的間隔物保護層120。
在方法10之步驟24中(見第1B圖)，形成一或多個介電層，且第一級通孔之後將形成其中。在本揭露中，一或多個介電層稱作第一級介電層。如第2G圖所示之此實施例中，第一級介電層包含CESL 124與ILD層126於CESL 124上。CESL 124可包含介電材料如SiN、SiO2、或SiON。ILD層126可包含氧化物如TEOS、BPSG、FSG、PSG、或BSG。ILD層126與CESL 124可各自與ILD層116與CESL 1124具有相同或不同的材料。此外，此實施例中的CESL 124可與介電層110及/或介電層122具有相同材料。CESL 124之形成方法可為PECVD製程或其他合適的沉積製程或氧化製程。ILD層126之沉積方法可為PECVD製程、FCVD製程、或其他合適的沉積製程。
在方法10之步驟26中(見第1B圖)，蝕刻多種層狀物以形成孔洞(或溝槽)128a與128b於S/D接點118上。如第2H圖所示，移除部份ILD層126、CESL 124、與介電層122，並露出孔洞128a與128b中的間隔物保護層120。孔洞128a與128b之形成方法可為多種製程，其包含光微影與蝕刻製程。光微影製程可包含形成光阻於ILD層126上，曝光光阻使其成一圖案以定義孔洞128a與128b之幾何形狀，進行曝光後烘烤製程，以及顯影光 阻以形成遮罩單元。接著以遮罩單元進行蝕刻製程，形成凹陷於層狀物如ILD層126、CESL 124、與介電層122中。接著移除遮罩單元(圖案化之光阻)。蝕刻製程可包含一或多道乾蝕刻製程、濕蝕刻製程、或其他合適蝕刻製程。特別的是，步驟26包含調整蝕刻製程以選擇性地移除介電層122，但實質上不影響間隔物保護層120。在一實施例中，蝕刻製程包含非等向蝕刻如非等向乾蝕刻製程。
在光微影製程中，即使不是不可能也非常難以避免覆蓋誤差。覆蓋誤差指的是遮罩單元定義的圖案與下方目標之間對不準。為了說明及比較，第2H圖係孔洞128a正確對準目標的S/D接點118，而孔洞128b則未對準目標的S/D接點118。特別的是，孔洞128b與閘極間隔物112部份重疊。若沒有間隔物保護層120，蝕刻製程將移除孔洞128b露出之部份的閘極間隔物112。理由之一為閘極間隔物112通常為低介電常數介電材料，其與介電層122並無足夠的蝕刻選擇性。換言之，移除介電層122之蝕刻製程通常也可移除閘極間隔物112。若閘極間隔物112被移除，則閘極堆疊108與沉積在孔洞128b中的S/D通孔(或插塞)可能短路，造成裝置缺陷。在此實施例中，間隔物保護層120與介電層122之間具有足夠的蝕刻選擇性。如此一來，即使產生光微影覆蓋誤差(如孔洞128b)，仍可保護閘極間隔物112使其免於蝕刻製程影響。
在方法10之步驟28中(見第1B圖)，蝕刻多個層狀物以形成孔洞130a與130b於閘極堆疊108上。如第2I圖所示，蝕刻製程蝕刻ILD層126、CESL 124、與介電層110以露出閘極堆 疊108的上表面。在一實施例中，步驟28與步驟26類似，亦包含光微影與蝕刻製程。舉例來說，光微影製程定義與顯影ILD層126上的遮罩單元，而蝕刻製程以遮罩單元作為蝕刻遮罩進行蝕刻，以形成孔洞130a與130b。藉由相同的遮罩單元，可保護孔洞128a與128b免於蝕刻製程影響。在一實施例中，步驟28包含多重選擇性蝕刻製程。舉例來說，步驟28包含調整蝕刻製程以選擇性地移除CESL 124，但實質上不影響間隔物保護層120。在又一實施例中，蝕刻製程可為非等向蝕刻製程如非等向乾蝕刻製程。
與步驟26類似，光微影覆蓋誤差亦造成孔洞130a及/或130b對不準個別的閘極堆疊108。為了說明與比較，第2I圖中的孔洞130a正確對準目標閘極堆疊108，但孔洞130b對不準目標閘極堆疊108。特別的是，孔洞130b與閘極間隔物112部份重疊。若無間隔物保護層120，蝕刻製程將移除孔洞130b露出的部份閘極間隔物112，因為閘極間隔物112與介電層110不具有足夠的蝕刻選擇性。如此一來，將劣化閘極堆疊108的電性效能，並造成其他長期可信度的問題。在此實施例中，間隔物保護層120可在蝕刻介電層110時，有效的保護閘極間隔物112。
在方法10之步驟30中(見第1B圖)，若對應S/D通孔之孔洞128a與128b及對應閘極通孔之孔洞130a與130b中露出任何的部份間隔物保護層120，則移除這些間隔物保護層120。如第2J圖所示，移除部份的間隔物保護層120(特別是對應S/D通孔之孔洞128a與128b者)以露出下方的S/D接點118。在一實 施例中，間隔物保護層120之移除方法可為乾蝕刻製程、濕蝕刻製程、或其他合適蝕刻製程。在其他實施例中，調整蝕刻製程以選擇性地移除間隔物保護層120，但實質上不影響閘極間隔物112。
在方法10之步驟32中(見第1B圖)，形成通孔(或插塞)於孔洞128a、128b、130a、與130b中。在一實施例中，步驟32包含沉積金屬132於半導體裝置100上以填入孔洞中(見第2K圖)，並進行CMP製程以移除多餘金屬並平坦化半導體裝置100的上表面(見第2L圖)。如此一來，可分別形成S/D通孔134a與134b於孔洞128a與128b中以電性連接S/D接點118，並分別形成閘極通孔136a與136b於孔洞130a與130b中以電性連接閘極堆疊108。S/D通孔134b與閘極通孔136b部份地位於個別的閘極間隔物112上。在實施例中，金屬132可包含鋁(Al)、鎢(W)、鈷(Co)、銅(Cu)、及/或其他合適材料。金屬132之形成方法可為CVD、PVD、電鍍、及/或其他合適製程。如第2I圖所示，由於間隔物保護層120的存在，經過步驟26與28的多種蝕刻製程後仍可實質上保留閘極間隔物112。位於每一閘極堆疊108兩側壁上的部份閘極間隔物112具有相同高度，即使有部份S/D通孔134b與閘極通孔136b位於其上。此外，部份間隔物保護層120仍保留於半導體裝置100中。舉例來說，某些部份間隔物保護層120位於閘極間隔物112、S/D接點118、及/或CESL 114上。
在方法10之步驟34中(見第1B圖)，進行額外步驟以完成製作半導體裝置100。舉例來說，方法10可形成多層內連線結構，使S/D通孔(134a與134b)及閘極通孔(136a與136b)連接 至半導體裝置100的其他部份，以形成完整IC。
本揭露一實施例提供半導體裝置與其形成方法的優點但不限於此。舉例來說，閘極間隔物上的間隔物保護層，可在形成第一級通孔(S/D通孔與閘極通孔)之多種蝕刻製程中保護閘極間隔物。上述結構可輕易整合至現有的IC製程。此外，上述揭露的形成方法可容忍製程偏差，並提供半導體裝置製程有力的解答。本揭露可用於製作平面FET，亦可用於製作三維裝置與多重閘極裝置如雙閘FET、FinFET、三閘FET、Omega FET、全環閘(GAA)裝置、或垂直GAA裝置。
在一實施例中，本揭露提供半導體裝置的形成方法。此方法包括：提供前驅物，且前驅物包括：基板；閘極堆疊，位於基板上；第一介電層，位於閘極堆疊上；閘極間隔物，位於閘極堆疊之側壁與第一介電層之側壁上；以及多個源極與汲極接點位於閘極堆疊之相對兩側上。此方法亦包含使閘極間隔物凹陷以至少露出第一介電層之部份側壁，但未露出閘極堆疊之側壁。此方法亦包含形成間隔物保護層於凹陷的閘極間隔物、第一介電層、與源極與汲極接點上。
在另一實施例中，本揭露提供半導體裝置的形成方法。此方法包括提供前驅物，且前驅物包括：基板；閘極堆疊，位於基板上；第一介電層，位於閘極堆疊上；閘極間隔物，位於閘極堆疊之側壁以及第一介電層之側壁上；以及多個源極與汲極接點位於閘極堆疊之相對兩側上。此方法亦包含使閘極間隔物凹陷以至少露出第一介電層之部份側壁，但不露出閘極堆疊的側壁。此方法亦包含使源極與汲極接點凹陷至低於第一 介電層的上表面；以及形成間隔物保護層於第一介電層、凹陷後的閘極間隔物、與凹陷後的源極與汲極接點上。
在又一實施例中，本揭露提供半導體裝置。半導體裝置包括：基板；閘極堆疊，位於基板上；閘極間隔物，位於閘極堆疊之側壁上；多個源極與汲極接點，且閘極堆疊與閘極間隔物隔開源極與汲極接點。半導體裝置亦包含間隔物保護層位於部份閘極間隔物上。半導體裝置亦包含閘極通孔，位於閘極堆疊上並電性連接至閘極堆疊；以及多個源極與汲極通孔，位於源極與汲極接點上並電性連接至源極與汲極接點。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明。本技術領域中具有通常知識者應理解可採用本申請案作為基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本發明之精神與範疇，並可在未脫離本發明之精神與範疇的前提下進行改變、替換、或更動。
100‧‧‧半導體裝置
102‧‧‧基板
104‧‧‧S/D區
106‧‧‧通道區
108‧‧‧閘極堆疊
110、122‧‧‧介電層
112‧‧‧閘極間隔物
114、124‧‧‧CESL
116、126‧‧‧ILD
118‧‧‧S/D接點
120‧‧‧間隔物保護層
134a、134b‧‧‧S/D通孔
136a、136b‧‧‧閘極通孔

Claims (8)

  1. 一種半導體裝置的形成方法，包括：提供一前驅物，且該前驅物包括：一基板；一閘極堆疊，位於該基板上；一第一介電層，位於該閘極堆疊上；一閘極間隔物，位於該閘極堆疊之側壁與該第一介電層之側壁上；多個源極與汲極接點位於該閘極堆疊之相對兩側上；使該閘極間隔物凹陷以至少露出該第一介電層之部份側壁，但未露出該閘極堆疊之側壁；形成一間隔物保護層於凹陷的該閘極間隔物、該第一介電層、與該些源極與汲極接點上；形成一第二介電層於該間隔物保護層上；以及至少使該第二介電層與該間隔物保護層凹陷，以露出該第一介電層之上表面，其中凹陷後的該間隔物保護層覆蓋該些源極與汲極接點。
  2. 如申請專利範圍第1項所述之半導體裝置的形成方法，更包括：在形成該間隔物保護層前，先使該些源極與汲極接點凹陷至低於該第一介電層的上表面。
  3. 如申請專利範圍第1項所述之半導體裝置的形成方法，更包括：形成一第一級介電層於具有該間隔物保護層、該第一介電 層、與該第二介電層之該前驅物上；形成多個源極與汲極通孔孔洞穿過該第一級介電層，至該些源極與汲極接點上；以及形成一閘極通孔孔洞穿過該第一級介電層，以至少露出部份該閘極堆疊。
  4. 如申請專利範圍第3項所述之半導體裝置的形成方法，更包括：移除該些源極與汲極通孔孔洞與該閘極通孔孔洞露出的部份該間隔物保護層；形成多個源極與汲極通孔於該些源極與汲極通孔孔洞中；以及形成一閘極通孔於該閘極通孔孔洞中，其中形成該些源極與汲極通孔之步驟與形成該閘極通孔之步驟係相同製程。
  5. 如申請專利範圍第3項所述之半導體裝置的形成方法，其中形成該些源極與汲極通孔孔洞之步驟包括調整一蝕刻製程，使其選擇性地移除該第二介電層而實質上不影響該間隔物保護層，且其中形成該閘極通孔孔洞之步驟包括調整一蝕刻製程，使其選擇性地移除該第一介電層而實質上不影響該間隔物保護層。
  6. 一種半導體裝置的形成方法，包括：提供一前驅物，且該前驅物包括：一基板；一閘極堆疊，位於該基板上；一第一介電層，位於該閘極堆疊上； 一閘極間隔物，位於該閘極堆疊之側壁以及該第一介電層之側壁上；多個源極與汲極接點位於該閘極堆疊之相對兩側上；使該閘極間隔物凹陷以至少露出該第一介電層之部份側壁，但不露出該閘極堆疊的側壁；使該些源極與汲極接點凹陷至低於該第一介電層的上表面；形成一間隔物保護層於該第一介電層、凹陷後的該閘極間隔物、與凹陷後的該些源極與汲極接點上；形成一第二介電層於該間隔物保護層上；以及至少使該第二介電層與該間隔物保護層凹陷，以露出該第一介電層之上表面，其中凹陷後的該間隔物保護層覆蓋該些源極與汲極接點。
  7. 如申請專利範圍第6項所述之半導體裝置的形成方法，更包括：在露出該第一介電層的上表面後，形成一第一級介電層於該間隔物保護層、該第一介電層、與該第二介電層上；形成多個源極與汲極通孔孔洞穿過該第一級介電層，以露出該些源極與汲極接點上的部份該間隔物保護層；以及形成一閘極通孔孔洞穿過該第一級介電層，以至少露出部份該閘極堆疊，其中形成該些源極與汲極通孔孔洞之步驟包括調整一蝕刻製程，使其選擇性地移除該第二介電層而實質上不影響該間隔物保護層，且其中形成該閘極通孔孔洞之步驟包括調整一蝕刻製程，使其選擇性地移除該第一 介電層而實質上不影響該間隔物保護層。
  8. 一種半導體裝置，包括：一基板；一閘極堆疊，位於該基板上；一第一介電層，位於該閘極堆疊上；一閘極間隔物，位於該閘極堆疊之側壁上；多個源極與汲極接點，且該閘極堆疊與該閘極間隔物隔開該些源極與汲極接點；一間隔物保護層，位於部份該閘極間隔物上並覆蓋該些源極與汲極接點，且露出該第一介電層；一閘極通孔，位於該閘極堆疊上並穿過該第一介電層以電性連接至該閘極堆疊；以及多個源極與汲極通孔，位於該些源極與汲極接點上並穿過該間隔物保護層以電性連接至該些源極與汲極接點。
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