TWI585901B - 鰭式場效電晶體結構及其製備方法 - Google Patents

鰭式場效電晶體結構及其製備方法 Download PDF

Info

Publication number
TWI585901B
TWI585901B TW104138919A TW104138919A TWI585901B TW I585901 B TWI585901 B TW I585901B TW 104138919 A TW104138919 A TW 104138919A TW 104138919 A TW104138919 A TW 104138919A TW I585901 B TWI585901 B TW I585901B
Authority
TW
Taiwan
Prior art keywords
carbon
forming
layer
germanium layer
substrate
Prior art date
Application number
TW104138919A
Other languages
English (en)
Other versions
TW201705373A (zh
Inventor
吳政達
陳政緯
吳宏益
張簡旭珂
游偉明
王廷君
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201705373A publication Critical patent/TW201705373A/zh
Application granted granted Critical
Publication of TWI585901B publication Critical patent/TWI585901B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02592—Microstructure amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02609—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Thin Film Transistor (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)

Description

鰭式場效電晶體結構及其製備方法
本揭露係關於鰭式場效電晶體結構及鰭式場效電晶體結構之製備方法。
半導體積體電路(integrated circuit，IC)產業呈指數成長。IC材料與設計方面的技術進展使得IC代數不斷推陳出新，且每一代IC的尺寸越來越小，電路則越來越複雜。在IC進化的過程中，功能密度(即，單位晶片面積中互連的元件數目)通常會變大，而其幾何尺寸(即，利用一製程可產生之最小構件(或線))則會變小。這種尺寸縮減的過程帶來的優點是能夠增加生產效率以及降低相關成本。
上述尺寸縮減的過程也增加了處理與製備IC的複雜性，且為了要實現此一目的，在IC處理與製備過程中也需要相應的技術發展。舉例來說，已發展出了三維電晶體(譬如鰭式場效電晶體)來取代平面電晶體。雖然既有的鰭式場效電晶體元件與鰭式場效電晶體元件的製備方法通常能夠達到預期之目的，但這些方法通常無法滿足所有面向。譬如，在鰭式場效電晶體之閘極氧化物與金屬閘極之間的不規則介面，對於鰭式場效電晶體製程發展帶來了挑戰。因此，需要對此一區域加以改善。
本揭露的一些實施例提出了一種形成鰭式場效電晶體的方法。所述方法包括提供一基板，於基板上形成複數個條帶，於該些條帶其中之一的上表面與側壁上形成一氧化物材料，以及在第一溫度下，於氧化物材料上形成碳摻雜矽層。所述方法進一步包括將所述溫度提高至大於第一溫度之第二溫度，其中形成碳摻雜矽層包括原位摻雜製程。
在一些實施例中，原位摻雜製程包括引入包括SiH4、C2H4或H2之氣體。
在一些實施例中，第一溫度介於約450℃至約650℃之間。
在一些實施例中，原位摻雜製程是在約0.2至約5.0托之間的壓力下進行。
在一些實施例中，碳摻雜矽層的濃度在約5E19/cm3至約1E22/cm3的範圍中。
在一些實施例中，第二溫度高於約700℃。
在一些實施例中，碳摻雜矽層包括<111>多晶矽。
在一些實施例中，<111>多晶矽的平均晶粒大小小於一預定值。
本揭露的一些實施例提出一種形成半導體元件的方法。所述方法包括提供一基板，形成由基板突出之一鰭結構，在基板上形成淺溝槽隔離物，以及在鰭結構上形成一氧化物材料。所述方法進一步包括於氧化物材料上形成碳摻雜非晶矽層或碳摻雜多晶矽層，其中形成碳摻雜非晶矽層或碳摻雜多晶矽層包括摻雜範圍介於5E19/cm3至約1E22/cm3間之碳。
在一些實施例中，形成碳摻雜矽層包括原位摻雜製 程、異位摻雜製程或其組合。
在一些實施例中，異位摻雜製程包括以碳與氮來佈植上述非晶矽層或多晶矽層。
在一些實施例中，原位摻雜製程包括在形成碳摻雜非晶矽層或碳摻雜多晶矽層時，引入SiH4、C2H4與H2其中之一。
在一些實施例中，碳摻雜多晶矽層係由碳摻雜非晶矽層在高於攝氏700度的溫度下轉換所得。
在一些實施例中，碳摻雜多晶矽層的晶粒大小約為不含碳之多晶矽層的晶粒大小之75%。
在一些實施例中，碳摻雜多晶矽層包括選自<100>、<110>與<111>之晶粒方向。
在一些實施例中，所述方法包括利用蝕刻製程以移除碳摻雜非晶矽層或碳摻雜多晶矽層。
本揭露的一些實施例提供一種鰭式場效電晶體結構。所述的鰭式場效電晶體結構包括一基板；設於基板上的複數個條帶；設於該些條帶其中之一的側壁與上表面上之金屬閘極。所述鰭式場效電晶體結構進一步包括一氧化物材料，設於金屬閘極及所述條帶之間，其中金屬閘極與氧化物材料間之介面的平均粗糙度的範圍是約0.1nm至約0.2nm。
在一些實施例中，所述鰭式場效電晶體結構是設於電路之I/O區域中。
在一些實施例中，氧化物材料的厚度介於約1.0nm至約4.0nm之間。
在一些實施例中，金屬閘極與氧化物材料之間的介面不包含多晶矽。
100‧‧‧鰭
101‧‧‧多晶矽層
102‧‧‧閘極氧化物
103‧‧‧介面
200、500‧‧‧方法
201、202、203、204、205‧‧‧步驟
501、502、503、504、505‧‧‧步驟
301、601、801‧‧‧基板
302、802‧‧‧條帶
303、603、803‧‧‧氧化物材料
304‧‧‧矽層
305a、305b、406‧‧‧介面
605a、605b‧‧‧介面
306、805‧‧‧隔離物
401‧‧‧非晶矽層
402‧‧‧上塗覆層
403‧‧‧多晶矽晶粒
404‧‧‧多晶矽晶粒
405‧‧‧下塗覆層
600、800‧‧‧鰭式場效電晶體結構
602‧‧‧鰭結構
602a、802a‧‧‧上表面
602b、802b‧‧‧側壁
604‧‧‧碳摻雜矽層
804‧‧‧金屬閘極
804a‧‧‧覆蓋層
804b‧‧‧摻雜層
804c‧‧‧傳導層
806‧‧‧凹部
807‧‧‧突出部
808‧‧‧介面
在閱讀了下文實施方式以及附隨圖式時，能夠最佳地理解本揭露的多種態樣。應注意到，根據本領域的標準作業習慣，圖中的各種特徵並未依比例繪製。事實上，為了能夠清楚地進行描述，可能會刻意地放大或縮小某些特徵的尺寸。
圖1A是習知鰭式場效電晶體結構在經過高於攝氏700度之退火製程後的剖面圖；圖1B是習知鰭式場效電晶體結構在經過高於攝氏700度之退火製程後的放大剖面圖；圖2是根據本揭露一些實施例，形成一鰭式場效電晶體結構之流程圖；圖3A-3E為根據本揭露一些實施例，製備鰭式場效電晶體結構之多種製程的部分剖面圖；圖3F為經過退火製程後之習知多晶矽閘極的剖面圖；圖3G為根據本揭露一些實施例退火製程後之原位碳摻雜多晶矽閘極的剖面圖；圖4A為經過蝕刻製程前之未退火非晶矽的剖面圖；圖4B為經過蝕刻製程後之未退火非晶矽的剖面圖；圖4C為經過蝕刻製程前之多晶矽(退火非晶矽)的剖面圖；圖4D為經過蝕刻製程後之多晶矽(退火非晶矽)的剖面圖；圖5為根據本揭露一些實施例，形成鰭式場效電晶體結構之流程圖；圖6A-6D為根據本揭露一些實施例，製備鰭式場效電晶體結構之多種步驟的部分剖面圖； 圖6E為根據本揭露一些實施例，經過退火製程後之原位碳摻雜多晶矽閘極的剖面圖；圖6F為根據本揭露一些實施例，經過佈植製程前之異位碳摻雜矽閘極的剖面圖；圖6G為根據本揭露一些實施例，經過佈植製程後之異位碳摻雜多晶矽閘極的剖面圖；圖6H為根據本揭露一些實施例，經過退火製程後之異位碳摻雜多晶矽閘極的剖面圖；圖7表示在不同熱退火條件下之標準化多晶粒大小；圖8A為根據本揭露一些實施例之具有金屬閘極的鰭式場效電晶體結構；圖8B為鰭式場效電晶體結構之閘極氧化物與金屬閘極間介面的剖面圖。
以下揭示內容提供了多種實施方式或例示，其能用以實現本揭示內容的不同特徵。下文所述之元件與配置的具體例子係用以簡化本揭示內容。當可想見，這些敘述僅為例示，其本意並非用於限制本揭示內容。舉例來說，在下文度描述中，將一第一特徵形成於一第二特徵上或之上，可能包含某些實施例其中所述的第一與第二特徵彼此直接接觸；且也可能包含某些實施例其中還有而外的元件形成於上述第一與第二特徵之間，而使得第一與第二特徵可能沒有直接接觸。此外，本揭示內容可能會在多個實施例中重複使用元件符號和/或標號。此種重複使用乃是基於簡潔與清楚的目的，且其本身不代表所討論的不同實施例和/或組態之間的關係。
再者，在此處使用空間上相對的詞彙，譬如「之下」、「下方」、「低於」、「之上」、「上方」及與其相似者，可能是為了 方便說明圖中所繪示的一元件或特徵相對於另一或多個元件或特徵之間的關係。這些空間上相對的詞彙其本意除了圖中所繪示的方位之外，還涵蓋了裝置在使用或操作中所處的多種不同方位。可能將所述設備放置於其他方位(如，旋轉90度或處於其他方位)，而這些空間上相對的描述詞彙就應該做相應的解釋。
下文詳細說明各實施例的製造與使用。然而，當可理解，本揭露提出了多種可用的發明性概念，且可實作於多種特定脈絡中。此處提及的具體實施例僅在說明製造與使用本發明之特定方式，而不應用以限制本發明。
在習知鰭式場效電晶體元件的製備步驟中，當於鰭式場效電晶體元件的閘極上形成閘極氧化物之後，會形成未摻雜矽層。相較於形成未摻雜矽層之後的某些後續步驟，上述未摻雜矽層是在較低的溫度(如，約攝氏530度)下所形成。然而，當在較高的溫度下進行操作時，會在矽層的不同位置形成具有不同方向之晶粒，上述位置包括鰭式場效電晶體結構之閘極氧化物與未摻雜矽層之間的介面。未摻雜矽層在高於約攝氏700度的溫度下很容易再結晶。再結晶之未摻雜矽層的體積會比沒有再結晶之矽層來得大。所述體積擴張會導致閘極氧化物與矽層間的介面粗糙度變大，且所述的粗糙度會影響最終產品之閘極氧化物與金屬閘極之間的介面。再結晶矽層的體積擴張也會危及金屬閘極尺寸的一致性，且因而會影響其效能。此外，金屬閘極與閘極氧化物之間的粗糙度會導致具有金屬閘極之鰭式場效電晶體元件出現較大的漏電流。
圖1A為經過退火製程後，複數個鰭100的剖面圖。在鰭100的閘極氧化物102上，形成了再結晶多晶矽層101。圖1B是多晶矽層101再結晶後，閘極氧化物102與多晶矽層101間之介面103的放大剖面圖。閘極氧化物102與多晶矽層101間的介面103之形狀是不規則 的。在一些實施例中，閘極氧化物102與多晶矽層101間的介面103之粗糙度可能會影響鰭式場效電晶體的效能。
為了減少矽層之再結晶，圖2為方法200之流程圖。其係在形成鰭式場效電晶體元件的過程中引入碳摻雜矽層。方法200包括多個步驟。參照圖2至圖3E，在步驟201中，提供基板301，如圖3A所示。在一些實施例中，基板包括矽。在步驟202中，於基板301上形成複數個條帶302，如圖3B所示。該些條帶302之材料通常和基板301的材料相同。圖3C之剖面圖詳細繪示了圖3B之鰭式場效電晶體結構300，其中示意的剖面圖是沿著圖3B之A-A'線段的切面所得。鰭式場效電晶體結構300包括基板301與複數個條帶302。於基板301上形成隔離物306，如圖3C所示。在步驟203中，於該些條帶302與隔離物306上形成氧化物材料303，如圖3D所示。
在步驟204中，在第一溫度下於氧化物材料303上形成矽層304，如圖3E所示。矽層304係沈積於條帶302上。在形成矽層304的過程中，將濃度在約5E19/cm3至約1E22/cm3之間的碳植入所述矽層304。在一些實施例中，用以形成矽層304的第一溫度介於約攝氏450度至約攝氏650度之間，通常在攝氏480度至攝氏620度之間。在一些實施例中，矽層304是在約0.2托(torr)至約5.0托的壓力下形成。在形成矽層304時，亦可引入包括SiH4、C2H4或H2之氣體。在本揭露中，於形成矽層的同時引入摻雜氣體的摻雜製程稱為原位摻雜製程。
在步驟205中，將溫度提高至高於第一溫度之第二溫度。舉例來說，在條帶302中形成輕摻雜汲極(lightly-doped drain，LDD)之製程通常是在高於約攝氏700度的溫度下進行；而源極/汲極退火通常是在高於攝氏約1100度的溫度下進行。在這樣的高溫下，未摻雜矽層會在不同位置再結晶，所述位置包括閘極氧化物材料303與矽層304間的介面305a與305b。
圖3F是圖3E虛線部分內之介面305a及/或305b的剖面圖。圖3F顯示在退火製程後未進行碳摻雜之習知多晶矽閘極。在閘極氧化物303與矽層304間的介面305a及/或305b處形成了再結晶之矽晶粒。圖3G為根據本揭露一些實施例，經過退火製程後之原位碳摻雜多晶矽閘極的剖面圖。碳摻雜矽之再結晶晶粒遠小於習知未經過碳摻雜之矽層的再結晶晶粒，如圖3F所示。
在於閘極氧化物303上形成矽層304之後的退火製程過程中，會在隨機的位置出現不同大小及方向的多晶矽晶粒，這些位置包括閘極氧化物303與矽層304間的介面305a及/或305b。在一些實施例中，多晶矽晶粒的方向(grain orientation)可以是<100>、<110>與<111>。圖3F顯示圖3E之虛線部分所示之閘極氧化物303與矽層304間的介面305a及/或305b在經過退火製程後的微結構。圖3F中所示晶粒的大小與方向可能不同。在一些實施例中，圖3F所示之多晶矽晶粒包含<111>之方向。圖3G顯示圖3E之虛線部分所示之閘極氧化物303與矽層304間的介面305a及/或305b在經過退火製程後的微結構。在一些實施例中，圖3G所示之多晶矽晶粒包括<111>之方向。當可理解，原位碳摻雜矽層之晶粒大小通常小於沒有碳摻雜之矽層的晶粒大小，因此，原位碳摻雜矽層中之<111>晶粒通常小於沒有碳摻雜之矽層中的<111>晶粒。因此，可以藉由將碳雜質引入至矽層304中，來降低<111>在閘極氧化物303與原位碳摻雜矽層304間的介面305a及/或305b處所形成之晶粒的大小。在一些實施例中，原位碳摻雜矽層中之平均<111>晶粒大小為約0.02~0.07μm。
由於晶粒的結晶結構不同，不同方向之晶粒對不同種類的蝕刻物可能具有不同的耐受性。在一些實施例中，再結晶之矽晶粒具有<100>、<110>與<111>中的至少一種方向。為了移除位於閘極氧化物303與矽層304間的介面305a及/或305b之晶粒，可施用一或多 種蝕刻物。在一些實施例中，所述蝕刻物可包含氫氧化鋁(NH4OH)。在一些實施例中，以蝕刻物NH4OH：H2O(NH4OH含量為3.7wt%)在攝氏40度的蝕刻溫度下進行濕式蝕刻，在此條件下對於方向為<100>、<110>與<111>之多晶矽晶粒的相對蝕刻率分別是100、37與3。在進行蝕刻製程之後，方向<111>之晶粒仍然會留存，而方向<100>與<110>之晶粒則會被移除。殘留的<111>晶粒會使得金屬閘極與閘極氧化物之間的粗糙度較大。這會導致具有金屬閘極之鰭式場效電晶體元件中出現較大的漏電流，且會使得鰭式場效電晶體元件不合格。藉由使用上文所述之原位碳摻雜矽層，可將<111>多晶矽之平均晶粒大小有效地縮減至一預定值以下，且因此相較於未經碳摻雜的較大<111>晶粒，此種較小的<111>晶粒較容易被移除。
現在參照圖4A-4D。圖4A為進行蝕刻製程前之未退火非晶矽的剖面圖。非晶矽層401夾設於上塗覆層402與下塗覆層405之間。圖4B顯示經過蝕刻製程後，未退火非晶矽之剖面圖。在蝕刻後，圖4B中夾設於上塗覆層402與下塗覆層405間的非晶矽層401明顯比圖4A中來得薄。非晶矽層401與上塗覆層402間的上介面406仍然相當平滑。圖4C為蝕刻製程前之多晶矽(經退火非晶矽)的剖面圖。在退火製程之後，非晶矽層401中會形成多晶矽晶粒403。圖4D顯示經過蝕刻製程後，多晶矽(經退火非晶矽)的剖面圖。可形成具有不同大小的多晶矽晶粒404。以蝕刻物NH4OH：H2O(體積比5：1)在攝氏50度的蝕刻溫度下進行濕式蝕刻。在蝕刻製程後，由於並未完全移除<111>晶粒，非晶矽層401與上塗覆層402間的上介面406比起圖4B所示的介面406更為粗糙。
圖5為方法500之流程圖，其係在形成鰭式場效電晶體元件的過程中形成碳摻雜非晶矽層或碳摻雜多晶矽層。方法500包括數個步驟。參照圖5至圖6D，在步驟501中，提供基板601，如圖6A所 示。在一些實施例中，基板包括矽。在步驟502中，形成由基板601突出之鰭結構，如圖6B所示。在一些實施例中，鰭結構602的結構和基板601相同。在步驟503中，於基板601上形成隔離結構，譬如淺溝槽隔離物，如圖6C所示。圖6C之剖面圖詳細繪示了圖6B之鰭式場效電晶體結構600，其中示意的剖面圖是沿著圖6B之B-B'線段的切面所得。鰭式場效電晶體結構600包括基板601與鰭結構602。於基板601上形成隔離物606，如圖6C所示。在步驟504中，於鰭結構602之上表面602a與側壁602b上形成氧化物材料603，如圖6D所示。
在步驟505中，於氧化物材料603與鰭結構602上形成碳摻雜矽層604，如圖6E所示。現在參照圖6A-6E。在一些實施例中，碳摻雜矽層604可以是碳摻雜非晶矽層或碳摻雜多晶矽層。可在後續的高溫製程中，於高於攝氏700度的溫度下，將碳摻雜非晶矽層轉換為碳摻雜多晶矽層。在形成碳摻雜矽層604的過程中，將濃度介於約5E19/cm3至約1E22/cm3之間的碳植入碳摻雜矽層604內。若增加碳原子濃度，則碳原子會更加均勻地摻雜於矽層中。
在一些實施例中，在約攝氏450度至約攝氏650度的第一溫度下形成碳摻雜矽層604，上述溫度通常是在攝氏480度至攝氏620度之間。在一些實施例中，在約0.2托至約5.0托的壓力下形成碳摻雜矽層604。在形成碳摻雜矽層604的過程中，引入包括SiH4、C2H4或H2之氣體。在本揭露中，於形成矽層的同時引入摻雜氣體的摻雜製程稱為原位摻雜製程。圖6E中以虛線圍繞之介面605a或605b的剖面圖實質上和圖3G所示者相同。
於一電路中，原位摻雜可應用在電路中之接收輸入/輸出(I/O)功率的鰭式場效電晶體元件上。在一些實施例中，I/O元件所接收的功率高於電路中其他元件所接收者。在一些實施例中，可利用上述原位摻雜製程來製備電路之I/O區域中的元件。
現在參照圖6A-6D、6F與6G。上文已敘述了形成圖6A-6D所述結構之流程。為求簡潔，用以形成圖6A-6D之結構的流程此處不再重複。在一些實施例中，當在鰭結構602與隔離物606上形成氧化物材料603(如圖6D所示)之後，接著在氧化物材料603上形成矽層604，如圖6F所示。在形成矽層604之後，將碳及/或氮植入矽層604，佈植濃度介於約5E19/cm3至約1E22/cm3之間，如圖6G所示。在一些實施例中，在約攝氏700度至約攝氏900度的溫度下，將矽層604退火處理約10至約60分鐘。在一些實施例中，在氮環境中進行矽層604之退火。在形成矽層604之後進行碳及/或氮的佈植製程。在本揭露中，將此種製程稱為異位摻雜製程。
圖6H為根據本揭露一些實施例，經過退火製程後之異位碳摻雜多晶矽閘極的剖面圖。碳摻雜矽之再結晶之晶粒小於習知未摻雜矽層的再結晶晶粒大小。在一些實施例中，異位碳摻雜矽之再結晶之晶粒大小可能大於原位碳摻雜矽層之再結晶之晶粒大小。
於一電路中，可對電路之輸入/輸出(I/O)功率接收的鰭式場效電晶體元件進行異位摻雜。在一些實施例中，I/O元件所接收的功率高於電路中其他元件所接收者。在一些實施例中，可利用上述異位摻雜製程來製備電路之I/O區域中的元件
現在參照圖6A-6E與圖6G。在一些實施例中，圖6A-6E顯示了於鰭式場效電晶體結構形成原位碳摻雜矽層之剖面圖。然而，在一些實施例中，可利用碳及/或氮原子進一步對原位碳摻雜矽層進行異位摻雜，如圖6G所示，以便達到約5E19/cm3至約1E22/cm3之摻雜物濃度。在一電路中，可對鰭式場效電晶體元件進行原位摻雜、異位摻雜或其組合。在一些實施例中，可利用上述原位與異位摻雜製程來製備電路之I/O區域中的元件。
圖7表示在不同熱退火條件下之標準化多晶粒大小。 隨著製程溫度提高，標準化之多晶粒大小也會變大。隨著製程所需的時間變長，標準化之多晶粒大小也會增加。在攝氏850度與40分鐘的異位氮摻雜條件下，異位碳摻雜多晶矽層的晶粒大小是不含碳之多晶矽層的晶粒大小之75%(如，一標準化之晶粒大小可由約2.1縮減至約1.6)。將碳及/或氮引入矽層604中之佈植製程可限制位於閘極氧化物603及矽層604間之介面605a及/或605b處之晶粒發生再結晶。
在於鰭式場效電晶體結構的中形成矽層604的過程中，可能會出現兩個問題。第一個問題是可能會形成方向<111>之晶粒。已知對於以濕式蝕刻物NH4OH：H2O(NH4OH含量為3.7wt%)在攝氏40度下進行的濕式蝕刻製程來說，方向<111>之晶粒的蝕刻率最低。在利用蝕刻製程來移除位於介面605a及/或605b的晶粒之後，可能無法完全移除<111>晶粒。回到圖4C與4D，在形成鰭式場效電晶體結構的過程中，可能會形成方向<111>的矽晶粒404且無法完全移除此種<111>晶粒。舉例來說，以多晶矽閘極來置換金屬閘極之製程涉及對多晶矽層進行蝕刻製程。多晶矽層中之<111>晶粒可以防制完全移除多晶矽晶粒，且因而會導致在鄰近閘極氧化物處存在一粗糙的蝕刻介面。因此，後續形成於金屬閘極與閘極氧化物間的介面不但粗糙而且還會被這些未移除的多晶矽晶粒隔開。因為閘極氧化物603與金屬閘極間的介面605a或605b之粗糙度會導致具有金屬閘極之鰭式場效電晶體元件出現較大的漏電流，可能會減損鰭式場效電晶體元件之效能。因此，如果能夠將多晶矽晶粒的大小控制在較小的尺寸，就能夠更輕易地移除<111>晶粒，且使得在閘極置換過程中經蝕刻製程後的殘留多晶矽變少。為了控制閘極在氧化物603及矽層604間之介面605a及/或605b處的<111>晶粒所造成的問題，可利用碳及/或氮來進行原位及/或異位摻雜，以縮減晶粒大小。
除了上述對於鰭式場效電晶體元件之閘極氧化物603 及矽層604間的多晶矽層之粗糙度與不完全移除相關的影響之外式，在閘極氧化物603與金屬閘極間的介面605a及/或605b處，於再結晶過程中因為晶粒成長所導致的體積擴張也會降低鰭式場效電晶體元件的產率，因為此種機械變形會進一步強化上述介面605a及/或605b之粗糙度。
參照圖8A，於閘極氧化物材料803上形成金屬層804。圖8A是鰭式場效電晶體結構800的剖面圖，其具有金屬閘極804。鰭式場效電晶體結構800包括基板801、位於基板801上的複數個條帶802以及位於該些條帶802其中之一的側壁802b與上表面802a之上的金屬閘極804。在基板801上形成隔離物805。鰭式場效電晶體結構進一步包括金屬閘極804與該些條帶802間的氧化物材料803。所述氧化物材料803的厚度介於約1至約4nm之間。
同樣參照圖8A，在利用蝕刻製程移除碳摻雜矽層之後，幾乎可以完全移除位於矽層與氧化物材料803間之介面802a及/或802b處的晶粒。之後在氧化物材料803上形成金屬閘極804。因此，金屬閘極804與氧化物材料803間的介面802a及/或802b不會包含未移除之多晶矽。除此之外，於再結晶過程中發生之矽晶粒的體積擴張可能會導致氧化物材料803變形。之後在氧化物材料803上形成金屬閘極804。金屬閘極804與氧化物材料803的介面粗糙就會影響到鰭式場效電晶體結構800的最終產物。在一些實施例中，碳摻雜矽層所經歷的再結晶生長較少，且因此矽晶粒的體積擴張沒有未經碳摻雜之矽層來得嚴重。因此，可以有效減少金屬閘極804與氧化物材料803間之介面的粗糙度。
鰭式場效電晶體結構800之金屬閘極804可包含多層。參照圖8A，金屬閘極804具有一三層結構。此種三層結構包括覆蓋層804a、摻雜層804b與傳導層804c。摻雜層804b用以提供摻雜物給傳導 層804c；在一些實施例中，摻雜物為鋁離子。覆蓋層804a可包含TiN、TaN或其他材料。覆蓋層804a形成於摻雜層804b上方。可利用多種沈積技術來形成覆蓋層804a，譬如ALD、PVD、CVD、PECVD、或其他適當技術。在一些實施例中，覆蓋層804a是非必要的層，故可由此處所述的三層結構中將其移除。在圖8A中，將金屬閘極804共形地沈積於複數個條帶802其中之一的上表面802a與側壁802b之上。該些條帶802由隔離物805所隔開。
圖8B為圖8A之鰭式場效電晶體結構800之閘極氧化物與金屬閘極間介面的詳細剖面圖，其中示意的剖面圖是沿著圖8A之C-C'線段的切面所得。圖8B顯示利用習知方法來製備鰭式場效電晶體結構時(譬如，並未以碳原子摻雜多晶矽閘極時)，在金屬閘極804之覆蓋層804a與氧化物材料803之間形成一粗糙表面。於金屬閘極804之覆蓋層804a與氧化物材料803間之介面808發生再結晶的過程中，晶粒的體積擴張會使得介面808變形。在蝕刻製程後，氧化物材料803中會形成凹部806。在蝕刻製程之後，在氧化物材料803的粗糙表面上形成金屬閘極804的覆蓋層804a。覆蓋層804a會形成於凹部806中。在一些實施例中，覆蓋層804a與氧化物材料803之間的突出部807可能是未移除之多晶矽晶粒。凹部806與突出部807造成了介面808處之平均粗糙度。由於金屬閘極804的形狀被預期外地改變，會減損鰭式場效電晶體元件的效能。相較之下，當利用本揭露上文所述之原位摻雜及/或異位摻雜時，可減低再結晶之晶粒大小與體積擴張，且可在金屬閘極804與氧化物材料803間形成一較平滑的介面。在一些實施例中，金屬閘極804之覆蓋層804a與氧化物材料803間之介面808可能不含未移除之多晶矽，亦即，覆蓋層804a可和氧化物材料803接觸而不會被未移除之多晶矽所隔開。在一些實施例中，金屬閘極804與氧化物材料803間之介面的平均粗糙度介於約0.1nm至0.2nm之間。如此一來，可以 提升鰭式場效電晶體元件之效能。
在一電路中，可對電路中接收輸入/輸出(I/O)功率的鰭式場效電晶體元件進行原位摻雜、異位摻雜或二者之組合。在一些實施例中，相較於電路中的其他元件，I/O元件會接收到較大的功率。在一些實施例中，上述原位摻雜、異位摻雜或其組合可用以製備一電路之I/O區域中的元件。
本揭露的一些實施例提出了一種形成鰭式場效電晶體的方法。所述方法包括提供一基板，於基板上形成複數個條帶，於該些條帶其中之一的上表面與側壁上形成一氧化物材料，以及在第一溫度下，於氧化物材料上形成碳摻雜矽層。所述方法進一步包括將所述溫度提高至大於第一溫度之第二溫度，其中形成碳摻雜矽層包括原位摻雜製程。
在一些實施例中，原位摻雜製程包括引入包括SiH4、C2H4或H2之氣體。
在一些實施例中，第一溫度介於約450℃至約650℃之間。
在一些實施例中，原位摻雜製程是在約0.2至約5.0托之間的壓力下進行。
在一些實施例中，碳摻雜矽層的濃度在約5E19/cm3至約1E22/cm3的範圍中。
在一些實施例中，第二溫度高於約700℃。
在一些實施例中，碳摻雜矽層包括<111>多晶矽。
在一些實施例中，<111>多晶矽的平均晶粒大小小於一預定值。
本揭露的一些實施例提出一種形成半導體元件的方法。所述方法包括提供一基板，形成由基板突出之一鰭結構，在基板 上形成淺溝槽隔離物，以及在鰭結構上形成一氧化物材料。所述方法進一步包括於氧化物材料上形成碳摻雜非晶矽層或碳摻雜多晶矽層，其中形成碳摻雜非晶矽層或碳摻雜多晶矽層包括摻雜範圍介於5E19/cm3至約1E22/cm3間之碳。
在一些實施例中，形成碳摻雜矽層包括原位摻雜製程、異位摻雜製程或其組合。
在一些實施例中，異位摻雜製程包括以碳與氮來佈植上述非晶矽層或多晶矽層。
在一些實施例中，原位摻雜製程包括在形成碳摻雜非晶矽層或碳摻雜多晶矽層時，引入SiH4、C2H4與H2其中之一。
在一些實施例中，碳摻雜多晶矽層係由碳摻雜非晶矽層在高於攝氏700度的溫度下轉換所得。
在一些實施例中，碳摻雜多晶矽層的晶粒大小約為不含碳之多晶矽層的晶粒大小之75%。
在一些實施例中，碳摻雜多晶矽層包括選自<100>、<110>與<111>之晶粒方向。
在一些實施例中，所述方法包括利用蝕刻製程以移除碳摻雜非晶矽層或碳摻雜多晶矽層。
本揭露的一些實施例提供一種鰭式場效電晶體結構。所述的鰭式場效電晶體結構包括一基板；設於基板上的複數個條帶；設於該些條帶其中之一的側壁與上表面上之金屬閘極。所述鰭式場效電晶體結構進一步包括一氧化物材料，設於金屬閘極及所述條帶之間，其中金屬閘極與氧化物材料間之介面的平均粗糙度的範圍是約0.1nm至約0.2nm。
在一些實施例中，所述鰭式場效電晶體結構是設於電路之I/O區域中。
在一些實施例中，氧化物材料的厚度介於約1.0nm至約4.0nm之間。
在一些實施例中，金屬閘極與氧化物材料之間的介面不包含多晶矽。
上文的敘述簡要地提出了本發明某些實施例之特徵，而使得本發明所屬技術領域具有通常知識者能夠更全面地理解本揭示內容的多種態樣。本發明所屬技術領域具有通常知識者當可明瞭，其可輕易地利用本揭示內容作為基礎，來設計或更動其他製程與結構，以實現與此處所述之實施方式相同的目的和/或達到相同的優點。本發明所屬技術領域具有通常知識者應當明白，這些均等的實施方式仍屬於本揭示內容之精神與範圍，且其可進行各種變更、替代與更動，而不會悖離本揭示內容之精神與範圍。
200‧‧‧方法
201~205‧‧‧步驟

Claims (10)

  1. 一種形成一鰭式場效電晶體的方法，包括：提供一基板；形成複數個條帶於該基板上；形成一氧化物材料於該些條帶其中之一的一上表面與一側壁上；於一第一溫度下，形成一碳摻雜矽層於該氧化物材料上；以及提升該溫度至高於該第一溫度之一第二溫度，其中該形成該碳摻雜矽層包括一原位摻雜製程。
  2. 如請求項1所述之方法，其中該原位摻雜製程包括引入包括SiH4、C2H4或H2之氣體。
  3. 如請求項1所述之方法，其中該第一溫度介於約450℃至約650℃之間。
  4. 如請求項1所述之方法，其中該原位摻雜製程是在約0.2至約5.0托之間的一壓力下進行。
  5. 如請求項1所述之方法，其中該碳摻雜矽層之一濃度範圍是在約5E19/cm3至約1E22/cm3之間。
  6. 如請求項1所述之方法，其中該第二溫度高於約700℃。
  7. 如請求項1所述之方法，其中該碳摻雜矽層包括<111>多晶矽。
  8. 如請求項7所述之方法，其中該<111>多晶矽之一平均晶粒大小小於一預定值。
  9. 一種形成一半導體元件的方法，包括：提供一基板；形成由該基板突出之一鰭結構；形成淺溝槽隔離物於該基板上； 形成一氧化物材料於該鰭結構上；形成一碳摻雜非晶矽層或一碳摻雜多晶矽層於該氧化物材料上，其中該形成一碳摻雜非晶矽層或一碳摻雜多晶矽層包括摻雜一範圍在約5E19/cm3至約1E22/cm3之間的碳。
  10. 一種鰭式場效電晶體結構，包括：一基板；複數個條帶，設於該基板上；一金屬閘極，設於該些條帶其中之一的一側壁與一上表面上；一氧化物材料，設於該金屬閘極與該些條帶之間；其中該金屬閘極與該氧化物材料間的一介面之一平均粗糙度的範圍是約0.1nm至約0.2nm。
TW104138919A 2015-03-16 2015-11-24 鰭式場效電晶體結構及其製備方法 TWI585901B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/658,511 US9406675B1 (en) 2015-03-16 2015-03-16 FinFET structure and method of manufacturing the same

Publications (2)

Publication Number Publication Date
TW201705373A TW201705373A (zh) 2017-02-01
TWI585901B true TWI585901B (zh) 2017-06-01

Family

ID=56507298

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104138919A TWI585901B (zh) 2015-03-16 2015-11-24 鰭式場效電晶體結構及其製備方法

Country Status (2)

Country Link
US (2) US9406675B1 (zh)
TW (1) TWI585901B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108962903B (zh) * 2018-09-19 2024-02-02 长江存储科技有限责任公司 半导体结构
CN109326507B (zh) * 2018-09-19 2021-07-16 长江存储科技有限责任公司 存储器的形成方法
US11145727B2 (en) * 2019-10-29 2021-10-12 Nanya Technology Corporation Semiconductor structure and method of forming the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040266115A1 (en) * 2003-06-25 2004-12-30 Bor-Wen Chan Method of making a gate electrode on a semiconductor device
US20100123926A1 (en) * 2008-11-17 2010-05-20 Canon Kabushiki Kaisha Image forming apparatus and control method thereof
US8298925B2 (en) * 2010-11-08 2012-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming ultra shallow junction

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5229711B2 (ja) * 2006-12-25 2013-07-03 国立大学法人名古屋大学 パターン形成方法、および半導体装置の製造方法
US7667271B2 (en) 2007-04-27 2010-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistors
US8120063B2 (en) * 2008-12-29 2012-02-21 Intel Corporation Modulation-doped multi-gate devices
US8440517B2 (en) 2010-10-13 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET and method of fabricating the same
US8497528B2 (en) 2010-05-06 2013-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a strained structure
US9245805B2 (en) 2009-09-24 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Germanium FinFETs with metal gates and stressors
US8362575B2 (en) 2009-09-29 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Controlling the shape of source/drain regions in FinFETs
US8610240B2 (en) 2009-10-16 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit with multi recessed shallow trench isolation
US8729627B2 (en) 2010-05-14 2014-05-20 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel integrated circuit devices
US8796759B2 (en) 2010-07-15 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Fin-like field effect transistor (FinFET) device and method of manufacturing same
US8367498B2 (en) 2010-10-18 2013-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Fin-like field effect transistor (FinFET) device and method of manufacturing same
US8962400B2 (en) 2011-07-07 2015-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. In-situ doping of arsenic for source and drain epitaxy
US8841701B2 (en) 2011-08-30 2014-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device having a channel defined in a diamond-like shape semiconductor structure
US8723272B2 (en) 2011-10-04 2014-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of manufacturing same
US8723236B2 (en) 2011-10-13 2014-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of manufacturing same
US8847293B2 (en) 2012-03-02 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Gate structure for semiconductor device
US8836016B2 (en) 2012-03-08 2014-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures and methods with high mobility and high energy bandgap materials
US8785285B2 (en) 2012-03-08 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US8680576B2 (en) 2012-05-16 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS device and method of forming the same
US8729634B2 (en) 2012-06-15 2014-05-20 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with high mobility and strain channel
US9105570B2 (en) * 2012-07-13 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for introducing carbon to a semiconductor structure
US8809139B2 (en) 2012-11-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Fin-last FinFET and methods of forming same
US8853025B2 (en) 2013-02-08 2014-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET/tri-gate channel doping for multiple threshold voltage tuning
US9093514B2 (en) 2013-03-06 2015-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Strained and uniform doping technique for FINFETs
US8906789B2 (en) * 2013-03-13 2014-12-09 Taiwan Semiconductor Manufacturing Co., Ltd. Asymmetric cyclic desposition etch epitaxy
US9324870B2 (en) * 2013-09-09 2016-04-26 Globalfoundries Inc. Fin field effect transistor including asymmetric raised active regions
US9379021B2 (en) * 2013-10-03 2016-06-28 Applied Materials, Inc. Method to reduce K value of dielectric layer for advanced FinFET formation
US20150162438A1 (en) * 2013-12-11 2015-06-11 International Business Machines Corporation Memory device employing an inverted u-shaped floating gate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040266115A1 (en) * 2003-06-25 2004-12-30 Bor-Wen Chan Method of making a gate electrode on a semiconductor device
US20100123926A1 (en) * 2008-11-17 2010-05-20 Canon Kabushiki Kaisha Image forming apparatus and control method thereof
US8298925B2 (en) * 2010-11-08 2012-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming ultra shallow junction

Also Published As

Publication number Publication date
TW201705373A (zh) 2017-02-01
US20160307895A1 (en) 2016-10-20
US9716090B2 (en) 2017-07-25
US9406675B1 (en) 2016-08-02

Similar Documents

Publication Publication Date Title
TWI749275B (zh) 半導體裝置及其製造方法
US9281305B1 (en) Transistor device structure
US9536887B2 (en) Airgap structure and method of manufacturing thereof
TW201916115A (zh) 半導體結構的製造方法
TW201919236A (zh) 半導體裝置
TWI786612B (zh) 具有氣隙結構的半導體元件結構及其製備方法
TW201820631A (zh) 半導體裝置
TW202011518A (zh) 半導體裝置的形成方法
TWI585901B (zh) 鰭式場效電晶體結構及其製備方法
CN113437023A (zh) 半导体元件及其制造方法
TW202013462A (zh) 半導體裝置與其形成方法
TW201740453A (zh) 在電晶體的源極/汲極區域上的磊晶膜上選擇性蝕刻的方法
KR100603588B1 (ko) 낮은 콘택 저항을 갖는 반도체 소자 및 그 제조 방법
CN114678469A (zh) 半导体结构及其形成方法
CN110310926B (zh) 解决sram单元器件金属硅化物缺陷形成的方法
US9412833B2 (en) Narrow semiconductor trench structure
KR102400361B1 (ko) 반도체 소자 및 그 제조 방법
US20150129939A1 (en) Method and structure for forming contacts
JP6434862B2 (ja) 半導体装置の製造方法
JPWO2015097798A1 (ja) 柱状半導体装置の製造方法
CN101197280B (zh) 金属硅化物的形成方法
US10043888B2 (en) Method for forming a semiconductor structure
TWI825825B (zh) 形成半導體裝置的方法
TWI802885B (zh) 具有石墨烯基元素的半導體元件及其製備方法
CN114334830B (zh) 一种肖特基结源漏CMOS finFET及其制作方法