TWI580036B - 半導體元件、鰭式場效電晶體之形成方法及半導體元件之製造方法 - Google Patents

半導體元件、鰭式場效電晶體之形成方法及半導體元件之製造方法 Download PDF

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TWI580036B
TWI580036B TW104133884A TW104133884A TWI580036B TW I580036 B TWI580036 B TW I580036B TW 104133884 A TW104133884 A TW 104133884A TW 104133884 A TW104133884 A TW 104133884A TW I580036 B TWI580036 B TW I580036B
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layer
germanium
boron
metal
material stack
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TW104133884A
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TW201626560A (zh
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蔡俊雄
陳明德
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台灣積體電路製造股份有限公司
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Description

半導體元件、鰭式場效電晶體之形 成方法及半導體元件之製造方法
本發明係關於一種半導體技術，特別係關於一種半導體製造技術。
半導體積體電路(semiconductor integrated circuit；IC)歷經了快速的成長。積體電路之發展歷程中，當幾何尺寸(意即可利用製程產生之最小組件或電路)縮小時，功能密度(意即每一晶片區域中之互連元件數目)通常會相對地增加。此按比例縮小元件的製程，通常藉由增加生產效率與降低相關之成本以提供優勢。此按比例縮小元件的製程係增加了積體電路製造之複雜度。因此，本案之類似的製程發展對於積體電路製造之發展為必須的。
半導體積體電路微電子結構形成於半導體基材之內與其上以形成半導體元件。基材上具有以介電層隔開，且以圖案化方式形成的導電層。邏輯半導體積體電路微電子結構以及記憶半導體積體電路微電子結構中，半導體積體電路微電子結構的製造通常利用鰭式場效電晶體(Fin Field-Effect Transistor；FinFET)做為開關元件。半導體積體電路微電子結構之技術領域中，鰭式場效電晶體元件通常做為邏輯與記憶之半導體積體電路微電子結構的開關元件。此外，於半導體積體電路微電子結構之中，鰭式場效電晶體元件能輕易的被製造與縮放尺寸。
因此，於半導體積體電路微電子結構之技術領域中，鰭式場效電晶體係必要的元件。當半導體元件尺寸縮小的同時，強化鰭式場效電晶體之性能的方法將於本案中揭露。
本案提出一種半導體元件及其製造方法。本案之實施方式揭露了源極與閘極區域之接觸結構的接觸電阻(contact resistance；Rcsd)。由於接觸電阻蕭基能位障高的降低以及摻雜濃度的增加，使得降低接觸電阻。藉由摻雜隔離層摻雜設計、能階對位校正與選擇性局部高溫加熱以去除缺陷，以於具有高應變與高摻雜濃度的部分源極與閘極區域中，降低蕭基能位障高以及增加摻雜濃度。
依據本案之一實施方式之半導元件製造方法係包含於基材上方形成閘極結構。於該基材中形成鄰近該閘極結構之凹陷。於凹陷中磊晶形成應變材料堆疊。此應變材料堆疊係包含至少三層狀物，每一此些至少三層狀物係包含摻雜物。使用複數摻雜物共同佈植應變材料堆疊，此些摻雜物係包含硼、鍺、銦、錫或其組合。於應變材料堆疊上形成金屬 層。對金屬層與應變材料堆疊退火以形成金屬矽化物層。
依據本案之一實施方式之鰭式場效電晶體(Fin Field-Effect Transistor；FinFET)的製造方法係包含形成複數個鰭片，此些鰭片從基材延伸。於此些鰭片上方形成虛擬閘極結構。於此些鰭片中形成鄰近虛擬閘極結構之複數個凹陷。於此些鰭片中之此些凹陷中磊晶形成複數個應變材料堆疊，每一此些應變材料堆疊係包含錫鍺(germanium-tin；GeSn)層與硼摻雜矽鍺(boron-doped silicon-geranium；SiGeB)層。將硼、銦、錫、或其組合植入此些應變材料堆疊。於此些應變材料堆疊上形成金屬層。進行微波退火(multi-stage microwave anneal；MWA)製程於金屬層與此些應變材料堆疊上，以於此些應變材料堆疊上形成複數個金屬矽化物層。於此些應變材料堆疊之間形成金屬接點，此金屬接點連接此些金屬矽化物層。
依據本案之一實施方式之半導體元件係包含鰭片、閘極結構、金屬矽化物層、金屬接點以及應變材料堆疊。鰭片從基材延伸出。閘極結構位於鰭片之頂面與複數個側壁上。應變材料堆疊位於鰭片上並鄰近閘極結構。應變材料堆疊係包含第一硼摻雜矽鍺、第二硼摻雜矽鍺層以及硼摻雜鍺錫層。第二硼摻雜矽鍺層位於第一硼摻雜矽鍺層上，此第二硼摻雜矽鍺層之鍺濃度高於第一硼摻雜矽鍺層之鍺濃度。硼摻雜鍺錫(B-doped germanium-tin；GeSnB)層位於第二硼摻雜矽鍺層上。金屬矽化物層位於硼摻雜鍺錫層上。金屬接點位於金屬矽化物層上。
100‧‧‧晶圓
102‧‧‧基材
104‧‧‧條形半導體區
104‧‧‧替換性條形半導體區
106‧‧‧隔離區域
106‧‧‧淺溝槽隔離區域
108‧‧‧凹陷
110‧‧‧條形半導體
110’‧‧‧半導體鰭片
112‧‧‧閘極介電質
114‧‧‧閘極電極
116‧‧‧閘極間隙壁
118‧‧‧閘極結構
120‧‧‧凹陷
122‧‧‧應變材料堆疊
122’‧‧‧源極與閘極區域
122A‧‧‧第一磊晶層
122B‧‧‧第二磊晶層
122C‧‧‧第三磊晶層
122D‧‧‧第四磊晶層
123‧‧‧小平面
124‧‧‧同佈植製程
125‧‧‧蝕刻擋止層
126‧‧‧層間介電層
126A‧‧‧部分結構
128‧‧‧替換性閘極介電質
130‧‧‧替換性閘極
134‧‧‧接觸開口
136‧‧‧非晶化前植入製程
140‧‧‧金屬層
142‧‧‧金屬矽化物層
144‧‧‧接觸栓塞
54‧‧‧閘極介電質
56‧‧‧閘極結構
200‧‧‧步驟
202~226‧‧‧步驟
A-A‧‧‧線段
B-B‧‧‧線段
C-C‧‧‧線段
第1至12圖繪示依據一些實施方式所製造之鰭式場效電晶體，於中間製造階段下的剖面圖及透視圖。
第13圖繪示依據一些實施方式之鰭式場效電晶體的製造方法。
以下的說明將提供許多不同的實施方式或實施例來實施本揭露的主題。元件或排列的具體範例將在以下討論以簡化本揭露。當然，這些描述僅為部分範例且本揭露並不以此為限。例如，將第一特徵係形成在第二特徵上或上方，此一敘述不但包含第一特徵和第二特徵直接接觸的實施方式，也包含其他特徵形成在第一特徵與第二特徵之間，且在此情形下第一特徵和第二特徵不會直接接觸的實施方式。此外，本揭露可能會在不同的範例中重複標號或文字。重複的目的是為了簡化及明確敘述，而非界定所討論之不同實施方式及配置間的關係。
此外，空間相對用語如「下面」、「下方」、「低於」、「上面」、「上方」及其他類似的用語，在此是為了方便描述圖中的一個元件或特徵和另一個元件或特徵的關係。空間相對用語除了涵蓋圖中所描繪的方位外，該用語更涵蓋裝置在使用或操作時的其他方位。也就是說，當該裝置的方位與圖式不同(旋轉90度或在其他方位)時，在本文中所使用的空間相 對用語同樣可相應地進行解釋。
總體而言，本案為接觸結構及其形成方法，以產生降低接觸電阻(reduced contact resistance；Rcsd)。特別係本揭露於下文所揭露之實施方式，例如：鰭式場效電晶體(Fin Field-Effect Transistor；FinFETs)之源極區域與汲極極區域，其接觸結構之下降接觸電阻的降低。藉由降低蕭基能位障高(Schottky barrier height)與增加摻雜濃度，以達到下降接觸電阻的降低(見方程式(1)所示)。蕭基能位障高之降低與摻雜濃度之增加，至少部分源自於具有高應變及高摻雜濃度之源極區域與汲極區域，其使用摻雜隔離層設計(dopant segregation design)、能階對位校準(band alignment tuning)以及選擇性局部高溫加熱(selective local high-temperature heating)，以減少介面缺陷。
第1至12圖繪示依據一些實施方式所製造之鰭式場效電晶體，於中間製造階段下的剖視圖及透視圖。第13圖繪示為第1至12圖所示之製程流程圖。
第1圖繪示為初始結構之透視圖。初始結構係包含晶圓100。此晶圓100係包含基材102、複數條形半導體104及複數隔離區域106。基材102之材質可包含半導體材料，例如：矽、鍺、金剛石、或其他類似的材料。可選地，基材102之材質可包含複合材料，例如：矽鍺化物(silicon germanium)、碳矽化物(silicon carbide)、砷鎵化物(gallium arsenic)、砷銦化物(indium arsenide)、磷銦化 物(indium phosphide)、矽鍺碳化物(silicon germanium carbide)、砷化鎵磷化物(gallium arsenic phosphide)、磷銦鎵化物(gallium indium phosphide)或其組合或其他類似的複合材料。此外，基材102之材質可包含絕緣底覆矽(silicon-on-insulator；SOI)基材。一般而言，絕緣底覆矽基材可包含層狀半導體材料，例如：磊晶矽(epitaxial silicon)、鍺(germanium)、矽鍺化物(silicon germanium)、絕緣底覆矽、絕緣底覆矽鍺(silicon germanium on insulator；SGOI)或其組合。基材102可摻雜p型摻雜物，例如：硼、鋁、鎵或其組合或其他類似的p型摻雜物。此外，基材102亦可摻雜此領域中具有通常知識者所習知的n型摻雜物。
基材102可包含主動元件(未繪示於第1圖)。此領域中具有通常知識者可了解到，因鰭式場效電晶體於結構上與功能上的設計需求，可使用廣泛且多樣的元件來製造鰭式場效電晶體。此些元件可包含：晶體管、電容器、電阻器或其組合或類似的元件。此些元件可由任何適合的方法形成。僅部分的基材102繪示於圖中，而此以足夠說明本案之實施方式。
條形半導體104(步驟200)與絕緣區域106(步驟202)係形成於基材102上方。絕緣區域106係從基材102的頂面延伸至基材102中。絕緣區域106可為淺溝槽隔離(Shallow Trench Isolation；STI)區域。淺溝槽隔離區域106之形成可包含將基材102用蝕刻之方式以形成溝渠(未 示於圖)，並將介電材料填充溝渠，以形成淺溝槽隔離區域106。淺溝槽隔離區域106之材質可包含，但不限於，由高濃度電漿所沉積之矽氧化物、或依據不同的製程方式所形成之其他介電材料。於本文中，位於鄰近此些淺溝槽隔離區域106之間的部分基材102為條形半導體104。條形半導體104之頂面與淺溝槽隔離區域106之頂面可實質上呈水平，例如沉積淺溝槽隔離區域106的材料之後，執行化學機械研磨(chemical mechanical polish；CMP)使其呈水平。此外，此些頂面亦可有些微不同的水平。
第2、3圖繪示依據一些實施方式，利用第3圖中的條形半導體110以揭露於第1圖中的替換性條形半導體104。於另一實施方式中，於第1圖中的條形半導體104未被替換，因此，其作用如第4至12圖繪示之條形半導體110。參照第2圖，至少條形半導體104的上部或大致上之整體可被移除。因此，凹陷108係形成於淺溝槽隔離區域106中。接著，於凹陷108中進行磊晶成長條形半導體110，以形成如第3圖所繪示之結構。條形半導體110之晶格常數可大於、實質上等於或小於基材102之晶格常數。於一些實施方式中，條形半導體110之材質可包含矽鍺(silicon germanium；SiGe)、三-五族化合物半導體、或其他類似的材料。條形半導體110中矽鍺的鍺原子百分比可約大於15%、或介於約15%到約60%之間。鍺原子百分比亦可更高。條形半導體110可實質上為純鍺區域，此純鍺區域之鍺原子百分比可大於約95%，但不以此為限。於進行條形半導 體110的磊晶期間，p型雜質(例如：硼)可為磊晶的原位摻雜。接著，淺溝槽隔離區域106可被凹陷，使得條形半導體110的頂部高於淺溝槽隔離區域106之頂面，以形成半導體鰭片110’(步驟204)(如第4圖所示)。
於第4圖中，閘極結構118係形成於半導體鰭片110’之上方。閘極結構118可包含閘極介電質112、閘極電極114、與閘極間隙壁116。閘極結構118係橫跨於複數半導體鰭片110’與淺溝槽隔離區域106之上方。閘極結構118具有實質上與半導體鰭片110’之縱軸相互垂直的縱軸。於一些實施方式中，閘極結構118為虛擬閘極結構(步驟206)，且可藉由「後閘極製程」及替換性閘極製程，與替換性閘極結構做替換。於其他實施方式中，閘極結構118可為主動閘極，且可形成於「先閘極製程」之中，且不可被替換。
閘極介電質(未示於圖)可用圖案化的方法形成閘極介電質112。閘極介電層可形成於半導體鰭片110’及淺溝槽隔離區域106之上方，而形成之方法可為，熱氧化法、化學氣相沉積製程、旋塗式玻璃材質製程、離子濺鍍法或於此領域中具有通常知識者所習之其他方法。於一些實施方式中，閘極介電層之材質可包含一或多個合適的介電材料，例如：矽氧化物、矽氮化物、低介電常數介電質像是碳摻雜氧化物、超低介電常數介電質像是多孔碳摻雜二氧化矽、聚合物像是聚酰亞胺、或其他類似的材料或其組合。於其他實施方式中，閘極介電層可包含具有高介電常數之介電材料，例 如：介電常數大於3.9之材料。介電材料之材質可包含矽氮化物(silicon nitrides)、氮氧化物(oxynitrides)、金屬氧化物像是二氧化鉿(HfO2)、鉿鋯氧化物(HfZrOx)、鉿矽氧化物(HfSiOx)、鉿鈦氧化物(HfTiOx)、鉿鋁氧化物(HfAlOx)、或其他類似的材料、或其組合或其多層之組合。
於閘極介電層形成之後，閘極電極114係形成於閘極介電層之上方。閘極電極114之形成方式包含，首先，於半導體鰭片110’與淺溝槽隔離區域106之上方形成閘極電極層(未示於圖)。接著，圖案化閘極電極層與閘極介電層，以形成閘極電極114及閘極介電質112。於一些實施方式中，閘極電極層之材質為導電材料，其可為多晶矽(polycrystalline-silicon；poly-Si)、多晶矽鍺(poly-crystalline silicon-germanium)、金屬氮化物(metallic nitrides)、金屬矽化物(metallic silicides)、金屬氧化物(metallic oxides)或金屬之其中一者。於一實施方式中，閘極電極層包含金屬材料，例如：氮化鈦(TiN)、氮化鉭(TaN)、碳化鉭(TaC)、鈷(Co)、釕(Ru)、鋁(Al)或其組合或其組合之多層。閘極電極層之沉積方法可包含，但不限於，化學氣相沉積製程、物理氣相沉積製程、離子濺鍍沉積製程或於此領域中具有通常知識者所習之可沉積導電材料之方法。閘極電極層之頂面可具有非平坦之頂面，且於沉積之後的平坦化方法可為化學機械研磨，但不以此為限。遮罩層(未示於圖)(例如：光阻劑、硬遮罩層、或其組合、或其組合之多層)可利用圖案化之方式形成於閘極電極層之 上方。接著，利用可接受之微影製程及蝕刻製程可將此圖案化之遮罩層轉移為閘極電極層之材料，以形成閘極電極56及閘極介電質54。
閘極間隙壁116可形成於閘極電極114之相對側。閘極間隙壁116通常形成之方法為毯覆式沉積製程以沉積間隙壁層(未示於圖)，並間隙壁層覆蓋於半導體鰭片110’、閘極電極114、閘極介電質112及淺溝槽隔離區域106之上方。於一實施方式中，閘極間隙壁116可包含間隙壁襯墊層(未示於圖)，此間隙壁襯墊層之材質可包含，但不限於，氮化矽(SiN)、碳化矽(SiC)、矽鍺(SiGe)、氮氧化物(oxynitride)、氧化物(oxide)或其組合。間隙壁層之材質可包含，但不限於，氮化矽(SiN)、氮氧化物(oxynitride)、碳化矽(SiC)、氮氧化矽(SiON)、氧化物(oxide)或其組合。間隙壁層形成之方法可包含，但不限於，化學氣相沉積製程、電漿輔助化學氣相沉積製程或離子濺鍍沉積製程。接著，圖案化閘極間隙壁116。此圖案化之形成方法可包含，但不限於，藉由非等向蝕刻製程，從閘極電極114、複數鰭片110’與淺溝槽隔離區域106之水平表面移除間隙壁層。
參照第5圖，未被閘極結構118覆蓋(步驟208)之半導體鰭片110’的部分結構藉由蝕刻的方式形成凹陷。半導體鰭片110’之凹陷的複數總頂面可實質上等於或低於淺溝槽隔離區域106的頂面之水平。因此，凹陷120係形成於淺溝槽隔離區域106之間。凹陷120位於閘極結構118之相對側。
第6a圖與6b圖繪示磊晶區域122的形成方法(步驟210)，其中第6b圖繪示為，沿著包含如第6a圖所示線段A-A之垂直平面之單磊晶區域122的剖面圖。於一些實施方式中，磊晶區域122為應變材料堆疊122。此應變材料堆疊122之晶格常數係不同於半導體鰭片110之晶格常數。因此，於閘極結構118下的鰭式場效電晶體之通道區域可產生應變或應力，以提高元件之載子遷移率。
於一些實施方式中，於應變材料堆疊122形成之前，藉由預清洗製程以清洗凹陷120，此預清洗製程所用之流體包含，但不限於，氫氟基氣體或矽鈷鎳基氣體。於一些實施方式中，應變材料堆疊122包含，但不限於，矽(Si)、鍺(Ge)、矽鍺(SiGe)、碳化矽(SiC)、磷化矽(SiP)、錫鍺(GeSn)、矽錫鍺(SiGeSn)、p型摻雜物(P-type dopant)、n型摻雜物(N-type dopant)、或三-五族元素之半導體材料、或其組合。於一些實施方式中，應變材料堆疊122包含複數磊晶層122A、122B、122C、以及122D。於p型鰭式場效電晶體之實施方式中，第一磊晶層122A為硼摻雜矽鍺(boron-doped SiGe；SiGeB)、第二磊晶層122B為硼摻雜矽鍺、第四磊晶層122D為硼摻雜矽鍺。於一些實施方式中，每一硼摻雜矽鍺層(122A、122B以及122D)具有不同的矽濃度、鍺濃度及/或硼濃度。於一些實施方式中，第三層122C為錫摻雜矽鍺(tin-doped SiGe；SiGeSn)、錫鍺、或硼摻雜錫鍺(B-doped GeSn；GeSnB)。磊晶層122A、122B、122C以及122D輔助低電阻金屬矽化物和/或金屬鍺化合物 形成於應變材料堆疊122上。於n型鰭式場效電晶體之實施方式中，硼摻雜錫鍺層可使用磷化矽層替換，且可用n型摻雜物以摻雜磊晶層122。
於先進製程中，接點之臨界維度(critical dimension；CD)持續下降。因此，於汲極/閘極區域與接觸栓塞(或接觸)之間，金屬矽化物被用以作為低電阻連接。下列方程式(1)所示為諸如金屬矽化物或金屬鍺之導體材料之電阻之間的關係式。此導體材料係形成於半導電材料旁，且係為影響電阻率的因素。
於方程式(1)中，pco係依據金屬與半導體材料所得之常數、φ B 係蕭基能位障高(Schottky barrier height；SBH)、m*係半導體材料之有效質量以及N係半導體材料的摻雜濃度。
特定接觸電阻pc的降低可包含數個方法。其中的一個方法為降低蕭基能位障高φ B 。而蕭基能位障高φ B 的降低方法可包含，能階對位的校準、金屬矽化物與半導體材料之間介面缺陷的減少以及摻雜隔離層的設計。另一特定接觸電阻pc的降低方法為增加摻雜濃度N。摻雜濃度的增加方法可包含，於應變材料堆疊122中提供更多摻雜物，而此些摻雜物係源自於磊晶製程中的原位摻雜以及源自於植入的方法。
應變材料堆疊122可依序地及選擇性地成長以 填充凹陷120。應變材料堆疊122之形成方式可包含，低壓化學氣相沉積製程、液相磊晶製程、分子束磊晶製程、氣相磊晶製程或其組合。於一些實施方式中，用以形成應變材料堆疊122所使用之反應氣體包含矽甲烷(SiH4)、氫矽化物(SiH2)、氯氣(Cl2)、氯化氫(HCl)、鍺烷(GeH4)、乙鍺烷(Ge2H6)、乙硼烷(B2H6)、氫氣(H2)或其組合。
第一磊晶層122A係形成於凹陷120之表面。於一實施方式中，第一磊晶層122A之材質為硼摻雜矽鍺。於一些實施方式中，第一磊晶層122A之鍺濃度(原子百分濃度)範圍為約15%到約30%。於一些實施方式中，第一磊晶層122的厚度範圍為約10奈米到約30奈米。
第二磊晶層122B係形成於第一磊晶層122A之上方。於一實施方式中，第二磊晶層122B之材質為硼摻雜矽鍺。於一些實施方式中，於第一磊晶層122A至第三磊晶層122C之方向，第二磊晶層122B於其底部至其頂部之鍺濃度為梯度增加。於鍺濃度為梯度增加之一些實施方式中，第二磊晶層122B於其底部至其頂部之鍺濃度，為第一磊晶層122A之鍺濃度增加至接近第三磊晶層122C之鍺濃度。此外，於鍺濃度為梯度增加之一些實施方式中，第二磊晶層122B於其底部至其頂部鍺濃度之增加濃度範圍，為其底部鍺濃度約30%到約80%。於一些實施方式中，第二磊晶層122B的厚度範圍為約10奈米到約30奈米。
第三磊晶層122C係形成於第二磊晶層122B之上方。於一些實施方式中，第三磊晶層122C之材質為錫摻 雜矽鍺(SiGeSn)、錫鍺(GeSn)或硼摻雜矽鍺(GeSnB)。第三磊晶層之係配置做為能階對位層，此能階對位層係對於位於其下方之第二磊晶層122B，與對於之後位於其上之金屬矽化物層142(如第11a至11c圖所示)。藉由此些層之能階對位，第三磊晶層122C係降低了位於金屬矽化物層142與應變材料堆疊122之間介面的蕭基能位障高。亦可摻雜硼於第三磊晶層122C，以提供摻雜隔離層的來源。依據第三磊晶層122C之摻雜物輪廓，第三磊晶層122C可為應變層或弛豫層(relaxed layer)。於一些實施方式中，第三磊晶層122C的鍺濃度範圍為約50%到約95%。於一些實施方式中，第三磊晶層122C的錫濃度範圍為約0.1%到約9%。於一些實施方式中，第三磊晶層122C的厚度範圍為約1奈米到約10奈米。
第四磊晶層122D係形成於第三磊晶層122C之上方。於一些實施方式中，第四磊晶層122D之材質為硼摻雜矽鍺。第四磊晶層122D的配置，係為了減少或避免因為第三磊晶層122C與金屬矽化物層142之間之化學勢差異所產生的電鍍腐蝕(galvanic corrosion)(如第11a至11c圖所示)。亦可摻雜硼於第四磊晶層122D，以提供摻雜隔離層的來源。於一些實施方式中，第四磊晶層122D的鍺濃度範圍約15%到約50%。於一些實施方式中，第四磊晶層122D的厚度範圍為約2奈米到約10奈米。
參照第7a圖、第7b圖及與第7c圖，於應變材料堆疊122上進行共同佈植製程124(步驟212)。第7b圖繪示 為，沿著包含如第7a圖所示線段A-A之垂直平面之半導體鰭片110’的剖示圖。而第7c圖繪示為，沿著如第6a圖所示線段A-A之單應變材料堆疊122的剖示圖。共同佈植製程124係增加了能階對位校準與摻雜隔離層的摻雜物濃度。於一些實施方式中，應變材料堆疊122磊晶形成之後，摻雜物濃度不夠高，以致於不能確保有足夠之能階對位校準及/或摻雜隔離層。亦即，於無包含共同佈植製程124的情況下，接觸結構之特定接觸電阻會有不利的影響。
於一些實施方式中，例如電漿摻雜製程的共同佈植製程124可摻雜硼、銦、錫、銻、類似的摻雜物或其組合。此些額外的摻雜物會產生更多的類施體態與類受體態，因此，可於應變材料堆疊122與後續所形成之金屬矽化物層142之間有效地降低位的蕭基能位障高(如第11a~11c圖所示)。於一些實施方式中，共同佈植製程124為低能量植入製程，此製程進行之能量範圍為約1電子伏特(kiloelectron volt；keV)到約10電子伏特。於一實施方式中，共同佈植製程124提供之植入劑量範圍約1E13atoms/cm2到5E15atoms/cm2。於共同佈植製程之後，第三磊晶層122C與第四磊晶層122D之兩者或其中一者的硼濃度範圍為約1E20atoms/cm2到約8E20atoms/cm2。
第8圖繪示為蝕刻擋止層125(etch stop layer；ESL)與層間介電(inter-layer dielectric；ILD)層126形成之後的結構透視圖。蝕刻擋止層125形成於閘極間隙壁116、閘極電極114(如第8圖所示之替換性閘極)、應變材料 堆疊122(可為源極區域/汲極區域122)、鰭片110’、與淺溝槽隔離區域106之上方。蝕刻擋止層125保形性地沉積於基材102之元件上方。於一實施方式中，蝕刻擋止層125之材質可包含，但不限於，氮化矽(SiN)、氮化碳矽(SiCN)、氮氧化矽(SiON)或其組合。蝕刻擋止層之形成方法可包含，但不限於，原子層沉積製程、分子層沉積製程、爐管製程、化學氣相沉積製程、電漿輔助化學氣相沉積製程或其組合。於一些實施方式中，於蝕刻擋止層125形成之前，可形成緩衝氧化物(未示於圖)。
於蝕刻擋止層125形成之後，層間介電層126可形成於蝕刻擋止層125之上方。層間介電層126可保形性地沉積於蝕刻擋止層125之上方。於一實施方式中，層間介電層126的材質可包含，但不限於，二氧化矽(SiO2)、氮氧化矽(SiON)或其組合。層間介電層126之形成方式可包含，但不限於，化學氣相沉積製程、分子層沉積製程、化學氣相沉積製程、次大氣壓化學氣相沉積製程、流動性化學氣相沉積製程、高濃度電漿製程、旋塗式介電製程或其組合。
可藉由化學機械研磨製程移除層間介電層126之部分結構。於其他實施方式中，亦可使用其他平坦化製程移來除層間介電層126之部分結構，例如：蝕刻製程。於替換性閘極之實施方式中，可藉由任何適當的蝕刻製程，以移除虛擬閘極電極114與虛擬閘極介電質112(步驟216)。
於虛擬閘極電極114與虛擬閘極介電質112被移除之後，替換性閘極介電質128與替換性閘極結構130可 形成於虛擬閘極電極114與虛擬閘極介電質112被移除前之位置(步驟218)。替換性閘極介電質128與替換性閘極結構130相似於前文所述之虛擬閘極電極114與虛擬閘極介電質112，因此於此處不重述其相關製程。
接著，移除層間介電層126之部分結構126A(步驟226)以形成接觸開口。此些接觸開口透過層間介電層126，並形成於閘極結構130之相對側。接觸開口134之其中一者繪示於第9a圖中。第9a、10a、11a圖、與第12圖為沿著包含如第8圖所示線段C-C之垂直平面的剖面圖。第9a圖與第9c圖為分別地沿著包含如第7a圖與第7c圖所示相似平面的剖面圖。第10圖與第11圖為分別地沿著包含如第9a圖、第9b圖、與第9c圖所示相似平面的剖面圖。
參照第9a圖、第9b圖、與第9c圖，接觸開口134位於層間介電層126中。源極與閘極區域122’(即應變材料堆疊122)包含彼此之間間隔一段距離的複數鏟形磊晶區域。源極與閘極區域122’具有小平面123。此小平面123包含朝上之小平面與朝下之小平面。小平面123可位於源極與閘極區域122’之座標平面<111>上。如第9a圖繪示，若於實施方式中出現緩衝氧化層，則可從接觸開口134移除緩衝氧化層與蝕刻擋止層125。此緩衝氧化層與蝕刻擋止層125可由蝕刻的方式移除，因此，暴露出小平面123與源極與閘極區域122’。接著，於曝露的小平面123上進行預清洗製程。此預清潔製程的進行可包含，但不限於，氫氟基氣體(HF-based gas)、矽鈷鎳基氣體(SiCoNi-based gas)。預 清洗製程可移除自然矽氧化物，而此自然矽氧化物之形成，係由於源極與閘極區域122’之暴露表面的自然氧化物。
於蝕刻擋止層125被移除之後，於源極與閘極區域122’(即應變材料堆疊122)上進行非晶化前植入製程136(pre-amorphization implant；PAI)(步驟222)。此非晶化前植入製程136植入於源極與閘極區域122’，以破壞源極與閘極區域122’，並形成非晶化區域(未示於圖)。於部分實施方中，非晶化區域可橫向延伸至閘極間隙壁116下。依據一些實施方式，非晶化前植入製程136可使用矽或鍺來植入源極與閘極區域122’。非晶化區域之深度可由非晶化前植入製程136之製程參數所控制，此植入參數例如：植入能量、植入型式及植入劑量。非晶化前植入製程136之進行可為鍺非晶化前植入製程，但不限於此。此製程植入之能量範圍為約5千電子伏特到約35千電子伏特，而植入之劑量範圍為約5E14atoms/cm2到約1E15atoms/cm2。
第10a圖、第10b圖、與第10c圖繪示為，金屬層140於源極與閘極區域122’(即應變材料堆疊122)之小平面123上的形成方式(步驟224)。此金屬層140之材質可包含，但不限於，鎳、鈦、鈷或其組合。金屬層140之形成方式可包含保形性的沉積方法，但不限於，原子層沉積製程或物理氣相沉積製程。此些形成方式可使得金屬層140形成於源極與閘極區域122’之小平面123的朝上表面及朝下表面。於一實施方式中，金屬層140的厚度範圍約20埃(angstrom；Å)到約30埃。
第11a圖、第11b圖、與第11c圖繪示為，金屬層140以及源極與閘極區域122’(即應變材料堆疊122)的退火製程(步驟226)，以於源極與閘極區域122’上形成金屬矽化物層142。於一些實施方式中，此退火製程為微波退火(microwave anneal；MWA)製程。微波退火製程可導致金屬層140和源極與閘極區域122’之間產生反應，以形成金屬矽化物層142。於一實施方式中，金屬矽化物層142大致上完全消耗源極與閘極區域122’之第四磊晶層122D。於一些實施方式中，金屬層140之部分結構被消耗，則未反應的金屬層140之部分結構可遺留於金屬矽化物層142之上方。接著，可藉由蝕刻製程或清洗製程移除此未反應的金屬層140。金屬矽化物層142之材質可包含，但不限於，鎳矽(NiSi)、鈦矽化物(TiSix)或其組合。
於一些實施方式中，退火製程為多段式微波退火(multi-stag microwave anneal；multi-stag MWA)製程。舉例而言，微波退火製程可包含第一階段之微波退火製程與第二階段之微波退火製程。第一階段之微波退火製程的執行溫度範圍約350℃到約550℃，而其持續時間範圍約50秒到約100秒。第二階段之微波退火製程執行的溫度範圍約500℃到約600℃，而其持續時間範圍約50秒到約180秒。於一些實施方式中，每一階段之溫度不可超過600℃，以避免閘極結構130之擴散而導致其可包含金屬(例如：鋁)，並以避免摻雜物失去活性。
對於需避免高溫處理之先進元件的製造過程 中，微波退火製程可用於退火製程。此微波退火製程可被調節，以局部增加特定結構、層、或區域的溫度，例如：位於金屬層140和半導體之源極與閘極區域122’(即應變材料堆疊122)之間介面的鄰近結構、層或區域，其溫度高於基材/晶圓102或其他周圍之結構、層或區域。舉例而言，當元件之基材/晶圓102以及其他區域的溫度不超過600℃時，位於金屬層140和半導體的源極與閘極區域122’之間介面之溫度可升溫至約1000℃到約1100℃。此外，對於元件結構之其他部分(例如：閘極結構)來說，微波退火製程可去除其大部分的群集缺陷/介面缺陷。因此，可降低藉由無金屬擴散損失之缺陷所造成的蕭基能位障高。於2014年4月10日申請，名為「缺陷復原之微波退火」之美國專利申請編號14/250217，更進一步揭露微波退火之製程及其設備相關細節，而於本文中亦參考及引用此專利之內容。
參照第12圖，將導電材料填充於遺留之接觸開口134(步驟228)。於填充導電材料完成之後，進行化學機械研磨以移除導電材料之多餘部分結構，而接觸開口134中遺留之導電材料則形成接觸栓塞144。於一些實施方式中，接觸栓塞144之材質為鎢(tungsten；W)。於另一實施方式中，接觸栓塞144之材質可包其他金屬或金屬合金像是鋁或銅，但不限於此。
於一實施方式中，n型鰭式場效電晶體可包含鎢接觸栓塞144、鎳矽金屬矽化物層142以及磷化矽源極與閘極區域122’，其蕭基能位障高約為0.75電子伏特。於另一 實施方式中，n型鰭式場效電晶體可包含鎢接觸栓塞144、矽化鈦金屬矽化物層142以及磷化矽源極與閘極區域122’，其蕭基能位障高約為0.55電子伏特。因此，應用本文之揭露，具有矽化鈦金屬矽化物層142之n型鰭式場效電晶體，係有較低之蕭基能位障高。
於一實施方式中，p型鰭式場效電晶體可包含鎢接觸栓塞144、鎳矽金屬矽化物層142以及矽鍺源極與閘極區域122’，其蕭基能位障高約為0.12電子伏特。於另一實施方式中，p型鰭式場效電晶體包含鎢接觸栓塞144、矽化鈦金屬矽化物層142以及磷化矽源極與閘極區域122’，其蕭基能位障高約為0.32電子伏特。因此應用本文之揭露，具有鎳矽金屬矽化物層142之p型鰭式場效電晶體，係有較低的蕭基能位障高。因此，於一些實施方式中，可同時應用n型以及p型鰭式場效電晶體(例如：互補式金屬氧化物半導體)，其中n型鰭式場效電晶體可使用矽鈦化物之金屬矽化物層，而p型鰭式場效電晶體可使用鎳矽金屬矽化物層，係對於兩種通道形式之鰭式場效電晶體提供最低的接觸電阻。
前文所揭露之實施方式，係降低了源極與閘極區域122’(即應變材料堆疊122)之接觸結構的接觸電阻(reduced contact resistance；Rcsd)。由於蕭基能位障高之降低與摻雜濃度之增加，係降低了接觸電阻(見前述之公式(1))。於具有高應變與高摻雜濃度之部分源極與閘極區域122’中，蕭基能位障高之降低與摻雜濃度之增加的方法可包含，摻雜隔離層的摻雜物設計、能階對位校準以及選擇 性局部高溫加熱以去除缺陷。
前述多個實施方式的特徵使本技術領域中具有通常知識者可更佳的理解本案之各個態樣。在此技術領域中具有通常知識者應瞭解，為了達到相同之目的及/或本案之實施方式之相同優點，其可輕易利用本案為基礎，進一步設計或修飾其他製程及結構。在本技術領域中具有通常知識者亦應瞭解，該等均等之結構並未背離本案之精神及範圍，而在不背離本案之精神及範圍下，其可在此進行各種改變、取代及修正。
100‧‧‧晶圓
102‧‧‧基材
106‧‧‧隔離區域
110‧‧‧條形半導體
116‧‧‧閘極間隙壁
122‧‧‧應變材料堆疊
125‧‧‧蝕刻擋止層
126‧‧‧層間介電層
126A‧‧‧部分結構
128‧‧‧替換性閘極介電質
130‧‧‧替換性閘極結構
C-C‧‧‧線段

Claims (10)

  1. 一種半導體元件的製造方法，包含：於一基材上方形成一閘極結構；於該基材中形成鄰近該閘極結構之一凹陷；於該凹陷中磊晶形成一應變材料堆疊，該應變材料堆疊包含至少三層狀物，每一該些至少三層狀物包含一第一摻雜物，每一該至少三層狀物具有一摻雜濃度；增加該至少三層狀物中至少任一者的該摻雜濃度，該增加包含使用複數第二摻雜物共同佈植該應變材料堆疊的該至少三層狀物的該至少任一者，該些第二摻雜物包含硼、鍺、銦、錫或其組合；於該應變材料堆疊上形成一金屬層；以及對該金屬層與該應變材料堆疊退火以形成一金屬矽化物層。
  2. 如請求項1所述之半導體元件的製造方法，更包含：於該應變材料堆疊上形成該金屬層之前，於該應變材料堆疊上進行一非晶化前值入製程，該非晶化前植入製程包含於該應變材料堆疊中植入鍺摻雜物。
  3. 如請求項2所述之半導體元件的製造方法，其中於該應變材料堆疊上進行該非晶化前植入製程，係執行於共同佈植該應變材料堆疊與該些第二摻雜物之後。
  4. 如請求項1所述之半導體元件的製造方法，其中對該金屬層與該應變材料堆疊退火更包含：進行一多段式微波退火(multi-stage microwave anneal；MWA)製程於該金屬層與該應變材料堆疊上。
  5. 如請求項1所述之半導體元件的製造方法，其中於該凹陷中磊晶形成之該應變材料堆疊更包含：磊晶形成一第一硼摻雜矽鍺(boron-doped silicon-germanium；SiGeB)層；磊晶形成一第二硼摻雜矽鍺層於該第一硼摻雜矽鍺層上，其中該第二硼摻雜矽鍺層之鍺濃度高於該第一硼摻雜矽鍺層之鍺濃度；磊晶形成一錫摻雜鍺(tin-doped germanium；GeSn layer)層於該第二硼摻雜矽鍺層上；以及磊晶形成一第三硼摻雜矽鍺層於該錫摻雜鍺層上。
  6. 如請求項5所述之半導體元件的製造方法，更包含：於該應變材料堆疊上形成該金屬層之前，於該應變材料堆疊與該基材上方形成一層間介電(inter-layer dielectric；ILD)層；形成通過該層間介電層之一開口以暴露該應變材料堆疊之部分結構，該金屬層位於該層間介電層之該開口中；以及 於該層間介電層與該金屬矽化物層之間形成一導電接點，該導電接點物理性接觸該金屬矽化物層。
  7. 如請求項5所述之半導體元件的製造方法，其中對該金屬層與該應變材料堆疊退火以形成該金屬矽化物層實質上消耗於該應變材料堆疊中全部之該第三硼摻雜矽鍺層。
  8. 一種鰭式場效電晶體(Fin Field-Effect Transistor；FinFET)之形成方法，包含：形成複數個鰭片，該些鰭片從一基材延伸；於該些鰭片上方形成一虛擬閘極結構；於該些鰭片中形成鄰近該虛擬閘極結構之複數個凹陷；於該些鰭片中之該些凹陷中磊晶形成複數個應變材料堆疊，每一該些應變材料堆疊包含一磊晶成長錫鍺(germanium-tin；GeSn)層與複數磊晶成長硼摻雜矽鍺(boron-doped silicon-geranium；SiGeB)層，該磊晶成長錫鍺層位於該些磊晶成長硼摻雜矽鍺層之中；將硼、銦、錫、或其組合植入該些應變材料堆疊；於該些應變材料堆疊上形成一金屬層；進行一微波退火(multi-stage microwave anneal；MWA)製程於該金屬層與該些應變材料堆疊上，以於該些應變材料堆疊上形成複數個金屬矽化物層；以及於該些應變材料堆疊之間形成一金屬接點，該金屬接 點連接該些金屬矽化物層。
  9. 如請求項8所述之鰭式場效電晶體之形成方法，其中於該微波退火製程期間，該基材之一溫度不超過約600℃。
  10. 一半導體元件，包含：一鰭片，該鰭片從一基材延伸出；一閘極結構，位於該鰭片之一頂面與複數個側壁上；一應變材料堆疊，位於該鰭片上並鄰近該閘極結構，該應變材料堆疊包含：一第一硼摻雜矽鍺(boron-doped silicon-geranium；SiGeB)層；一第二硼摻雜矽鍺層，位於該第一硼摻雜矽鍺層上，該第二硼摻雜矽鍺層之鍺濃度高於第一硼摻雜矽鍺層之鍺濃度；以及一硼摻雜鍺錫(B-doped germanium-tin；GeSnB)層，位於該第二硼摻雜矽鍺層上；一金屬矽化物層，位於該硼摻雜鍺錫層上；以及一金屬接點，位於該金屬矽化物層上。
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