TWI567944B - 半導體裝置與其製造方法 - Google Patents

半導體裝置與其製造方法 Download PDF

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TWI567944B
TWI567944B TW104128663A TW104128663A TWI567944B TW I567944 B TWI567944 B TW I567944B TW 104128663 A TW104128663 A TW 104128663A TW 104128663 A TW104128663 A TW 104128663A TW I567944 B TWI567944 B TW I567944B
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gate
fin
substrate
insulating structure
semiconductor device
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TW104128663A
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TW201635488A (zh
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張哲誠
林志翰
陳威廷
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台灣積體電路製造股份有限公司
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
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Description

半導體裝置與其製造方法
本揭露是有關於一種半導體裝置。
隨著半導體工業演進至奈米工藝技術，以得到較高的裝置密度、高效能和低成本，半導體裝置製造和設計均進步至三維的設計，例如鰭式場效電晶體(fin field effect transistor，簡稱FinFET)。鰭式場效電晶體包含自基底往其平面法線之方向延伸的鰭。鰭式場效電晶體的通道則是形成在鰭。柵極則置於(例如包覆)鰭上。鰭式場效電晶體可降低短通道效應。
本揭露之一態樣提供一種半導體裝置，包含基板、第一閘極、第二閘極與絕緣結構。基板包含第一鰭與第二鰭。第一閘極置於第一鰭上。第二閘極置於第二鰭上。第一閘極與第二閘極之間形成間隙，且間隙往基板漸寬。絕緣結構置於間隙中。絕緣結構具有相對之上表面與下表面，下 表面面向基板，且上表面面向第一閘極之邊緣往上表面內彎。
在多個實施方式中，第一閘極之數量為複數個，且半導體裝置更包含介電層，置於兩相鄰之第一閘極之間。
在多個實施方式中，絕緣結構之下表面與第一閘極面向絕緣結構之側壁形成第一角度，且第一角度小於90度。
在多個實施方式中，第一閘極具有圓角，面向絕緣結構與基板。
本揭露之一態樣提供一種半導體裝置，包含基板、第一閘極、第二閘極與絕緣結構。基板包含第一鰭與第二鰭。第一閘極置於第一鰭上。第二閘極置於第二鰭上，且與第一閘極互相分離。絕緣結構置於第一閘極與第二閘極之間。絕緣結構具有相對之上表面與下表面，絕緣結構之下表面面向基板。絕緣結構之下表面的面積大於絕緣結構之上表面的面積，且絕緣結構之上表面面向第一閘極之邊緣往上表面內彎。
在多個實施方式中，第一閘極具有面向基板之下表面。第一閘極之下表面與第一閘極面向第二閘極之側壁之間形成第一角度，且第一角度大於90度。
在多個實施方式中，絕緣結構具有頂部與底部。底部置於頂部與基板之間，頂部之寬度短於底部之寬度。
本揭露之再一態樣提供一種半導體裝置的製造方法，包含提供基板，包含第一鰭與第二鰭。形成假性層於基板上以覆蓋第一鰭與第二鰭。圖案化假性層，以於第一鰭與第二鰭之間形成假性結構，且暴露出第一鰭與第二鰭。分別形成第一閘極與第二閘極於假性結構的相對側。第一閘極覆蓋第一鰭，且第二閘極覆蓋第二鰭。移除假性結構，以在第一閘極與第二閘極之間形成間隙。形成絕緣結構於間隙中。
在多個實施方式中，第一閘極之數量為複數個，且該方法更包含形成介電層於兩相鄰之第一閘極之間。
在多個實施方式中，方法更包含形成遮罩於假性層上。圖案化遮罩以於第一鰭與第二鰭之間形成圖案化遮罩。假性層係藉由圖案化遮罩而被圖案化。
在上述實施方式中，第一閘極可容易地被填入於第一凹槽中，且並不會於第一閘極與基板之間形成一空間。同樣的，第二閘極可被容易地填入於第二凹槽中，且並不會於第二閘極與基板之間形成一空間。因此，第一閘極與第二閘極的電性性能可被改善。
110‧‧‧基板
111、136t、160t、165t、170t‧‧‧上表面
112‧‧‧第一鰭
114‧‧‧第二鰭
116‧‧‧絕緣結構
120‧‧‧閘極絕緣層
130‧‧‧假性層
132‧‧‧第一凹槽
134‧‧‧第二凹槽
136‧‧‧假性結構
136b、160b、165b、170b‧‧‧下表面
137a、137b、162、167、172a、172b‧‧‧邊緣
138a、138b、164、169‧‧‧側壁
142‧‧‧第一介電層
144‧‧‧第二介電層
150‧‧‧遮罩
160‧‧‧第一閘極
163、168‧‧‧角
165‧‧‧第二閘極
170‧‧‧絕緣結構
174‧‧‧頂部
176‧‧‧底部
B-B‧‧‧線段
D‧‧‧距離
G‧‧‧間隙
Hb‧‧‧高度
W、Wt、Wb、Wm‧‧‧寬度
φ1、φ2、θ1、θ2、θ3、θ4、θ3b、θ3t、θ4b、θ4t‧‧‧夾角
從以下結合所附圖式所做的詳細描述，可對本揭露之態樣有更佳的了解。需注意的是，根據業界實務的標準做法，各種特徵不是按比例繪製。實際上，為了清楚討論起見，各種特徵的尺寸可任意放大或縮小。
第1A圖至第6A圖為本揭露一些實施方式之製造半導體結構的方法於不同階段的上視圖。
第1B圖至第6B圖為分別沿著第1A圖至第6A圖之線段B-B的剖面圖。
第7圖為本揭露一些實施方式之製造半導體結構的剖面圖。
第8圖為本揭露一些實施方式之製造半導體結構的剖面圖。
第9圖為本揭露一些實施方式之製造半導體結構的剖面圖。
以下的揭露提供了許多不同實施方式或範例，以實施所提供之標的之不同特徵。以下所描述之構件與安排的特定範例係用以簡化本揭露。當然這些僅為範例，並非用以做為限制。舉例而言，於描述中，第一特徵形成於第二特徵上方或上，可能包含第一特徵與第二特徵以直接接觸的方式形成的實施方式，亦可能包含額外特徵可能形成在第一特徵與第二特徵之間的實施方式，如此第一特徵與第二特徵可能不會直接接觸。此外，本揭露可能會在各範例中重複參考數字及/或文字。這樣的重複係基於簡化與清楚之目的，以其本身而言並非用以指定所討論之各實施方式及/或配置之間的關係。
另外，在此說明中可能會使用空間相對用語，例如「下方(underlying)」、「下方(below)」、「較低(lower)」、「上方(overlying)」、「較高(upper)」等等，以方便說明如圖式所繪示之一元件或一特徵與另一(另一些)元件或特徵之關係。除了在圖中所繪示之方向外，這些空間相對用詞意欲含括元件在使用或操作中的不同方位。設備可能以不同方式定位(旋轉90度或在其他方位上)，因此可利用同樣的方式來解釋在此所使用之空間相對描述符號。
本揭露之實施方式提供一些形成半導體裝置的改進方法與其結構。這些實施方式將在以下形成鰭式場效電晶體(finFET)內容中被討論，其鰭式場效電晶體係具有單一或複數鰭，且形成於體(bulk)矽基底上。本領域具通常知識者可理解本揭露之實施方式可應用於其他結構。
第1A圖至第6A圖為本揭露一些實施方式之製造半導體結構的方法於不同階段的上視圖，而第1B圖至第6B圖為分別沿著第1A圖至第6A圖之線段B-B的剖面圖。請先參照第1A圖與第1B圖。提供基板110，其包含第一鰭112與第二鰭114，突出於基板110的上表面111。在一些實施方式中，第一鰭112與第二鰭114包含矽。在一些實施方式中，第一鰭112與第二鰭114之寬度W為約10奈米，而相鄰之第一鰭112與第二鰭114之間的距離D為約35奈米，然而本揭露不以此為限。另外，應注意的是，第1A圖與第1B圖之第一鰭112與第二鰭114的數量為例示，並非用以限制本揭露。本領域具通常知識 者，可依實際情況，彈性選擇合適之第一鰭112與第二鰭114的數量。
在一些實施方式中，基板110可為半導體材料且可包含習知結構，其例如包含遞變層(graded layer)或隱埋氧化物(buried oxide)。在一些實施方式中，基板110包含體(bulk)矽，其可未摻雜或(如p型、n型或其組合)摻雜。其他適合形成半導體裝置的材料亦可被使用。基板110可替代為其他材料，例如鍺(germanium)、石英(quartz)、藍寶石(sapphire)與玻璃(glass)。或者，基板110可為絕緣體上半導體(semiconductor-on-insulator,SOI)基板之主動層，或者為例如形成於體矽層上之矽-鍺層的多層結構。
第一鰭112與第二鰭114可以，例如，光罩顯影方式圖案化與蝕刻基板110以形成。在一些實施方式中，一光阻材料層(未繪示)置於基板110上。光阻材料層接著被照射(或曝光)成欲定圖案(在此為第一鰭112與第二鰭114)並顯影以去除部分之光阻材料。剩餘之光阻材料保護其下方之材料免於後續製程，例如蝕刻，的破壞。應注意的是，其他的遮罩，例如氧化物或氮化矽遮罩可用於蝕刻製程。
在其他的實施方式中，第一鰭112與第二鰭114可為磊晶成長而成。舉例而言，底下被暴露之材料，例如基板110被暴露的部分，可利用磊晶製程以形成第一鰭112與第二鰭114。可使用光罩以在磊晶成長製程中控制第一鰭112與第二鰭114的形狀。
在第1B圖中，基板110可更包含絕緣結構116。絕緣結構116，其可為環繞第一鰭112與第二鰭114的淺溝槽絕緣(Shallow Trench Isolation,STI)，可利用四乙氧基矽烷(tetra-ethyl-ortho-silicate,TEOS)與氧氣當前導物以化學氣相沉積(Chemical Vapor Deposition,CVD)法形成。在其他實施方式中，絕緣結構116可利用於基板110中佈植離子，例如氧、氮、碳等等，而形成。在其他的實施方式中，絕緣結構116可為絕緣體上半導體(SOI)晶圓之絕緣層。
在第1B圖中，一閘極絕緣層120形成於第一鰭112與第二鰭114上。閘極絕緣層120，其避免電子空乏，可包含，例如，高介電係數(high-k)材料，如金屬氧化物、金屬氮化物、金屬矽化物、過渡金屬氧化物、過渡金屬氮化物、過渡金屬矽化物、金屬之氮氧化物、金屬鋁化物、矽化鋯(zirconium silicate)、鋁化鋯(zirconium aluminate)、或其組合。一些實施方式中可包含二氧化鉿(hafnium oxide,HfO2)、矽氧鉿化合物(hafnium silicon oxide,HfSiO)、氮矽氧鉿化合物(hafnium silicon oxynitride,HfSiON)、氧鉭鉿化合物(hafnium tantalum oxide,HfTaO)、氧鈦鉿化合物(hafnium titanium oxide,HfTiO)、氧鋯鉿化合物(hafnium zirconium oxide,HfZrO)、氧化鑭(lanthanum oxide,LaO)、氧化鋯(zirconium oxide,ZrO)、氧化鈦(titanium oxide,TiO)、氧化鉭(tantalum oxide,Ta2O5)、氧化釔(yttrium oxide,Y2O3)、鈦酸鍶(strontium titanium oxide,SrTiO3,STO)、鈦酸鋇(barium titanium oxide,BaTiO3,BTO)、氧 鍶鋇化合物(barium zirconium oxide,BaZrO)、氧鑭鉿化合物(hafnium lanthanum oxide,HfLaO)、氧矽鑭化合物(lanthanum silicon oxide,LaSiO)、氧矽鋁化合物(aluminum silicon oxide,AlSiO)、氧化鋁(aluminum oxide,Al2O3)、氮化矽(silicon nitride,Si3N4)、氮氧化矽(oxynitrides,SiON)或其組合。閘極絕緣層120可具有多層結構，例如一層氧化矽(即中間層)與另一層高介電係數材料。閘極絕緣層120可具有厚度T，其範圍為約10埃至約30埃。閘極絕緣層120可利用化學氣相沉積(chemical vapor deposition,CVD)法、物理氣相沉積(physical vapor deposition,PVD)法、原子層沉積(atomic layer deposition,ALD)法、熱氧化、臭氧氧化、其他合適的製程或其組合而形成。
在第1A圖與第1B圖中，一假性層130形成於基板110上，以覆蓋閘極絕緣層120、第一鰭112與第二鰭114。換句話說，閘極絕緣層120置於假性層130與基板110之間。在一些實施方式中，假性層130包含半導體材料，例如多晶矽、非晶矽等等。假性層130可為摻雜或非摻雜。舉例而言，在一些實施方式中，假性層130包含利用低壓化學氣相沉積(low-pressure chemical vapor deposition,LPCVD)法沉積之非摻雜多晶矽。多晶矽可利用，舉例而言，原位摻雜多晶矽之熔爐沉積(furnace deposition)以沉積多晶矽。或者，假性層130可包含其他合適的材料。
在一些實施方式中，一或多個介電層可形成於假性層130的相對側。舉例而言，在第1A圖與第1B圖中，第一 介電層142與第二介電層144一併形成於假性層130的相對側。一之第一介電層142置於二之第二介電層144之間，且一之第二介電層144置於一之第一介電層142與假性層130之間。第一介電層142之材質可為氧化物，第二介電層144之材質可為氮化矽，然而本揭露不在此限。第一介電層142與第二介電層144可以一或多層介電層(未繪示)形成於先前形成之結構上。介電層可包含氮化矽、氮氧化物、碳化矽、氮氧化矽、氧化物等等，且可藉由例如化學氣相沉積(chemical vapor deposition,CVD)法、電漿增強化學氣相沉積(plasma enhanced CVD)法、濺鍍或其他習知方法形成。第一介電層142與第二介電層144可包含不同材料，其具有與假性層130不同之蝕刻特性，因此第一介電層142與第二介電層144可用來當成圖案化假性層130之遮罩(於第3A圖與第3B圖描述)。第一介電層142與第二介電層144可接著被圖案化，因此可執行一或多個蝕刻製程以從該結構之水平面上移除部分之第一介電層142與第二介電層144。
接著請參照第2A圖與第2B圖。形成一遮罩150於假性層130、第一介電層142與第二介電層144上，且經圖案化以定義閘極(如第6A圖與第6B圖所示)之間的絕緣區，也就是定義閘極之端部。在一些實施方式中，遮罩150為一光阻遮罩，其利用沉積、曝光與顯影一層光阻材料的方式而形成。遮罩150被圖案化用以於閘極之間形成絕緣區域，其細節將於後續製程中詳細描述。
在一些實施方式中，遮罩150在圖案化前先被修栽(trim)。舉例而言，遮罩150可利用等向性濕式蝕刻，例如於溴化氫/氧氣(HBr/O2)環境中進行電漿製程，而蝕刻以進一步縮小遮罩150的尺寸。
請一併參照第3A圖與第3B圖。為了清楚起見，第3B圖繪示的閘極絕緣層120於第3A圖被省略。被遮罩150所暴露的假性層130(如第2A圖與第2B圖所示)利用回蝕製程或其他合適的製程以移除(或圖案化)以形成假性結構136。舉例而言，假性層130可被選擇性蝕刻以於第二介電層144之間形成第一凹槽132與第二凹槽134。假性結構136置於第一凹槽132與第二凹槽134之間。第一凹槽132暴露一部分置於第一鰭112上之閘極絕緣層120，且第二凹槽134暴露一部分置於第二鰭114上之閘極絕緣層120。被暴露之假性層130可利用濕蝕刻製程，其包含暴露於含氫溶液(如氫氧化銨(ammonium hydroxide))、去離子水與/或其他合適之蝕刻液以移除。
請一併參照第4A圖與第4B圖。為了清楚起見，第4B圖繪示的閘極絕緣層120於第4A圖被省略。第3A圖與第3B圖之遮罩150可以灰化(ashing)、剝離(stripping)或其他合適的方式去除。剩餘部分之假性層130(如第2圖所繪示)於第一凹槽132與第二凹槽134之間形成假性結構136。假性結構136可為一栓狀(plug)結構，其由兩相鄰之第二介電層144、第一凹槽132與第二凹槽134所包圍。假性結構136具有相對之一上表面136t與一下表面136b。下表面136b面向基板110。也就是說，下表面136b毗鄰閘極絕緣層120。在第4A圖中，假性結 構136之上表面136t具有相對二邊緣137a與137b。邊緣137a面向第一凹槽132，且邊緣137b面向第二凹槽134。邊緣137a與137b皆向上表面136t內彎曲。更進一步地，在第4B圖中，下表面136b之面積大於上表面136t之面積。假性結構136具有兩相對之側壁138a與138b。側壁138a面向第一凹槽132，且側壁138b面向第二凹槽134。下表面136b與側壁138a之間形成一夾角φ1，且夾角φ1小於90度，亦即夾角φ1為一銳角。下表面136b與側壁138b之間形成另一夾角φ2，且夾角φ2小於90度，亦即夾角φ2為一銳角。因此，假性結構136往上表面136t漸窄，且往下表面136b漸寬。
此處之「實質上」係用以修飾任何可些微變化的關係，但這種些微變化並不會改變其本質。舉例而言，在此揭露之夾角φ1與φ2除了包含小於90度的態樣外，只要夾角φ1與φ2之結構不變，其可略大於或等於90度。
在一些實施方式中，在移除遮罩150(如第3A圖與第3B圖所繪示)後修栽(trim)假性結構136。舉例而言，利用等向性濕式製程蝕刻假性結構136以更進一步地縮小假性結構136之臨界尺寸(critical dimension)。
在第4A圖與第4B圖中，靠近假性結構136之上表面136t的第一凹槽132的開口尺寸大於靠近假性結構136之下表面136b的第一凹槽132的開口尺寸。同樣的，靠近假性結構136之上表面136t的第二凹槽134的開口尺寸大於靠近假性結構136之下表面136b的第二凹槽134的開口尺寸。如此的構造 提供較大的製程窗口以供填入第一閘極160與第二閘極165(如第5A圖與第5B圖所繪示)，詳見後述。
請一併參照第5A圖與第5B圖。形成第一閘極160以填入第一凹槽132，且形成第二閘極165以填入第二凹槽134。如此一來，第一閘極160覆蓋第一鰭112，且第二閘極165覆蓋第二鰭114。自第3A圖至第5B圖之製程被稱為替代閘極(replacement gate loop)製程。更進一步的，若第2A圖與第2B圖之假性層130的材質為多晶矽，則自第3A圖至第5B圖之製程被稱為替代多晶矽閘極(replacement polysilicon gate loop)製程。在一些實施方式中，第一凹槽132與第二凹槽134可填入一或多層材料。填入製程包含化學氣相沉積(chemical vapor deposition,CVD)法、物理氣相沉積(physical vapor deposition,PVD)法、原子層沉積(atomic layer deposition,ALD)法、高密度電漿化學氣相沉積(high density plasma chemical vapor deposition,HDPCVD)法、金屬有機化學氣相沉積(metal organic chemical vapor deposition,MOCVD)法、遠距電漿化學氣相沉積(remote plasma chemical vapor deposition,RPCVD)法、電漿增強化學氣相沉積(plasma enhanced chemical vapor deposition,PECVD)法、電鍍(plating)法、其他合適的方法與/或其組合。之後，執行一金屬化學機械研磨(metal chemical mechanical planarization,CMP)製程以回蝕與平坦化金屬層以形成第一閘極160與第二閘極165。第一閘極160與第二閘極165可與金屬間連接元件耦合，且可置於閘極絕緣層120上。第一閘極160與第二閘極165 可包含高介電係數材料，氮化鈦(titanium nitride,TiN)、氮化鉭(tantalum nitride,TaN)、碳鉭化合物(tantalum carbon,TaC)、矽鈷化合物(cobalt silicon,CoSi)、矽鋯化合物(zirconium silicon,ZrSi2)、矽鉬化合物(molybdenum silicon,MoSi2)、矽鉭化合物(tantalum silicon,TaSi2)、矽鎳化合物(nickel silicon,NiSi2)、氮化鎢(tungsten nitride,WN)、鋁鈦化合物(titanium aluminum,TiAl)、氮化鋁鈦(titanium aluminum nitride,TiNAl)、鋁、鈦、銀、氮碳鉭化合物(tantalum carbon nitride,TaCN)、氮矽鉭化合物(tantalum silicon nitride,TaSiN)、錳、鋯、釕、鉬、銅、鎢、鈷、鎳、碳鈦化合物(titanium carbon,TiC)、碳鋁鈦化合物(titanium aluminum carbon,TiAlC)、碳鋁鉭化合物(tantalum aluminum carbon,TaAlC)、其他合適的導電材料或其組合。第一閘極160與第二閘極165可利用化學氣相沉積法、物理氣相沉積法、電鍍或其他合適的方法形成，且可接著執行化學機械研磨以平坦化閘極結構。第一閘極160與第二閘極165可具有多層結構且可以多步驟製程形成。
第一閘極160具有相對之一上表面160t與一下表面160b。下表面160b面向基板110。也就是說，下表面160b毗鄰閘極絕緣層120。在第5A圖中，第一閘極160的上表面160t具有面向假性結構136之邊緣162。邊緣162往假性結構136之上表面136t彎曲。更進一步的，在第5B圖中，第一閘極160具有面向假性結構136與第二閘極165之側壁164。側壁164為第一閘極160之一端。下表面160b與側壁164之間形成之夾角θ1 實質大於90度，亦即夾角θ1為鈍角。因此第一閘極160朝其上表面160t漸寬，且朝其下表面160b漸窄。
另外，第二閘極165具有相對之一上表面165t與一下表面165b。下表面165b面向基板110。也就是說，下表面165b毗鄰閘極絕緣層120。在第5A圖中，第二閘極165的上表面165t具有面向假性結構136之邊緣167。邊緣167往假性結構136之上表面136t彎曲。更進一步的，在第5B圖中，第二閘極165具有面向假性結構136與第一閘極160之側壁169。側壁169為第二閘極165之一端。下表面160b與側壁169之間形成之夾角θ2實質大於90度，亦即夾角θ2為鈍角。因此第二閘極165朝其上表面165t漸寬，且朝其下表面165b漸窄。
請一併參照第6A圖與第6B圖。利用回蝕製程或其他合適的製程移除第5A圖與第5B圖之假性結構136。舉例而言，假性結構136可被選擇性蝕刻，以於第一閘極160與第二閘極165之間形成間隙G。間隙G朝著基板110漸寬。假性結構136以濕蝕刻製程移除，其包含暴露至含氫氧溶液(例如氫氧化銨)、去離子水與/或其他合適的蝕刻液。
接著，形成絕緣結構170於間隙G中。舉例而言，一間介電層(inter-layer dielectric,ILD)(未繪示)形成於第一閘極160與第二閘極165上以及間隙G中。在一些實施方式中，間介電層之材質為氧化物，例如矽酸磷玻璃(phospho-silicate glass(PSG))，矽酸硼玻璃(boro-silicate glass(BSG))，硼摻雜矽酸磷玻璃(boron-doped phospho-silicate glass (BPSG))，四乙氧基矽烷(TEOS)等等。接著執行化學研磨平坦化製程回蝕與平坦化間介電層以形成絕緣結構170。
絕緣結構170可為一栓狀結構，其被二相鄰之第二介電層144、第一閘極160與第二閘極165包圍。絕緣結構170具有相對之上表面170t與下表面170b。下表面170b面向基板110。換言之，下表面170b毗鄰閘極絕緣層120。在第6A圖中，絕緣結構170之上表面170t具有兩相對的邊緣172a與172b。邊緣172a面向第一閘極160，且邊緣172b面向第二閘極165。邊緣172a與172b皆往上表面170t中心彎曲。更進一步地，在第6B圖中，下表面170b的面積大於上表面170t的面積。絕緣結構170之下表面170b與第一閘極160之側壁164之間形成之夾角θ3實質小於90度，亦即夾角θ3為銳角。絕緣結構170之下表面170b與第二閘極165之側壁169之間形成之夾角θ4實質小於90度，亦即夾角θ4為銳角。因此，絕緣結構170往上表面170t漸窄，且往下表面170b漸寬。
在第6B圖中，第一閘極160與第一鰭112形成一鰭場效電晶體(fin field effect transistor,finFET)，且第二閘極165與第二鰭114形成另一鰭場效電晶體。第一閘極160與第二閘極165被絕緣結構170所隔離。上述之結構與製造方法可改善替代閘極製程之閘極性能。如此的結構提供閘極電極端線(在此亦即第一閘極160之側壁164)與閘極電極端線(在此亦即第二閘極165之側壁169)之間較大的距離，以增加製程窗口與減少漏電流。再加上，如此的結構亦可提供填入第一閘極160與第二閘極165時較大的製程窗口。
第7圖為本揭露一些實施方式之製造半導體結構的剖面圖。第7圖與第6B圖之半導體裝置的不同處在於絕緣結構170、第一閘極160與第二閘極165的形狀。在第7圖中，絕緣結構170具有一頂部174與一底部176。底部176置於頂部174與基板110之間。頂部174具有實質同寬之寬度，而底部176的寬度朝基板110漸寬。詳細而言，頂部174具有寬度Wt，底部176具有寬度Wb，而絕緣結構170之頂部174與底部176之間的界面具有寬度Wm。在第7圖中，寬度Wt實質等於寬度Wm且實質短於寬度Wb。更進一步地，毗鄰頂部174之側壁164實質筆直(垂直)，而毗鄰底部176之側壁164實質圓滑。換言之，第一閘極160具有一實質圓角163，其面向絕緣結構170與基板110。另外，毗鄰頂部174之側壁169實質筆直(垂直)，而毗鄰底部176之側壁169實質圓滑。換言之，第二閘極165具有一實質圓角168，其面向絕緣結構170與基板110。因第7圖的半導體裝置其他相關的結構細節與第6B圖的半導體裝置相似，因此便不再贅述。
第8圖為本揭露一些實施方式之製造半導體結構的剖面圖。第8圖與第7圖之半導體裝置的不同處在於絕緣結構170之底部176的形狀。在第8圖中，底部176具有尖銳邊角(corner)，且寬度Wt實質等於或短於寬度Wm，且實質短於寬度Wb。詳細而言，絕緣結構170之下表面170b與毗鄰底部176之側壁164之間形成之夾角θ3b實質小於90度，亦即夾角θ3b為銳角。絕緣結構170之下表面170b與毗鄰底部176之側壁169之間形成之另一夾角θ4b實質小於90度，亦即夾角θ4b為銳 角。更進一步地，絕緣結構170之下表面170b與毗鄰頂部174之側壁164之間形成之夾角θ3t實質大於夾角θ3b。絕緣結構170之下表面170b與毗鄰頂部174之側壁169之間形成之夾角θ4t實質大於夾角θ4b。另外，絕緣結構170之底部176的高度Hb滿足0<Hb<200奈米。因第8圖的半導體裝置其他相關的結構細節與第7圖的半導體裝置相似，因此便不再贅述。
第9圖為本揭露一些實施方式之製造半導體結構的剖面圖。第9圖與第8圖之半導體裝置的不同處在於絕緣結構170之頂部174與底部176的形狀。在第9圖中，寬度Wt實質等於或短於寬度Wm，且實質短於寬度Wb。詳細而言，絕緣結構170之下表面170b與毗鄰底部176之側壁164之間形成之夾角θ3b為約80度至約90度。絕緣結構170之下表面170b與毗鄰底部176之側壁169之間形成之夾角θ4b為約80度至約90度。更進一步的，絕緣結構170之下表面170b與毗鄰頂部174之側壁164之間形成之夾角θ3t小於或等於夾角θ3b。絕緣結構170之下表面170b與毗鄰頂部174之側壁169之間形成之夾角θ4t小於或等於夾角θ4b。另外，絕緣結構170之底部176的高度Hb滿足0<Hb<200奈米。因第9圖的半導體裝置其他相關的結構細節與第8圖的半導體裝置相似，因此便不再贅述。
另外，第7圖至第9圖的製程方法與第6B圖的製程方法相似。第7圖至第9圖的第一凹槽與第二凹槽的形成方法可與第3A圖與第3B圖的製程方法相似或不同。第一凹槽與第二凹槽(與第一閘極160、第二閘極165與絕緣結構170)的外觀可和用不同蝕刻方法或蝕刻條件調整。
如上所述，在第3A圖與第3B圖中，假性層130被圖案化成第一凹槽132與第二凹槽134。因此，第一凹槽132靠近假性結構136之上表面136t的開口大於第一凹槽132靠近假性結構136之下表面136b的開口；且第二凹槽134靠近假性結構136之上表面136t的開口大於第二凹槽134靠近假性結構136之下表面136b的開口。藉由如此的結構，第5B圖的第一閘極160可容易地被填入於第一凹槽132中，且並不會於第一閘極160與基板110之間形成一空間。同樣的，第5B圖的第二閘極165可容易地被填入於第二凹槽134中，且並不會於第二閘極165與基板110之間形成一空間。因此，第一閘極160與第二閘極165的電性性能可被改善。
根據本揭露之一些實施方式，一種半導體裝置包含基板、第一閘極、第二閘極與絕緣結構。基板包含第一鰭與第二鰭。第一閘極置於第一鰭上。第二閘極置於第二鰭上。第一閘極與第二閘極之間形成間隙，且間隙往基板漸寬。絕緣結構置於間隙中。絕緣結構具有相對之上表面與下表面，下表面面向基板，且上表面面向第一閘極之邊緣往上表面內彎。
根據本揭露之一些實施方式，一種半導體裝置包含基板、第一閘極、第二閘極與絕緣結構。基板包含第一鰭與第二鰭。第一閘極置於第一鰭上。第二閘極置於第二鰭上，且與第一閘極互相分離。絕緣結構置於第一閘極與第二閘極之間。絕緣結構具有相對之上表面與下表面，絕緣結構之下表面面向基板。絕緣結構之下表面的面積大於絕緣結構 之上表面的面積，且絕緣結構之上表面面向第一閘極之邊緣往上表面內彎。
根據本揭露之一些實施方式，一種半導體裝置的製造方法包含提供基板，包含第一鰭與第二鰭。形成假性層於基板上以覆蓋第一鰭與第二鰭。圖案化假性層，以於第一鰭與第二鰭之間形成假性結構，且暴露出第一鰭與第二鰭。分別形成第一閘極與第二閘極於假性結構的相對側。第一閘極覆蓋第一鰭，且第二閘極覆蓋第二鰭。移除假性結構，以在第一閘極與第二閘極之間形成間隙。形成絕緣結構於間隙中。
上述已概述數個實施方式的特徵，因此熟習此技藝者可更了解本揭露之態樣。熟悉此技藝者應了解到，其可輕易地利用本揭露做為基礎，來設計或潤飾其他製程與結構，以實現與在此所介紹之實施方式相同之目的及/或達到相同的優點。熟悉此技藝者也應了解到，這類對等架構並未脫離本揭露之精神和範圍，且熟悉此技藝者可在不脫離本揭露之精神和範圍下，進行各種之更動、取代與潤飾。
110‧‧‧基板
112‧‧‧第一鰭
114‧‧‧第二鰭
116‧‧‧絕緣結構
120‧‧‧閘極絕緣層
160‧‧‧第一閘極
164、169‧‧‧側壁
165‧‧‧第二閘極
170‧‧‧絕緣結構
170b‧‧‧下表面
170t‧‧‧上表面
G‧‧‧間隙
θ3、θ4‧‧‧夾角

Claims (10)

  1. 一種半導體裝置，包含：一基板，包含一第一鰭與一第二鰭；一第一閘極，置於該第一鰭上；一第二閘極，置於該第二鰭上，其中該第一閘極與該第二閘極之間形成一間隙，且該間隙往該基板漸寬；以及一絕緣結構，置於該間隙中，其中該絕緣結構具有相對之一上表面與一下表面，該下表面面向該基板，且該上表面面向該第一閘極之一邊緣往該上表面內彎。
  2. 如請求項1所述之半導體裝置，其中該第一閘極之數量為複數個，且該半導體裝置更包含：一介電層，置於兩相鄰之該些第一閘極之間。
  3. 如請求項1所述之半導體裝置，其中該絕緣結構之該下表面與該第一閘極面向該絕緣結構之一側壁形成一第一角度，且該第一角度小於90度。
  4. 如請求項1所述之半導體裝置，其中該第一閘極具有一圓角，面向該絕緣結構與該基板。
  5. 一種半導體裝置，包含：一基板，包含一第一鰭與一第二鰭；一第一閘極，置於該第一鰭上； 一第二閘極，置於該第二鰭上，且與該第一閘極互相分離；以及一絕緣結構，置於該第一閘極與該第二閘極之間，其中該絕緣結構具有相對之一上表面與一下表面，該絕緣結構之該下表面面向該基板，該絕緣結構之該下表面的面積大於該絕緣結構之該上表面的面積，且該絕緣結構之該上表面面向該第一閘極之一邊緣往該上表面內彎。
  6. 如請求項5所述之半導體裝置，其中該第一閘極具有面向該基板之一下表面，該第一閘極之該下表面與該第一閘極面向該第二閘極之一側壁之間形成一第一角度，且該第一角度大於90度。
  7. 如請求項5所述之半導體裝置，其中該絕緣結構具有一頂部與一底部，該底部置於該頂部與該基板之間，該頂部之寬度短於該底部之寬度。
  8. 一種半導體裝置的製造方法，包含：提供一基板，包含一第一鰭與一第二鰭；形成一假性層於該基板上以覆蓋該第一鰭與該第二鰭；圖案化該假性層，以於該第一鰭與該第二鰭之間形成一假性結構，且暴露出該第一鰭與該第二鰭； 分別形成一第一閘極與一第二閘極於該假性結構的相對側，其中該第一閘極覆蓋該第一鰭，且該第二閘極覆蓋該第二鰭；移除該假性結構，以在該第一閘極與該第二閘極之間形成一間隙；以及形成一絕緣結構於該間隙中。
  9. 如請求項8所述之方法，其中該第一閘極之數量為複數個，且該方法更包含：形成一介電層於兩相鄰之該些第一閘極之間。
  10. 如請求項8所述之方法，更包含：形成一遮罩於該假性層上；以及圖案化該遮罩以於該第一鰭與該第二鰭之間形成一圖案化遮罩，其中該假性層係藉由該圖案化遮罩而被圖案化。
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US20180033698A1 (en) 2018-02-01
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