TWI564433B - 用於電子裝置中金屬化作用之蝕刻化學 - Google Patents

用於電子裝置中金屬化作用之蝕刻化學 Download PDF

Info

Publication number
TWI564433B
TWI564433B TW104106711A TW104106711A TWI564433B TW I564433 B TWI564433 B TW I564433B TW 104106711 A TW104106711 A TW 104106711A TW 104106711 A TW104106711 A TW 104106711A TW I564433 B TWI564433 B TW I564433B
Authority
TW
Taiwan
Prior art keywords
etchant
layer
acid
metal
exposed portion
Prior art date
Application number
TW104106711A
Other languages
English (en)
Other versions
TW201538797A (zh
Inventor
派崔克 后根
強恩 墨爾
亞力士 布瑞爾
亞瑞德 沛提特
Original Assignee
史達克公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 史達克公司 filed Critical 史達克公司
Publication of TW201538797A publication Critical patent/TW201538797A/zh
Application granted granted Critical
Publication of TWI564433B publication Critical patent/TWI564433B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/1288Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00Etching metallic material by chemical means
    • C23F1/02Local etching
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00Etching metallic material by chemical means
    • C23F1/10Etching compositions
    • C23F1/14Aqueous compositions
    • C23F1/16Acidic compositions
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00Etching metallic material by chemical means
    • C23F1/10Etching compositions
    • C23F1/14Aqueous compositions
    • C23F1/16Acidic compositions
    • C23F1/18Acidic compositions for etching copper or alloys thereof
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00Etching metallic material by chemical means
    • C23F1/10Etching compositions
    • C23F1/14Aqueous compositions
    • C23F1/16Acidic compositions
    • C23F1/26Acidic compositions for etching refractory metals
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00Etching metallic material by chemical means
    • C23F1/10Etching compositions
    • C23F1/14Aqueous compositions
    • C23F1/16Acidic compositions
    • C23F1/30Acidic compositions for etching other metallic material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/1296Multistep manufacturing methods adapted to increase the uniformity of device parameters
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41733Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H01L29/4958Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
    • H01L29/66765Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651Silicon transistors
    • H01L29/7866Non-monocrystalline silicon transistors
    • H01L29/78663Amorphous silicon transistors
    • H01L29/78669Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1343Electrodes
    • G02F1/13439Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/1368Active matrix addressed cells in which the switching element is a three-electrode device
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00Materials and properties
    • G02F2202/10Materials and properties semiconductor
    • G02F2202/103Materials and properties semiconductor a-Si

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Mechanical Engineering (AREA)
  • Materials Engineering (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • ing And Chemical Polishing (AREA)
  • Weting (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

用於電子裝置中金屬化作用之蝕刻化學 相關申請案
本申請案主張2014年3月7日申請之美國臨時專利申請案第61/949,641號之權利及優先權,該案之整體揭示內容以引用方式併入本文中。
在各種不同實施例中,本發明係關於諸如平板顯示器之電子裝置之金屬化作用,尤其關於用於進行該金屬化作用之蝕刻化學。
平板顯示器已快速地遍佈各種市場,且目前通常用於多種電器、電視機、電腦、行動電話、及其他電子裝置中。常用平板顯示器之一個實例為薄膜電晶體(TFT)液晶顯示器(LCD)(或TFT-LCD)。典型TFT-LCD包含各自控制光自LCD之像素或子像素發射之TFT之陣列。圖1描繪可見於TFT-LCD中的習知TFT 100之理想化截面。如所顯示,TFT 100包括形成於玻璃基板110上之閘極電極105。閘極絕緣體115使閘極電極105與上覆導電結構電絕緣。在閘極電極105之電控制下,通常由非晶型矽組成之活性層120使電荷在源極電極125及汲極電極130之間傳導,且所傳導的電荷控制與其所連接之像素或子像素(未顯示)之操作。源極/汲極絕緣體132使源極電極125與汲極電極130電隔離,且保護性地密封TFT 100。如所顯示,閘極電極105、源極電極125、 及汲極電極130通常各自包括障壁金屬層135及在其之上之金屬導體層140。障壁135提供導體140與底層玻璃及/或矽之間之良好黏著性及減少或防止其間之擴散。
隨時間的推移,LCD面板尺寸增加,而基於TFT的像素尺寸卻減小,從而對TFT-LCD結構中導體的要求越來越高。為減小導體中之電阻且藉此增加電信號在TFT-LCD中之傳播速度,製造商現將諸如銅(Cu)之低電阻率金屬用於顯示器中之導體140。已將諸如鉬(Mo)、鈦(Ti)、或鉬-鈦合金(Mo-Ti)之金屬用於Cu導體140下之障壁135。然而,特定言之,隨著部件尺寸持續減小,在製造TFT-LCD期間,該等金屬之處理存在困難。例如,如圖2中所顯示,在用習知濕式蝕刻化學蝕刻電極(諸如閘極電極105)期間,可產生(一或兩種電極材料之)蝕刻殘餘物200或蝕刻間斷點210(例如,(由兩種不同電極材料之不均勻蝕刻速率所引起)之階梯式或非線性輪廓)。
有鑑於前述,需要可於處理用於諸如TFT-LCD之電子裝置之金屬雙層期間使用,且可以蝕刻速率僅具有最小(若有的話)非均勻性且不產生有害蝕刻殘餘物之方式進行該蝕刻之改良的蝕刻化學。
根據本發明之各種不同實施例,特徵為兩種或更多種不同金屬材料之層狀堆疊之圖案化金屬結構(例如,用於LCD之TFT之部分)係使用可在待蝕刻金屬材料及任一其上配置該等金屬材料之基底層或基板(例如,玻璃或Si基板)之間提供高蝕刻選擇性之改良的蝕刻劑來蝕刻。除此之外,蝕刻化學實質上非選擇性地蝕刻待蝕刻結構之各種金屬材料(換言之,該等金屬材料係以實質上相同速率蝕刻),藉此最大限度減少或實質上消除介於不同金屬材料之間之界面處之任何的間斷點或「階梯」。另外,根據本發明實施例之蝕刻化學蝕刻金屬材料,同時在接近蝕刻結構之側壁處留下極少(若有的話)蝕刻殘餘物(例如,一 或多種所蝕刻金屬材料之殘餘物);該等側壁本身亦實質上筆直。(如本文所用,為適用於側壁,當以平面圖觀察時,「筆直」意指實質上線性、及/或實質上符合用於蝕刻圖案化結構之上覆遮罩材料之輪廓。筆直側壁可與「波形」側壁對比,「波形」側壁可由在蝕刻期間底切或部分地移除遮罩材料所產生。)
在本發明之各種不同實施例中,蝕刻劑包括(基本上由、或由)鹽酸、甲磺酸、硝酸、及視情況選用之檸檬酸及/或非酸稀釋劑之混合物(組成)。在各種不同實施例中,稀釋劑為水(例如,去離子(DI)水)。另外,在各種不同實施例中,蝕刻劑包含以重量計多於48%(例如,至少49%)之稀釋劑及因而包含少於52%之酸。蝕刻劑甚至可包含50%酸、49%酸、45%酸、或更少酸。該等相當稀的蝕刻劑組合物通常較容易處理及處置,且由於其中酸含量較少而較為便宜。在各種不同實施例中,蝕刻劑包括(基本上由、或由)以重量計(除非另有指示,否則本文所提供之所有百分比均係以重量計)5%至10%硝酸、5%至15%鹽酸、及20%至40%甲磺酸、0%至7%檸檬酸(或2%至7%檸檬酸)、及水(例如,去離子水)之混合物(組成)。在特定實施案中,蝕刻劑可包括(基本上由、或由)7%硝酸、9%鹽酸、33%甲磺酸、及51%水之混合物(組成),或蝕刻劑可包括(基本上由、或由)7%硝酸、12%鹽酸、30%甲磺酸、及51%水之混合物(組成),或蝕刻劑可包括(基本上由、或由)7%硝酸、12%鹽酸、25%甲磺酸、及56%水之混合物(組成),或蝕刻劑可包括(基本上由、或由)7%硝酸、5%鹽酸、37%甲磺酸、及51%水之混合物(組成),或蝕刻劑可包括(基本上由、或由)7%硝酸、12%鹽酸、30%甲磺酸、5%檸檬酸、及46%水之混合物(組成),或蝕刻劑可包括(基本上由、或由)9%硝酸、12%鹽酸、30%甲磺酸、及49%水之混合物(組成)。
在本發明之其他實施例中,蝕刻劑包括(基本上由、或由)磷酸、 甲磺酸、硝酸、及視情況選用之非酸稀釋劑之混合物(組成)。在各種不同實施例中,稀釋劑為水(例如,去離子(DI)水)。另外,在各種不同實施例中,蝕刻劑包含以重量計多於15%之稀釋劑及因而包含小於85%之酸。蝕刻劑甚至可包含80%酸或更少酸(例如,約74%至78%酸)。在各種不同實施例中,蝕刻劑包括(基本上由、或由)2%至5%硝酸、40%至75%磷酸、及5%至30%甲磺酸、及水之混合物(組成)。在特定實施案中,蝕刻劑可包括(基本上由、或由)3.5%硝酸、60%磷酸、15%甲磺酸、及21.5%水(組成),或蝕刻劑可包括(基本上由、或由)3.5%硝酸、50%磷酸、20%甲磺酸、及26.5%水(組成),或蝕刻劑可包括(基本上由、或由)3.5%硝酸、68.6%磷酸、10%甲磺酸、及17.9%水(組成)。
根據本發明實施例使用的蝕刻劑尤其適於蝕刻包括或基本上由下列組成之金屬結構:(i)一或多種耐火金屬(例如,Mo及/或鎢(W))或一或多種耐火金屬與一或多種其他金屬組分之合金及(ii)在其上之包括(基本上由、或由)例如Cu、銀(Ag)、金(Au)、或鋁(Al)(組成)之高度導電金屬或合金之雙層。該等金屬雙層尤其可用作TFT之部分(例如,電極),如下文詳述。其他金屬組分可包括諸如鉭(Ta)、鈮(Nb)、Mo、鎢(W)、鋯(Zr)、鉿(Hf)、錸(Re)、鋨(Os)、釕(Ru)、銠(Rh)、Ti、釩(V)、鉻(Cr)、及/或鎳(Ni)之金屬,且其他金屬組分可以1至50%之重量濃度(即,重量%)(個別地或共同地)存在於合金中,如2014年6月5日申請之美國專利申請案序號14/296,796、及2014年6月5日申請之美國專利申請案序號14/296,800中所述,各案之整體揭示內容係以引用方式併入本文中。在較佳實施例中,待蝕刻之雙層包括(基本上由、或由)頂部有Cu層之Mo及/或W之層(組成)。金屬結構之多個(例如,兩個)層較佳在本文所述蝕刻劑中展現實質上相等的蝕刻速率。因此,透過使用該等蝕刻劑,可最大限度減少或消除與蝕刻相關之殘 餘物及間斷點。
在一個態樣中,本發明之實施例之特徵在於一種形成薄膜電晶體之電極之方法。提供一包含(基本上由、或由)矽及/或玻璃(組成)之基底層。在該基底層之上沉積障壁層。該障壁層包含(基本上由、或由)一或多種耐火金屬或一或多種耐火金屬與一或多種其他金屬組分之合金(組成)。在該障壁層之上沉積導體層。該導體層包含(基本上由、或由)Cu、Ag、Au、及/或Al(組成)。在該障壁層之上形成遮罩層。該遮罩層係經圖案化以露出該導體層之一部分,該遮罩層之其餘部分至少部分地界定電極之形狀。此後,施用蝕刻劑以移除該導體層及該障壁層之未被圖案化遮罩層掩蔽之部分,藉此形成該電極之側壁,該側壁包括(a)該障壁層之暴露部分、(b)該導體層之暴露部分、及(c)介於該障壁層之暴露部分及該導體層之暴露部分之間之界面。該蝕刻劑包括(基本上由、或由)(i)鹽酸、甲磺酸、硝酸、及水之混合物或(ii)磷酸、甲磺酸、硝酸、及水之混合物(組成)。
本發明之實施例可包括呈各種組合中任何一種組合之一或多項下述實施例。儘管在該障壁層之暴露部分及該導體層之暴露部分之間存有界面,但是該電極之側壁可實質上無間斷點。在緊鄰該介於障壁層之暴露部分及該導體層之暴露部分之間之界面處,該障壁層之暴露部分可自該導體層之暴露部分突出約6μm或更少。該障壁層之暴露部分可突出約1μm至約5μm。該障壁層之暴露部分可突出約1μm至約3μm。在施用蝕刻劑後,該電極於(i)介於該障壁層之暴露部分及該導體層之暴露部分之間之界面及/或(ii)介於該障壁層之暴露部分及該基底層之間之界面處可實質上無蝕刻殘餘物。該蝕刻劑可包含以重量計至少49%、或至少51%之水。該蝕刻劑可包含檸檬酸。
蝕刻劑可包含(基本上由、或由)以重量計5%至10%硝酸、5%至15%鹽酸、20%至40%甲磺酸、及0%至7%檸檬酸(組成),其餘為水。 蝕刻劑可包括(基本上由、或由)由以重量計7%硝酸、9%鹽酸、33%甲磺酸、及51%水組成之混合物(組成)。蝕刻劑可包括(基本上由、或由)由以重量計7%硝酸、12%鹽酸、30%甲磺酸、及51%水組成之混合物(組成)。蝕刻劑可包括(基本上由、或由)由以重量計7%硝酸、12%鹽酸、25%甲磺酸、及56%水組成之混合物(組成)。蝕刻劑可包括(基本上由、或由)由以重量計7%硝酸、5%鹽酸、37%甲磺酸、及51%水組成之混合物(組成)。蝕刻劑可包括(基本上由、或由)由以重量計7%硝酸、12%鹽酸、30%甲磺酸、5%檸檬酸、及46%水組成之混合物(組成)。蝕刻劑可包括(基本上由、或由)由以重量計9%硝酸、12%鹽酸、30%甲磺酸、及49%水組成之混合物(組成)。
蝕刻劑可包含(基本上由、或由)以重量計2%至5%硝酸、40%至75%磷酸、及5%至30%甲磺酸(組成),其餘為水。蝕刻劑可包括(基本上由、或由)由以重量計3.5%硝酸、60%磷酸、15%甲磺酸、及21.5%水組成之混合物(組成)。蝕刻劑可包括(基本上由、或由)由以重量計3.5%硝酸、50%磷酸、20%甲磺酸、及26.5%水組成之混合物(組成)。蝕刻劑可包括(基本上由、或由)由以重量計3.5%硝酸、68.6%磷酸、10%甲磺酸、及17.9%水組成之混合物(組成)。
障壁層可包含(基本上由、或由)Mo、W、或Mo及W之合金(組成)。障壁層可包含(基本上由、或由)Mo及/或W與一或多種其他金屬組分之合金(組成)。導體層可包含(基本上由、或由)Cu(組成)。障壁層可包含(基本上由、或由)Mo(組成)及/或導體層可包含(基本上由、或由)Cu(組成)。遮罩層可包含(基本上由、或由)光阻劑(組成)。可移除圖案化遮罩層之剩餘部分。基底層可包含(基本上由、或由)玻璃(組成)。基底層可包含(基本上由、或由)矽(組成)。基底層可包含(基本上由、或由)非晶型矽(組成)。
在另一個態樣中,本發明之實施例之特徵在於一種蝕刻金屬雙 層之方法。提供包括(基本上由、或由)(i)基底層、(ii)配置在該基底層之上之第一金屬層、及(iii)配置在該第一金屬層之上之第二金屬層(組成)之結構。該第二金屬層不同於該第一金屬層(亦即,該第二金屬層包含(基本上由、或由)一或多種不同於該第一金屬層之一或多種金屬之金屬(組成))。在該第二金屬層之上形成遮罩層。該遮罩層係經圖案化以露出該第二金屬層之一部分,該遮罩層之剩餘部分界定預定形狀。此後,施用蝕刻劑以移除該第二金屬層及該第一金屬層之未被圖案化遮罩層掩蔽之部分,藉此形成具有側壁之金屬雙層,該側壁包括(a)該第一金屬層之暴露部分、(b)該第二金屬層之暴露部分、及(c)介於該第一金屬層之暴露部分及該第二金屬層之暴露部分之間之界面。該蝕刻劑包括(基本上由、或由)(i)鹽酸、甲磺酸、硝酸、及水之混合物或(ii)磷酸、甲磺酸、硝酸、及水之混合物(組成)。
本發明之實施例可包括呈各種組合中任何一種組合之一或多項下述實施例。該基底層可包含(基本上由、或由)矽及/或玻璃(組成)。該第一金屬層可包含(基本上由、或由)一或多種耐火金屬或一或多種耐火金屬與一或多種其他金屬組分之合金(組成)。該第二金屬層可包含(基本上由、或由)Cu、Ag、Au、及/或Al(組成)。儘管該第一金屬層之暴露部分及該第二金屬層之暴露部分之間存有界面,但是該金屬雙層之側壁可實質上無間斷點。在緊鄰該介於該第一金屬層之暴露部分及該第二金屬層之暴露部分之間之界面處,該第一金屬層之暴露部分可自該第二金屬層之暴露部分突出約6μm或更少。該第一金屬層之暴露部分可突出約1μm至約5μm。該第一金屬層之暴露部分可突出約1μm至約3μm。在施用該蝕刻劑後,該金屬雙層可於(i)介於該第一金屬層之暴露部分及該第二金屬層之暴露部分之間之界面及/或(ii)介於該第一金屬層之暴露部分及該基底層之間之界面處實質上無蝕刻殘餘物。該蝕刻劑可包含以重量計至少49%水、或至少51%水。該蝕 刻劑可包含檸檬酸。
蝕刻劑可包含(基本上由、或由)以重量計5%至10%硝酸、5%至15%鹽酸、20%至40%甲磺酸、及0%至7%檸檬酸(組成),其餘為水。蝕刻劑可包括(基本上由、或由)由以重量計7%硝酸、9%鹽酸、33%甲磺酸、及51%水組成之混合物(組成)。蝕刻劑可包括(基本上由、或由)由以重量計7%硝酸、12%鹽酸、30%甲磺酸、及51%水組成之混合物(組成)。蝕刻劑可包括(基本上由、或由)由以重量計7%硝酸、12%鹽酸、25%甲磺酸、及56%水組成之混合物(組成)。蝕刻劑可包括(基本上由、或由)由以重量計7%硝酸、5%鹽酸、37%甲磺酸、及51%水組成之混合物(組成)。蝕刻劑可包括(基本上由、或由)由以重量計7%硝酸、12%鹽酸、30%甲磺酸、5%檸檬酸、及46%水組成之混合物(組成)。蝕刻劑可包括(基本上由、或由)由以重量計9%硝酸、12%鹽酸、30%甲磺酸、及49%水組成之混合物(組成)。
蝕刻劑可包含(基本上由、或由)以重量計2%至5%硝酸、40%至75%磷酸、及5%至30%甲磺酸(組成),其餘為水。蝕刻劑可包括(基本上由、或由)由以重量計3.5%硝酸、60%磷酸、15%甲磺酸、及21.5%水組成之混合物(組成)。蝕刻劑可包括(基本上由、或由)由以重量計3.5%硝酸、50%磷酸、20%甲磺酸、及26.5%水組成之混合物(組成)。蝕刻劑可包括(基本上由、或由)由以重量計3.5%硝酸、68.6%磷酸、10%甲磺酸、及17.9%水組成之混合物(組成)。
第一金屬層可包含(基本上由、或由)Mo、W、或Mo及W之合金(組成)。第一金屬層可包含(基本上由、或由)Mo及/或W與一或多種其他金屬組分之合金(組成)。第二金屬層可包含(基本上由、或由)Cu(組成)。第一金屬層可包含(基本上由、或由)Mo(組成),且第二金屬層可包含(基本上由、或由)Cu(組成)。遮罩層可包含(基本上由、或由)光阻劑(組成)。可移除圖案化遮罩層之剩餘部分。基底層可包含(基本上 由、或由)玻璃(組成)。基底層可包含(基本上由、或由)矽(組成)。基底層可包含(基本上由、或由)非晶型矽(組成)。
在又另一態樣中,本發明之實施例之特徵在於一種用於實質上非選擇性地蝕刻配置在基底層之上之金屬雙層之部分而不蝕刻該基底層之蝕刻劑。該金屬雙層包括(基本上由、或由)(i)第一金屬層及(ii)(a)不同於該第一金屬層且(b)配置在該第一金屬層之上之第二金屬層(組成)。該蝕刻劑包括(基本上由、或由)(i)鹽酸、甲磺酸、硝酸、及水之混合物或(ii)磷酸、甲磺酸、硝酸、及水之混合物(組成)。
本發明之實施例可包括呈各種組合中任何一種組合之一或多項下述實施例。該基底層可包含(基本上由、或由)矽及/或玻璃(組成)。該第一金屬層可包含(基本上由、或由)一或多種耐火金屬或一或多種耐火金屬與一或多種其他金屬組分之合金(組成)。該第二金屬層可包含(基本上由、或由)Cu、Ag、Au、及/或Al(組成)。該蝕刻劑可經組態以蝕刻該金屬雙層,且藉此形成該金屬雙層之側壁,儘管該第一金屬層之暴露部分及該第二金屬層之暴露部分之間存有界面,但是該側壁實質上無間斷點。在緊鄰該介於該第一金屬層之暴露部分及該第二金屬層之暴露部分之間之界面處,該第一金屬層之暴露部分可自該第二金屬層之暴露部分突出約6μm或更少。該第一金屬層之暴露部分可突出約1μm至約5μm。該第一金屬層之暴露部分可突出約1μm至約3μm。在蝕刻該金屬雙層之後,蝕刻劑可經組態以在(i)介於該第一金屬層之暴露部分及該第二金屬層之暴露部分之間之界面及/或(ii)介於該第一金屬層之暴露部分及該基底層之間之界面處實質上無蝕刻殘餘物殘留。該蝕刻劑可包含以重量計至少49%水、或至少51%水。該蝕刻劑可包含檸檬酸。
蝕刻劑可包含(基本上由、或由)以重量計5%至10%硝酸、5%至15%鹽酸、20%至40%甲磺酸、及0%至7%檸檬酸(組成),其餘為水。 蝕刻劑可包括(基本上由、或由)由以重量計7%硝酸、9%鹽酸、33%甲磺酸、及51%水組成之混合物(組成)。蝕刻劑可包括(基本上由、或由)由以重量計7%硝酸、12%鹽酸、30%甲磺酸、及51%水組成之混合物(組成)。蝕刻劑可包括(基本上由、或由)由以重量計7%硝酸、12%鹽酸、25%甲磺酸、及56%水組成之混合物(組成)。蝕刻劑可包括(基本上由、或由)由以重量計7%硝酸、5%鹽酸、37%甲磺酸、及51%水組成之混合物(組成)。蝕刻劑可包括(基本上由、或由)由以重量計7%硝酸、12%鹽酸、30%甲磺酸、5%檸檬酸、及46%水組成之混合物(組成)。蝕刻劑可包括(基本上由、或由)由以重量計9%硝酸、12%鹽酸、30%甲磺酸、及49%水組成之混合物(組成)。
蝕刻劑可包含(基本上由、或由)以重量計2%至5%硝酸、40%至75%磷酸、及5%至30%甲磺酸(組成),其餘為水。蝕刻劑可包括(基本上由、或由)由以重量計3.5%硝酸、60%磷酸、15%甲磺酸、及21.5%水組成之混合物(組成)。蝕刻劑可包括(基本上由、或由)由以重量計3.5%硝酸、50%磷酸、20%甲磺酸、及26.5%水組成之混合物(組成)。蝕刻劑可包括(基本上由、或由)由以重量計3.5%硝酸、68.6%磷酸、10%甲磺酸、及17.9%水組成之混合物(組成)。
第一金屬層可包含(基本上由、或由)Mo、W、或Mo及W之合金(組成)。第一金屬層可包含(基本上由、或由)Mo及/或W與一或多種其他金屬組分之合金(組成)。第二金屬層可包含(基本上由、或由)Cu(組成)。第一金屬層可包含(基本上由、或由)Mo(組成),且第二金屬層可包含(基本上由、或由)Cu(組成)。蝕刻劑可經組態以不蝕刻施覆在第二金屬層之部分之上之遮罩層。遮罩層可包含(基本上由、或由)光阻劑(組成)。基底層可包含(基本上由、或由)玻璃(組成)。基底層可包含(基本上由、或由)矽(組成)。基底層可包含(基本上由、或由)非晶型矽(組成)。
藉由參考以下描述、附圖、及申請專利範圍將可更瞭解本文所揭示的本發明之該等及其他目標、及優點及特徵。另外,應瞭解,本文所述的各種不同實施例之特徵並不相互排斥及可以各種組合及排列存在。如本文所用,術語「約」及「實質上」意指±10%,及在一些實施例中,意指±5%。除非本文另外定義,否則術語「基本上由...組成」意指不包括有助於起作用之其他材料。儘管如此,該等其他材料可共同地或個別地以微量存在。例如,基本上由多種金屬組成之結構一般將僅包含彼等金屬及僅包含可透過化學分析偵測到但無助於起作用之非刻意性的雜質(其可係金屬或非金屬)。如本文所用,「基本上由至少一種金屬組成」係指一種金屬或兩種或更多種金屬之混合物,但並非金屬及非金屬元素或諸如氧或氮之化學物質之化合物(例如,金屬氮化物或金屬氧化物);此等非金屬元素或化學物質可共同地或個別地以微量(例如作為雜質)存在。如本文所用,「基板」或「基底層」係指其上配置有或未配置一或多個其他層之支撐構件(例如,半導體基板(諸如矽、GaAs、GaN、SiC、藍寶石、或InP)或包括(或基本上由)另一材料(例如)諸如玻璃之絕緣材料(組成)之平臺),或指該一或多個其他層本身。
100‧‧‧薄膜電晶體(TFT)
105‧‧‧閘極電極
110‧‧‧玻璃基板
115‧‧‧閘極絕緣體
120‧‧‧活性層
125‧‧‧源極電極
130‧‧‧汲極電極
132‧‧‧源極/汲極絕緣體
135‧‧‧障壁金屬層
140‧‧‧金屬導體層
200‧‧‧蝕刻殘餘物
210‧‧‧蝕刻間斷點
300‧‧‧障壁層
310‧‧‧基板
320‧‧‧導體層
330‧‧‧遮罩層
400‧‧‧電極
410‧‧‧側壁
420‧‧‧界面
430‧‧‧角度
500‧‧‧金屬結構
505‧‧‧Cu層
510‧‧‧Mo層
515‧‧‧矽基板
520‧‧‧間斷點
525‧‧‧鋸齒狀側壁
550‧‧‧金屬結構
555‧‧‧Cu層
560‧‧‧Mo層
565‧‧‧基板
570‧‧‧間斷點
575‧‧‧側壁
在該等圖式中,不同視圖中的相同參考符號一般指相同部件。再者,該等圖式不一定係按比例繪製,反之,一般重點在於說明本發明之原理。在隨後的描述中,參考以下圖式來描述本發明之各種不同實施例,其中:圖1為用於液晶顯示器之薄膜電晶體之截面示意圖;圖2為經蝕刻的習知TFT電極之截面示意圖;圖3及4為TFT電極在根據本發明之各種不同實施例製造期間之截面示意圖; 圖5A為藉由習知蝕刻化學蝕刻之金屬結構之平面光學顯微圖;及圖5B為藉由根據本發明之實施例之蝕刻化學蝕刻之金屬結構之平面光學顯微圖。
圖3描繪根據本發明之實施例製造TFT閘極電極中之初始步驟。如所顯示,藉由(例如)濺鍍或其他物理沉積製程在基板310(例如,玻璃或矽基板)上沉積障壁層300。隨後藉由(例如)濺鍍或其他物理沉積製程在障壁層300上沉積導體層320。通常,障壁層300之厚度將在導體層320之厚度之約5%與約25%之間(例如,約10%)。例如,障壁層300之厚度可為約50nm,且導體層320之厚度可為約500nm。在導體層320之上形成遮罩層330(例如,光阻劑)及藉由習知光微影術圖案化。
如圖4中所顯示,接著藉由(較佳)以單一步驟濕式蝕刻來蝕刻導體層320及障壁層300之未被遮罩層330覆蓋之部分而製得電極400(例如,閘極電極)。使用濕蝕刻劑以實質上相同速率蝕刻除去該等金屬層,從而獲得實質上平滑及/或線性且在介於導體層320及障壁層300之間之界面420處實質上無任何間斷點(例如,階梯式或非線性輪廓)之側壁410。
該濕蝕刻劑可包括(基本上由、或由)例如鹽酸、甲磺酸、硝酸、及視情況選用之檸檬酸及/或非酸稀釋劑之混合物(組成)。在各種不同實施例中,該稀釋劑為水(例如,去離子(DI)水)。另外,在各種不同實施例中,該蝕刻劑包含以重量計多於48%(例如,至少49%)之稀釋劑及因而包含少於52%之酸。該蝕刻劑甚至可包含50%酸、49%酸、45%酸、或更少酸。此等相當稀的蝕刻劑組合物通常較容易處理及處置,且由於其中的酸含量較少而較為便宜。在各種不同實施例中,該蝕刻劑包括(基本上由、或由)以重量計(除非另有指示,否則本文中所 提供之所有百分比均係以重量計)5%至10%硝酸、5%至15%鹽酸、及20%至40%甲磺酸、0%至7%檸檬酸(或2%至7%檸檬酸)、及水(例如,去離子水)之混合物(組成)。在特定實施案中,該蝕刻劑可包括(基本上由、或由)7%硝酸、9%鹽酸、33%甲磺酸、及51%水之混合物(組成),或該蝕刻劑可包括(基本上由、或由)7%硝酸、12%鹽酸、30%甲磺酸、及51%水之混合物(組成),或該蝕刻劑可包括(基本上由、或由)7%硝酸、12%鹽酸、25%甲磺酸、及56%水之混合物(組成),或該蝕刻劑可包括(基本上由、或由)7%硝酸、5%鹽酸、37%甲磺酸、及51%水之混合物(組成),或該蝕刻劑可包括(基本上由、或由)7%硝酸、12%鹽酸、30%甲磺酸、5%檸檬酸、及46%水之混合物(組成),或該蝕刻劑可包括(基本上由、或由)9%硝酸、12%鹽酸、30%甲磺酸、及49%水之混合物(組成)。
在其他實施例中,該濕蝕刻劑可包括(基本上由、或由)磷酸、甲磺酸、硝酸、及視情況選用之非酸稀釋劑之混合物(組成)。在各種不同實施例中,該稀釋劑為水(例如,去離子(DI)水)。另外,在各種不同實施例中,該蝕刻劑包含以重量計多於15%之稀釋劑及因而包含少於85%之酸。該蝕刻劑甚至可包含80%酸或更少酸(例如,約74%至78%酸)。在各種不同實施例中,該蝕刻劑包括(基本上由、或由)2%至5%硝酸、40%至75%磷酸、及5%至30%甲磺酸、及水之混合物(組成)。在特定實施案中,該蝕刻劑可包括(基本上由、或由)3.5%硝酸、60%磷酸、15%甲磺酸、及21.5%水(組成),或該蝕刻劑可包括(基本上由、或由)3.5%硝酸、50%磷酸、20%甲磺酸、及26.5%水(組成),或該蝕刻劑可包括(基本上由、或由)3.5%硝酸、68.6%磷酸、10%甲磺酸、及17.9%水(組成)。
在蝕刻製程之後,基板310(及電極400)可藉由(例如)DI水沖洗並乾燥(例如,藉由旋轉或高速氣流)。在蝕刻之後,基板310(及電極 400)較佳在緊鄰電極400之區域中實質上不含導體層320及障壁層300中之一者或兩者之蝕刻殘餘物。根據本發明之各種不同實施例,濕式蝕刻製程係在室溫下進行。在其他實施例中,將蝕刻劑加熱至介於40℃及60℃之間之溫度。可將濕蝕刻劑噴灑於基板310上,或可將基板310部分地或完全地浸泡於濕蝕刻劑中。濕式蝕刻製程可以分批(即,多基板)製程或以單基板製程進行。蝕刻時間(即,基板及/或其上的層暴露於蝕刻劑的時間量)可為(例如)240秒或更短時間、或甚至180秒或更短時間,然而,可使用更長時間以移除較厚層。在較佳實施例中,於蝕刻之後,側壁410與底層基板310之表面形成介於約50°與約70°之間(例如約60°)之角度430。在蝕刻之後,遮罩層330可藉由習知方式移除,例如,丙酮、商業光阻劑剝離劑、及/或暴露於氧電漿。
圖5A為經習知蝕刻化學蝕刻(在此情況中係PAN蝕刻,即,磷酸、乙酸、及硝酸之混合物)之金屬結構500之平面光學顯微圖。金屬結構500之特徵在於500nm Cu層505位於50nm Mo層510頂部,此兩層配置在矽基板515上。(雖然未顯示於圖5A中,但在蝕刻期間,Cu層505被光阻劑層掩蔽。)如所顯示,經蝕刻之金屬結構500之特徵在於Cu層505及Mo層510之邊緣之間之相當大的間斷點520。間斷點520可(例如)在10μm及20μm之間、或甚至更大。此外,經蝕刻之金屬結構500展現相當粗糙、鋸齒狀側壁525。
圖5B為經根據本發明一較佳實施例之蝕刻劑蝕刻之金屬結構550之平面光學顯微圖。金屬結構550之特徵在於500nm Cu層555位於50nm Mo層560頂部,此兩層配置在矽基板565上。(雖然未顯示於圖5B中,但在蝕刻期間,Cu層555被光阻劑層掩蔽。)如所顯示,經蝕刻之金屬結構550之特徵在於Cu層555及Mo層560之邊緣之間之小得多的間斷點570。間斷點570可(例如)在1μm與5μm之間、在1μm與3μm之間、或甚至更小。另外,經蝕刻之金屬結構550展現平滑且實質上筆 直之側壁575。此外,經蝕刻之金屬結構在介於基板565與Mo層560之間之界面處、及在介於Cu層555及Mo層560之間之界面處實質上無蝕刻殘餘物。
實例
製造一系列用於蝕刻研究之樣品,以比較習知蝕刻化學與根據本發明之實施例之蝕刻化學。各樣品係由矽基板、配置在該基板上之50nm Mo層、及配置在該Mo層上之500nm Cu層組成。使用光阻劑以掩蔽該基板上金屬結構之一部分,如圖3所顯示。如圖4所示意性地顯示,蝕刻該等樣品直到移除Mo及Cu層之未掩蔽部分。(由於各蝕刻劑中酸的量不同,故各樣品之蝕刻速率及因此蝕刻時間一般不同。)分析樣品以確定(1)在緊鄰經蝕刻之結構處存在或不存在金屬殘餘物(如圖2所示意性地顯示),及(2)Mo及Cu層之間之蝕刻間斷點(若存在的話)之階梯尺寸(如圖2所示意性地顯示)。平行於基板之平面來測定階梯尺寸。結果概述於下表中。
用於本實驗中之各種蝕刻劑之化學成分如下,其中所有濃度均係以重量計。首先,對照組蝕刻劑(習知PAN蝕刻劑)為50%磷酸、10%乙酸、5%硝酸、及35%水之混合物。蝕刻劑1為7%硝酸、9%鹽酸、33%甲磺酸、及51%水之混合物。蝕刻劑2為7%硝酸、12%鹽 酸、30%甲磺酸、及51%水之混合物。蝕刻劑3為60%磷酸、3.5%硝酸、15%甲磺酸、及21.5%水之混合物。蝕刻劑4為7%硝酸、12%鹽酸、25%甲磺酸、及56%水之混合物。蝕刻劑5為7%硝酸、5%鹽酸、37%甲磺酸、及51%水之混合物。蝕刻劑6為7%硝酸、12%鹽酸、30%甲磺酸、5%檸檬酸、及46%水之混合物。蝕刻劑7為50%磷酸、3.5%硝酸、20%甲磺酸、及26.5%水之混合物。蝕刻劑8為68.6%磷酸、3.5%硝酸、10%甲磺酸、及17.9%水之混合物。蝕刻劑9為9%硝酸、12%鹽酸、30%甲磺酸、及49%水之混合物。
如蝕刻結果證實,根據本發明之實施例之蝕刻劑1至10成功地蝕刻Mo及Cu層,僅造成極小蝕刻間斷點。比較而言,對照組蝕刻劑蝕刻該等層,同時形成比根據本發明之實施例之表現最佳的蝕刻劑大約一個數量級的蝕刻間斷點,因而證實根據本發明之實施例之蝕刻化學之優異性。
本文所用的術語及表述語係用作描述性但不具限制性之術語及表述語,且在使用此等術語及表述語時,無意排除所顯示並描述之特徵或其部分之任何等效物。此外,已描述本發明之特定實施例,一般技術者應明瞭,可在不脫離本發明之精神及範疇下使用包含本文所揭示概念之其他實施例。因此,所述實施例在所有方面中均應被視作僅係例示性而非限制性。
300‧‧‧障壁層
310‧‧‧基板
320‧‧‧導體層
330‧‧‧遮罩層
400‧‧‧電極
410‧‧‧側壁
420‧‧‧界面
430‧‧‧角度

Claims (79)

  1. 一種形成薄膜電晶體之電極之方法,該方法包括:提供一包含矽或玻璃中至少一者之基底層;於該基底層之上沉積包含一或多種耐火金屬或一或多種耐火金屬與一或多種其他金屬組分之合金之障壁層;於該障壁層之上沉積包含Cu、Ag、Au、或Al中至少一者之導體層;於該障壁層之上形成遮罩層;將該遮罩層圖案化以露出該導體層之一部分,該遮罩層之剩餘部分至少部分地界定該電極之形狀;此後,施用蝕刻劑以移除該導體層及該障壁層之未被該圖案化遮罩層掩蔽之部分,藉此形成電極之側壁,該側壁包括(a)該障壁層之暴露部分、(b)該導體層之暴露部分、及(c)介於該障壁層之暴露部分及該導體層之暴露部分之間之界面,其中該蝕刻劑包括鹽酸、甲磺酸、硝酸、及水之混合物。
  2. 如請求項1之方法,其中,儘管該障壁層之暴露部分及該導體層之暴露部分之間存有界面,但是該電極之該側壁實質上無間斷點(discontinuities)。
  3. 如請求項1之方法,其中,在緊鄰該介於該障壁層之暴露部分及該導體層之暴露部分之間之界面處,該障壁層之暴露部分自該導體層之暴露部分突出6μm或更少。
  4. 如請求項3之方法,其中該障壁層之暴露部分突出1μm至5μm。
  5. 如請求項3之方法,其中該障壁層之暴露部分突出1μm至3μm。
  6. 如請求項1之方法,其中,在施用該蝕刻劑後,該電極於(i)介於該障壁層之暴露部分及該導體層之暴露部分之間之界面及(ii)介 於該障壁層之暴露部分及該基底層之間之界面處無蝕刻殘餘物。
  7. 如請求項1之方法,其中該蝕刻劑包含以重量計至少49%水。
  8. 如請求項1之方法,其中該蝕刻劑包含以重量計至少51%水。
  9. 如請求項1之方法,其中該蝕刻劑包含檸檬酸。
  10. 如請求項1之方法,其中該蝕刻劑包含以重量計5%至10%硝酸、5%至15%鹽酸、20%至40%甲磺酸、及0%至7%檸檬酸,其餘為水。
  11. 如請求項1之方法,其中該蝕刻劑包括由以重量計7%硝酸、9%鹽酸、33%甲磺酸、及51%水組成之混合物。
  12. 如請求項1之方法,其中該蝕刻劑包括由以重量計7%硝酸、12%鹽酸、30%甲磺酸、及51%水組成之混合物。
  13. 如請求項1之方法,其中該蝕刻劑包括由以重量計7%硝酸、12%鹽酸、25%甲磺酸、及56%水組成之混合物。
  14. 如請求項1之方法,其中該蝕刻劑包括由以重量計7%硝酸、5%鹽酸、37%甲磺酸、及51%水組成之混合物。
  15. 如請求項1之方法,其中該蝕刻劑包括由以重量計7%硝酸、12%鹽酸、30%甲磺酸、5%檸檬酸、及46%水組成之混合物。
  16. 如請求項1之方法,其中該蝕刻劑包括由以重量計9%硝酸、12%鹽酸、30%甲磺酸、及49%水組成之混合物。
  17. 如請求項1之方法,其中該障壁層包含Mo、W、或Mo及W之合金。
  18. 如請求項1之方法,其中該障壁層包含Mo及/或W與一或多種其他金屬組分之合金。
  19. 如請求項1之方法,其中該導體層包含Cu。
  20. 如請求項1之方法,其中該障壁層包含Mo及該導體層包含Cu。
  21. 如請求項1之方法,其中該遮罩層包含光阻劑。
  22. 如請求項1之方法,其進一步包括移除該圖案化遮罩層之剩餘部分。
  23. 如請求項1之方法,其中該基底層包含玻璃。
  24. 如請求項1之方法,其中該基底層包含矽。
  25. 如請求項24之方法,其中該基底層包含非晶型矽。
  26. 一種蝕刻金屬雙層之方法,該方法包括:提供一包括(i)基底層、(ii)配置在該基底層之上之第一金屬層、及(iii)配置在該第一金屬層之上之第二金屬層之結構,該第二金屬層係不同於該第一金屬層;於該第二金屬層之上形成遮罩層;將該遮罩層圖案化以露出該第二金屬層之一部分,該遮罩層之剩餘部分界定預定形狀;此後,施用蝕刻劑以移除該第二金屬層及該第一金屬層之未被圖案化遮罩層掩蔽之部分,藉此形成具有側壁之金屬雙層,該側壁包括(a)該第一金屬層之暴露部分、(b)該第二金屬層之暴露部分、及(c)介於該第一金屬層之暴露部分及該第二金屬層之暴露部分之間之界面,其中該蝕刻劑包括鹽酸、甲磺酸、硝酸、及水之混合物。
  27. 如請求項26之方法,其中該基底層包含矽或玻璃中之至少一者。
  28. 如請求項26之方法,其中該第一金屬層包含一或多種耐火金屬或一或多種耐火金屬與一或多種其他金屬組分之合金。
  29. 如請求項26之方法,其中該第二金屬層包含Cu、Ag、Au、或Al中之至少一者。
  30. 如請求項26之方法,其中儘管該第一金屬層之暴露部分及該第 二金屬層之暴露部分之間存有界面,但是該金屬雙層之該側壁實質上無間斷點。
  31. 如請求項26之方法,其中,在緊鄰該介於該第一金屬層之暴露部分及該第二金屬層之暴露部分之間之界面處,該第一金屬層之暴露部分自該第二金屬層之暴露部分突出6μm或更少。
  32. 如請求項31之方法,其中該第一金屬層之暴露部分突出1μm至5μm。
  33. 如請求項31之方法,其中該第一金屬層之暴露部分突出1μm至3μm。
  34. 如請求項26之方法,其中,在施用該蝕刻劑後,該金屬雙層於(i)介於該第一金屬層之暴露部分及該第二金屬層之暴露部分之間之界面及(ii)介於該第一金屬層之暴露部分及該基底層之間之界面處無蝕刻殘餘物。
  35. 如請求項26之方法,其中該蝕刻劑包含以重量計至少49%水。
  36. 如請求項26之方法,其中該蝕刻劑包含以重量計至少51%水。
  37. 如請求項26之方法,其中該蝕刻劑包含檸檬酸。
  38. 如請求項26之方法,其中該蝕刻劑包含以重量計5%至10%硝酸、5%至15%鹽酸、20%至40%甲磺酸、及0%至7%檸檬酸,其餘為水。
  39. 如請求項26之方法,其中該蝕刻劑包括由以重量計7%硝酸、9%鹽酸、33%甲磺酸、及51%水組成之混合物。
  40. 如請求項26之方法,其中該蝕刻劑包括由以重量計7%硝酸、12%鹽酸、30%甲磺酸、及51%水組成之混合物。
  41. 如請求項26之方法,其中該蝕刻劑包括由以重量計7%硝酸、12%鹽酸、25%甲磺酸、及56%水組成之混合物。
  42. 如請求項26之方法,其中該蝕刻劑包括由以重量計7%硝酸、5% 鹽酸、37%甲磺酸、及51%水組成之混合物。
  43. 如請求項26之方法,其中該蝕刻劑包括由以重量計7%硝酸、12%鹽酸、30%甲磺酸、5%檸檬酸、及46%水組成之混合物。
  44. 如請求項26之方法,其中該蝕刻劑包括由以重量計9%硝酸、12%鹽酸、30%甲磺酸、及49%水組成之混合物。
  45. 如請求項26之方法,其中該第一金屬層包含Mo、W、或Mo及W之合金。
  46. 如請求項26之方法,其中該第一金屬層包含Mo及/或W與一或多種其他金屬組分之合金。
  47. 如請求項26之方法,其中該第二金屬層包含Cu。
  48. 如請求項26之方法,其中該第一金屬層包含Mo及該第二金屬層包含Cu。
  49. 如請求項26之方法,其中該遮罩層包含光阻劑。
  50. 如請求項26之方法,其進一步包括移除該圖案化遮罩層之剩餘部分。
  51. 如請求項26之方法,其中該基底層包含玻璃。
  52. 如請求項26之方法,其中該基底層包含矽。
  53. 如請求項52之方法,其中該基底層包含非晶型矽。
  54. 一種用於實質上非選擇性地蝕刻配置在基底層之上之金屬雙層之部分而不蝕刻該基底層之蝕刻劑,該金屬雙層包括(i)第一金屬層及(ii)(a)不同於該第一金屬層且(b)配置在該第一金屬層之上之第二金屬層,該蝕刻劑包括鹽酸、甲磺酸、硝酸、及水之混合物。
  55. 如請求項54之蝕刻劑,其中該基底層包含矽或玻璃中之至少一者。
  56. 如請求項54之蝕刻劑,其中該第一金屬層包含一或多種耐火金 屬或一或多種耐火金屬與一或多種其他金屬組分之合金。
  57. 如請求項54之蝕刻劑,其中該第二金屬層包含Cu、Ag、Au、或Al中之至少一者。
  58. 如請求項54之蝕刻劑,其中該蝕刻劑係經組態以蝕刻該金屬雙層,且藉此形成該金屬雙層之側壁,儘管該第一金屬層之暴露部分及該第二金屬層之暴露部分之間存有界面,但是該側壁實質上無間斷點。
  59. 如請求項54之蝕刻劑,其中(i)該蝕刻劑係經組態以蝕刻該金屬雙層,且藉此形成該在該第一金屬層之暴露部分及該第二金屬層之暴露部分之間具有界面之金屬雙層之側壁,且(ii)在緊鄰介於該第一金屬層之暴露部分及該第二金屬層之暴露部分之間之界面處,該第一金屬層之暴露部分自該第二金屬層之暴露部分突出6μm或更少。
  60. 如請求項59之蝕刻劑,其中該第一金屬層之暴露部分突出1μm至5μm。
  61. 如請求項59之蝕刻劑,其中該第一金屬層之暴露部分突出1μm至3μm。
  62. 如請求項54之蝕刻劑,其中該蝕刻劑係經組態以(i)蝕刻該金屬雙層,且藉此形成該在該第一金屬層之暴露部分及該第二金屬層之暴露部分之間具有界面之金屬雙層之側壁,及(ii)在蝕刻該金屬雙層之後,在(a)介於該第一金屬層之暴露部分及該第二金屬層之暴露部分之間之界面及(b)介於該第一金屬層之暴露部分及該基底層之間之界面處無蝕刻殘餘物殘留。
  63. 如請求項54之蝕刻劑,其中該蝕刻劑包含以重量計至少49%水。
  64. 如請求項54之蝕刻劑,其中該蝕刻劑包含以重量計至少51%水。
  65. 如請求項54之蝕刻劑,其中該蝕刻劑包含檸檬酸。
  66. 如請求項54之蝕刻劑,其中該蝕刻劑包含以重量計5%至10%硝酸、5%至15%鹽酸、20%至40%甲磺酸、及0%至7%檸檬酸,其餘為水。
  67. 如請求項54之蝕刻劑,其中該蝕刻劑包括由以重量計7%硝酸、9%鹽酸、33%甲磺酸、及51%水組成之混合物。
  68. 如請求項54之蝕刻劑,其中該蝕刻劑包括由以重量計7%硝酸、12%鹽酸、30%甲磺酸、及51%水組成之混合物。
  69. 如請求項54之蝕刻劑,其中該蝕刻劑包括由以重量計7%硝酸、12%鹽酸、25%甲磺酸、及56%水組成之混合物。
  70. 如請求項54之蝕刻劑,其中該蝕刻劑包括由以重量計7%硝酸、5%鹽酸、37%甲磺酸、及51%水組成之混合物。
  71. 如請求項54之蝕刻劑,其中該蝕刻劑包括由以重量計7%硝酸、12%鹽酸、30%甲磺酸、5%檸檬酸、及46%水組成之混合物。
  72. 如請求項54之蝕刻劑,其中該蝕刻劑包括由以重量計9%硝酸、12%鹽酸、30%甲磺酸、及49%水組成之混合物。
  73. 如請求項54之蝕刻劑,其中該第一金屬層包含Mo、W、或Mo及W之合金。
  74. 如請求項54之蝕刻劑,其中該第一金屬層包含Mo及/或W與一或多種其他金屬組分之合金。
  75. 如請求項54之蝕刻劑,其中該第二金屬層包含Cu。
  76. 如請求項54之蝕刻劑,其中該第一金屬層包含Mo及該第二金屬層包含Cu。
  77. 如請求項54之蝕刻劑,其中該基底層包含玻璃。
  78. 如請求項54之蝕刻劑,其中該基底層包含矽。
  79. 如請求項78之蝕刻劑,其中該基底層包含非晶型矽。
TW104106711A 2014-03-07 2015-03-03 用於電子裝置中金屬化作用之蝕刻化學 TWI564433B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US201461949641P 2014-03-07 2014-03-07

Publications (2)

Publication Number Publication Date
TW201538797A TW201538797A (zh) 2015-10-16
TWI564433B true TWI564433B (zh) 2017-01-01

Family

ID=54018163

Family Applications (2)

Application Number Title Priority Date Filing Date
TW104106711A TWI564433B (zh) 2014-03-07 2015-03-03 用於電子裝置中金屬化作用之蝕刻化學
TW105130663A TWI608128B (zh) 2014-03-07 2015-03-03 用於電子裝置中金屬化作用之蝕刻化學

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW105130663A TWI608128B (zh) 2014-03-07 2015-03-03 用於電子裝置中金屬化作用之蝕刻化學

Country Status (6)

Country Link
US (3) US9455283B2 (zh)
JP (1) JP2017510090A (zh)
KR (1) KR102287017B1 (zh)
CN (1) CN106170869B (zh)
TW (2) TWI564433B (zh)
WO (1) WO2015134456A1 (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9455283B2 (en) * 2014-03-07 2016-09-27 H.C. Starck, Inc. Etch chemistries for metallization in electronic devices
DE102016105056A1 (de) * 2016-03-18 2017-09-21 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines optoelektronischen Halbleiterchips und optoelektronischer Halbleiterchip
JP6769760B2 (ja) * 2016-07-08 2020-10-14 関東化学株式会社 エッチング液組成物およびエッチング方法
KR102388085B1 (ko) * 2017-05-29 2022-04-18 동우 화인켐 주식회사 금속막 식각액 조성물 및 이를 이용한 도전 패턴 형성 방법
KR102368027B1 (ko) * 2017-05-22 2022-02-25 동우 화인켐 주식회사 금속막 식각액 조성물 및 이를 이용한 도전 패턴 형성 방법
CN108930037B (zh) * 2017-05-22 2021-02-26 东友精细化工有限公司 金属膜蚀刻液组合物及利用其的导电图案形成方法
KR101926274B1 (ko) * 2017-11-17 2018-12-06 동우 화인켐 주식회사 은 박막 식각액 조성물 및 이를 이용한 식각 방법 및 금속 패턴의 형성 방법
KR20190058758A (ko) * 2017-11-21 2019-05-30 삼성디스플레이 주식회사 식각액 조성물 및 이를 이용한 디스플레이 장치의 제조방법
KR20190111724A (ko) * 2018-03-23 2019-10-02 동우 화인켐 주식회사 은 박막 식각액 조성물 및 이를 이용한 식각 방법 및 금속 패턴의 형성 방법
KR102650435B1 (ko) * 2019-06-14 2024-03-26 삼성디스플레이 주식회사 표시 패널
KR102659176B1 (ko) 2020-12-28 2024-04-23 삼성디스플레이 주식회사 은 함유 박막의 식각 조성물, 이를 이용한 패턴 형성 방법 및 표시장치의 제조 방법
CN112680229A (zh) * 2021-01-29 2021-04-20 深圳市百通达科技有限公司 一种湿电子化学的硅基材料蚀刻液及其制备方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200616071A (en) * 2004-11-05 2006-05-16 Mitsubishi Chem Corp Etchant and method of etching
TW200811314A (en) * 2006-08-22 2008-03-01 Kanto Kagaku Etchant compositions for metal laminated films having titanium and aluminum layer
US20140024206A1 (en) * 2012-07-23 2014-01-23 Dongwoo Fine-Chem Co., Ltd. Etchant composition and method of forming metal wire and thin film transistor array panel using the same

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100866976B1 (ko) * 2002-09-03 2008-11-05 엘지디스플레이 주식회사 액정표시장치용 어레이기판과 제조방법
JP4093147B2 (ja) 2003-09-04 2008-06-04 三菱電機株式会社 エッチング液及びエッチング方法
TWI351765B (en) * 2007-08-29 2011-11-01 Au Optronics Corp Display element and method of manufacturing the sa
WO2010013636A1 (ja) * 2008-07-29 2010-02-04 株式会社アルバック 配線膜、薄膜トランジスタ、ターゲット、配線膜の形成方法
KR101499239B1 (ko) * 2008-08-26 2015-03-06 삼성디스플레이 주식회사 박막 트랜지스터 표시판 및 그 제조 방법
KR101582946B1 (ko) 2009-12-04 2016-01-08 삼성디스플레이 주식회사 박막 트랜지스터 표시판 및 그 제조 방법
KR101845083B1 (ko) * 2010-12-10 2018-04-04 동우 화인켐 주식회사 액정표시장치용 어레이 기판의 제조방법
KR101895421B1 (ko) * 2011-02-24 2018-09-07 삼성디스플레이 주식회사 배선, 박막 트랜지스터, 및 박막 트랜지스터 표시판과 이들을 제조하는 방법들
KR20120138074A (ko) * 2011-06-14 2012-12-24 삼성디스플레이 주식회사 박막 트랜지스터, 및 박막 트랜지스터 표시판과 이들을 제조하는 방법
US8878176B2 (en) * 2011-08-11 2014-11-04 The Hong Kong University Of Science And Technology Metal-oxide based thin-film transistors with fluorinated active layer
KR101404511B1 (ko) * 2012-07-24 2014-06-09 플란제 에스이 식각액 조성물, 및 다중금속막 식각 방법
KR102002131B1 (ko) * 2012-08-03 2019-07-22 삼성디스플레이 주식회사 식각액 조성물 및 이를 이용한 박막 트랜지스터 제조 방법
JP6291570B2 (ja) * 2013-06-06 2018-03-14 エイチ.シー. スターク インコーポレイテッド 電子素子における金属被覆のための銅合金障壁層およびキャッピング層
US9455283B2 (en) * 2014-03-07 2016-09-27 H.C. Starck, Inc. Etch chemistries for metallization in electronic devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200616071A (en) * 2004-11-05 2006-05-16 Mitsubishi Chem Corp Etchant and method of etching
TW200811314A (en) * 2006-08-22 2008-03-01 Kanto Kagaku Etchant compositions for metal laminated films having titanium and aluminum layer
US20140024206A1 (en) * 2012-07-23 2014-01-23 Dongwoo Fine-Chem Co., Ltd. Etchant composition and method of forming metal wire and thin film transistor array panel using the same

Also Published As

Publication number Publication date
JP2017510090A (ja) 2017-04-06
US20160372500A1 (en) 2016-12-22
US10186530B2 (en) 2019-01-22
WO2015134456A1 (en) 2015-09-11
CN106170869B (zh) 2020-01-10
KR102287017B1 (ko) 2021-08-05
US20150255494A1 (en) 2015-09-10
TWI608128B (zh) 2017-12-11
KR20160130808A (ko) 2016-11-14
CN106170869A (zh) 2016-11-30
TW201700791A (zh) 2017-01-01
US20190148420A1 (en) 2019-05-16
US9455283B2 (en) 2016-09-27
US10923514B2 (en) 2021-02-16
TW201538797A (zh) 2015-10-16

Similar Documents

Publication Publication Date Title
TWI564433B (zh) 用於電子裝置中金屬化作用之蝕刻化學
US11392257B2 (en) Copper-alloy capping layers for metallization in touch-panel displays
JP6078063B2 (ja) 薄膜トランジスタデバイスの製造方法
TW201634754A (zh) 用於銀薄層的蝕刻劑組合物,使用其形成金屬圖案的方法和使用其製作陣列基板的方法
JP2007157916A (ja) Tft基板及びtft基板の製造方法
TW201809356A (zh) 含銀薄膜的蝕刻液組合物及利用其的顯示基板
US10739879B2 (en) Current-induced dark layer formation for metallization in electronic devices
TW201313879A (zh) 用於金屬互連體之蝕刻劑以及使用其以製備液晶顯示元件的方法
JP2004156070A (ja) 透明導電膜を含む積層膜のエッチング液組成物
JP2012189725A (ja) Ti合金バリアメタルを用いた配線膜および電極、並びにTi合金スパッタリングターゲット
JP2012188691A (ja) Ti合金配線膜および電極、並びにTi合金スパッタリングターゲット
JP2010258346A (ja) 表示装置およびこれに用いるCu合金膜
KR20180090081A (ko) 은 함유 박막 식각액 조성물 및 이를 이용한 표시장치용 어레이기판의 제조방법
TWI645074B (zh) 用於銀層的蝕刻劑組合物和形成金屬圖案的方法及用其製造顯示基板的方法
KR20170006480A (ko) 다층막 식각액 조성물 및 이를 이용한 액정 표시 장치용 어레이 기판의 제조방법
KR20190000331A (ko) 은 함유 박막 식각액 조성물 및 이를 이용한 표시장치용 어레이기판의 제조방법
KR20170127308A (ko) 식각액 조성물 및 이를 이용한 표시 장치용 어레이 기판의 제조방법

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees