TWI555148B - 半導體結構 - Google Patents

半導體結構 Download PDF

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TWI555148B
TWI555148B TW101136960A TW101136960A TWI555148B TW I555148 B TWI555148 B TW I555148B TW 101136960 A TW101136960 A TW 101136960A TW 101136960 A TW101136960 A TW 101136960A TW I555148 B TWI555148 B TW I555148B
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layer
titanium
semiconductor structure
thickness
silver
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TW101136960A
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TW201415588A (zh
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邱祥清
吳聲明
楊光浩
林恭安
王晨聿
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頎邦科技股份有限公司
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Priority to US13/677,518 priority patent/US20140097540A1/en
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    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
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    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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Description

半導體結構
本發明係有關於一種半導體結構，特別係有關於一種可降低電阻之半導體結構。
習知半導體製程中，為了改善高功率IC散熱問題而開發出晶背金屬化製程(Back Side Metal Process)，其係在晶圓背面蒸鍍或濺鍍一層或多層可做為接合/導熱用的金屬層，該金屬層亦可再接合基材(例如：散熱片/Lead frame)，以達到較佳的散熱及導電效果，目前一般蒸鍍或濺鍍於晶圓背面之金屬層大多選用金或銀，但目前金價居高不下，因此基於成本考量下，銀層係為較佳選擇，然銀層與矽晶圓之間必須以鈦層作為黏著層，但後端封裝製程中溫度過高而鈦層厚度薄時，銀層會融化而擴散至矽-鈦層，造成矽晶圓與銀層剝離，反之，溫度過高而鈦層厚度厚時，鈦-銀層會產生介面合金共化物，因而導致電阻抗上升。
本發明之主要目的係在於提供一種半導體結構，其包含一矽基板、一鈦層、一鎳層、一銀層以及一金屬材質黏著層，該矽基板係具有一主動面及一背面，該鈦層係形成於該背面，該鈦層係具有一上表面，該鎳層係形成於該鈦層之該上表面，該銀層係形成於該鎳層上，該金屬材質黏著層係形成於該鎳層及該銀層之間。藉由該金屬材質黏著層使該鎳層與該銀層具有良好之結合強度 ，且該鎳層可作為一良好之阻障層，進而使該半導體結構達到最佳的散熱及導電效果，並降低封裝後的電阻抗。
請參閱第1圖及附件1，其係本發明之一較佳實施例，一種半導體結構100係包含一矽基板110、一鈦層120、一鎳層130、一銀層140以及一金屬材質黏著層150，該矽基板110係具有一主動面111及一背面112，該矽基板110之該主動面111係可形成有複數個線路及複數個電連接元件(圖未繪出)，該鈦層120係形成於該背面112，該鈦層120係具有一上表面121，該鈦層120之厚度範圍係介於100-10000Å，其中該鈦層120形成於該矽基板110之該背面112之前，必須先經過下列步驟：首先，貼設一保護膠帶(圖未繪出)於該矽基板110之該主動面111，接著，研磨該矽基板110之該背面112以薄化該矽基板110，之後，蝕刻該矽基板110之該背面112以增加該背面112之粗糙度，進而提高該鈦層120及該矽基板110之結合強度，接著，利用蒸鍍或濺鍍方法使該鈦層120形成於該矽基板110之該背面112，之後，該鎳層130係形成於該鈦層120之該上表面121，該鎳層130之厚度範圍係介於100-10000Å，該銀層140係形成於該鎳層130上，該銀層140之厚度範圍係介於100-100000Å，該金屬材質黏著層150係形成於該鎳層130及該銀層140之間，在本實施例中，該金屬材質黏著層150之材質係選自於鈦，該金屬材質黏著層150之厚度範圍係介於1-5000Å，且該金屬材質黏著層150係具有一第一厚度T1，該鈦層 120係具有一第二厚度T2，該第一厚度T1係不大於該第二厚度T2。由於鈦對於金屬材質而言係為一良好之黏著劑，因此該金屬材質黏著層150之材質選自於鈦且將該金屬材質黏著層150之厚度控制於1-5000Å，使得該半導體結構100中該鎳層130與該銀層140可藉由該金屬材質黏著層150達到良好之結合強度，且該金屬材質黏著層150與該銀層140之間不會產生介面合金共化物，此外，由於該鎳層130係位於該銀層140及該鈦層120之間，因此可作為一良好之阻障層，進而使該半導體結構100達到最佳的散熱及導電效果，並降低封裝後的電阻抗。
本發明之保護範圍當視後附之申請專利範圍所界定者為準，任何熟知此項技藝者，在不脫離本發明之精神和範圍內所作之任何變化與修改，均屬於本發明之保護範圍。
100‧‧‧半導體結構
110‧‧‧矽基板
111‧‧‧主動面
112‧‧‧背面
120‧‧‧鈦層
121‧‧‧上表面
130‧‧‧鎳層
140‧‧‧銀層
150‧‧‧金屬材質黏著層
T1‧‧‧第一厚度
T2‧‧‧第二厚度
第1圖：依據本發明之一較佳實施例，一種半導體結構示意圖。
附件1：依據本發明之一較佳實施例，該半導體結構之SEM照片圖。
100‧‧‧半導體結構
110‧‧‧矽基板
111‧‧‧主動面
112‧‧‧背面
120‧‧‧鈦層
121‧‧‧上表面
130‧‧‧鎳層
140‧‧‧銀層
150‧‧‧金屬材質黏著層
T1‧‧‧第一厚度
T2‧‧‧第二厚度

Claims (6)

  1. 一種半導體結構，其至少包含：一矽基板，其係具有一主動面及一背面；一鈦層，其係直接形成於該背面，該鈦層係具有一上表面；一鎳層，，其係形成於該鈦層之該上表面；一銀層，其係形成於該鎳層上；以及一金屬材質黏著層，其係形成於該鎳層及該銀層之間，該金屬材質黏著層係具有一第一厚度，該鈦層係具有一第二厚度，該第一厚度係不大於該第二厚度。
  2. 如申請專利範圍第1項所述之半導體結構，其中該金屬材質黏著層之材質係選自於鈦。
  3. 如申請專利範圍第1項所述之半導體結構，其中該鈦層之厚度範圍係介於100-10000Å。
  4. 如申請專利範圍第1項所述之半導體結構，其中該鎳層之厚度範圍係介於100-10000Å。
  5. 如申請專利範圍第1項所述之半導體結構，其中該銀層之厚度範圍係介於100-100000Å。
  6. 如申請專利範圍第1項所述之半導體結構，其中該金屬材質黏著層之厚度範圍係介於1-5000Å。
TW101136960A 2012-10-05 2012-10-05 半導體結構 TWI555148B (zh)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5523623A (en) * 1994-03-09 1996-06-04 Matsushita Electric Industrial Co., Ltd. Ohmic electrode for a p-type compound semiconductor and a bipolar transistor incorporating the ohmic electrode
US20070138482A1 (en) * 2005-12-08 2007-06-21 Nissan Motor Co., Ltd. Silicon carbide semiconductor device and method for producing the same
US20080099769A1 (en) * 2006-10-25 2008-05-01 Infineon Technologies Austria Ag PRODUCTION OF AN INTEGRATED CIRCUIT INCLUDING ELECTRICAL CONTACT ON SiC

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110006409A1 (en) * 2009-07-13 2011-01-13 Gruenhagen Michael D Nickel-titanum contact layers in semiconductor devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5523623A (en) * 1994-03-09 1996-06-04 Matsushita Electric Industrial Co., Ltd. Ohmic electrode for a p-type compound semiconductor and a bipolar transistor incorporating the ohmic electrode
US20070138482A1 (en) * 2005-12-08 2007-06-21 Nissan Motor Co., Ltd. Silicon carbide semiconductor device and method for producing the same
US20080099769A1 (en) * 2006-10-25 2008-05-01 Infineon Technologies Austria Ag PRODUCTION OF AN INTEGRATED CIRCUIT INCLUDING ELECTRICAL CONTACT ON SiC

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