TWI536563B - 集成電路結構及其製造方法 - Google Patents

集成電路結構及其製造方法 Download PDF

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TWI536563B
TWI536563B TW103145049A TW103145049A TWI536563B TW I536563 B TWI536563 B TW I536563B TW 103145049 A TW103145049 A TW 103145049A TW 103145049 A TW103145049 A TW 103145049A TW I536563 B TWI536563 B TW I536563B
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layer
photoresist
forming
source
contact plug
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TW201535728A (zh
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丁致遠
謝志宏
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台灣積體電路製造股份有限公司
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Description

集成電路結構及其製造方法
本發明是關於一種集成電路結構及其製造方法，特別是有關於一種無縫孔之接觸插塞及其製造方法。
在集成電路的形成中，半導體裝置形成於半導體基板上，且隨後透過金屬化層連接。金屬化層係透過接觸插塞與半導體裝置連接。此外，外部墊係透過接觸插塞與半導體裝置連接。
一般而言，接觸插塞之形成過程包含形成層間介電質(Inter-Layer Dielectric，ILD)於半導體裝置上，形成接觸開口於層間介電質內，並於接觸開口內填充金屬材料。然而，隨著集成電路尺度縮小的增加，前述之製程遇到缺陷。當水平尺寸(如：相鄰多晶矽線之間的聚對聚節距(poly-to-poly pitch))不斷縮小時，接觸插塞以及接觸插塞與自對準矽化物間的接觸區域之直徑減小。層間介電質之厚度並不會與接觸插塞寬度減少之相同比例相應地減少。因此，接觸插塞之高寬比(aspect ratio)增加，導致接觸窗形 成過程越來越多及困難。
集成電路之尺度縮小導致些許問題。首先，越來越難於填充接觸開口時，不於其中造成縫孔(孔隙)。此外，當接觸插塞之橫向尺寸減少，縫孔之尺寸並不會按比例減少。這不僅會導致接觸插塞傳導電流之有效區域不按比例地減少，亦會導致隨後形成之接觸窗蝕刻終止層以及金屬線陷入縫孔，因而導致可靠性問題。因此，形成接觸開口之製程窗口變為越來越窄，且接觸開口之形成已成為集成電路尺度縮小之瓶頸。
根據一些實施方式，一種方法包含形成基板層於裝置上，形成反轉記憶柱(reverse memory post)於基板層上，以及以反轉記憶柱作為蝕刻遮罩對基板層進行蝕刻。基板層之剩餘部分包含圓柱結構。接著，移除反轉記憶柱。
根據另一些實施方式，一種方法包含形成金屬層於金屬氧化物半導體(Metal-Oxide-Semiconductor，MOS)裝置上。金屬層包含第一底面以及第二底面，第一底面與MOS裝置之源/汲極矽化物接觸，第二底面與MOS裝置之閘極矽化物接觸。方法更包含形成光阻於金屬層上，圖案化光阻以於光阻中形成開口，以及形成反轉記憶層，以反轉記憶層之第一部分填充至光阻之開口中，並以反轉記憶層之第二部分上覆光阻。移除反轉記憶層之第二部分，且反轉記憶層之第一部分留在開口中。接著，移除光阻。以反轉記憶 層之第一部分作為蝕刻遮罩對金屬層進行蝕刻，其中金屬層之剩餘部分包含閘極接觸插塞以及源/汲極接觸插塞。接著，移除反轉記憶層之第一部分。於蝕刻金屬層之後，形成層間介電質以環繞閘極接觸插塞以及源/汲極接觸插塞。
根據又一實施方式，一種集成電路結構包含半導體基板以及位於半導體基板表面之MOS裝置。MOS裝置包含位於半導體基板上的閘電極以及位於閘電極之一側的源/汲極區。閘極接觸插塞上覆並電耦合至閘電極。源/汲極接觸插塞上覆並電耦合至源/汲極區。集成電路結構更包含層間介電質，且閘極接觸插塞以及源/汲極接觸插塞沉積於層間介電質內。層間介電質內包含孔隙。
10‧‧‧MOS裝置
12‧‧‧半導體基板
14‧‧‧淺溝槽隔離區
16‧‧‧主動區
18‧‧‧源/汲極區
20‧‧‧輕摻雜源/汲極區
22‧‧‧源/汲極矽化物
26‧‧‧閘極介電質
28‧‧‧閘電極
30‧‧‧閘極矽化物
32‧‧‧閘極間隔物
42‧‧‧導電層
42A‧‧‧頂面
44‧‧‧蓋罩層
46‧‧‧光阻
48‧‧‧微影遮罩
50‧‧‧開口
52‧‧‧反轉記憶層
52’‧‧‧反轉記憶柱
54‧‧‧閘極接觸插塞
56‧‧‧源/汲極接觸插塞
58‧‧‧層間介電質
60‧‧‧孔隙
62‧‧‧蝕刻終止層
64‧‧‧金屬間介電層
66‧‧‧金屬線
W1‧‧‧橫向尺寸
為更充分了解本實施方式及其優點，請參照下述之詳細說明並伴隨相關圖式，其中：第1至11B圖係繪示根據一些示例性的實施方式之形成集成電路結構之中間階段的剖視圖。
以下詳細敘述了本揭示實施方式之製造及使用。然而，應當瞭解的是實施方式提供多個可應用之發明觀點，其可被實施於各種特定內容。以下敘述之特定實施方式僅為示例，並不限制本揭示的範圍。
根據示例性之實施方式，提供包含用以連接金 屬氧化物半導體(Metal-Oxide-Semiconductor，MOS)裝置之接觸插塞的集成電路結構及其形成方法。根據一些實施方式，繪示形成接觸插塞之中間階段。以下敘述實施方式的變化。在各個圖示及示例性的實施方式中，相同之數字標號係用以代表相同之元件。
第1圖係繪示根據一些示例性實施例之MOS裝置10之一部分的剖視圖。MOS裝置10係形成於半導體基板12之頂面，其可包含結晶矽、結晶鍺、矽鍺、III-V族化合物半導體或者類似物。半導體基板12亦可為塊狀矽基板(bulk silicon substrate)或絕緣體上矽(Silicon-On-Insulator，SOI)基板。淺溝槽隔離(Shallow trench isolation，STI)區14可形成在半導體基板12以隔離主動區16，其係用以形成閘極堆疊於其上。MOS裝置10可進一歩包含源極和汲極區(在下文以源/汲極區表示)18、輕摻雜源/汲極(Lightly Doped source/Drain，LDD)區20以及源/汲極矽化物22。
包含閘極介電質26、閘電極28以及閘極矽化物30之閘極堆疊形成於主動區16上。閘極介電質26可由氧化矽、氮化矽、氧氮化矽、高介電常數材料，如氧化鉿、氧化鑭、氧化鋁及/或類似物形成。閘電極28可包括含矽部分，例如多晶矽區。閘極矽化物30可形成於閘電極28之頂部。閘極間隔物32形成於閘極堆疊之側壁。
請參照第2圖，導電層42形成於MOS裝置10上。在一些實施方式中，導電層42係由金屬材料形成，故 在下文以金屬層或基板層表示，其亦可由其它非金屬之導電材料形成。金屬層42包含鎢或鎢合金。舉例而言，除鎢之外，金屬層42可包含鋁、銅、鈦、鉭或其組合。金屬層42之頂面42A係高於MOS裝置10之閘極堆疊的頂面。可進行化學機械研磨(Chemical Mechanical Polish，CMP)以平坦化金屬層42之頂面42A。在一些實施方式中，金屬層42包含第一底面以及第二底面，第一底面與源/汲極矽化物22之頂面接觸，且第二底面與閘極矽化物30之頂面接觸。此外，由於金屬層42具有低的高寬比(aspect ratio)，金屬層42內沒有縫孔或大致上沒有縫孔形成。
蓋罩層44形成於金屬層42上。在一些實施方式中，蓋罩層44包含氧化矽、氮化矽、氮氧化矽、碳化矽或其它材料。蓋罩層44係作為表層以在上覆遮罩形成時，保護下層之金屬層42，其中遮罩係用以圖案化金屬層42。
然後，請參照第3圖，塗布光阻46。微影遮罩48隨後用於曝光光阻46。微影遮罩48包含透明圖案以及不透明圖案，其中透明圖案允許光線(以箭頭表示)通過，而不透明圖案遮擋光線。據此，部分之光阻46經過曝光。光阻46隨後經過顯影以形成開口50，如第4圖所示。開口50與閘極矽化物30及源/汲極矽化物22重疊。開口50之頂視形狀可為矩形或圓形。
然後，如第5圖所示，形成反轉記憶層(reverse memory layer)52。反轉記憶層52之命名係由於反轉記憶層52之最終圖案(請參照第6圖)為第4圖所示之光阻46的反 轉圖案。反轉記憶層52係由具有相對於光阻46及蓋罩層44高之蝕刻選擇性的材料所形成。在一些實施方式中，反轉記憶層52包含無機材料，如氧化矽、氮化矽、氮氧化矽、碳氧化矽或類似物。在另一些實施方式中，反轉記憶層52為含金屬材料，包含鋁、錳、鈷、鈦、鉭、鎢、鎳、錫、鎂或其合金。在又一些實施方式中，反轉記憶層52包含陶瓷，其尚可包含氧及/或氮，以及金屬選自鋁、錳、鈷、鈦、鉭、鎢、鎳、錫、鎂或其合金。
由於開口50之横向尺寸W1(請參照第4圖)較小以防止孔隙於反轉記憶層52形成，故以具有良好間隙填充能力之填充方法形成反轉記憶層52。在一些示例性的實施方式中，以原子層沉積(Atomic Layer Deposition，ALD)形成反轉記憶層52。
請參照第6圖，對反轉記憶層52進行回蝕，直至完全移除光阻46上之反轉記憶層52的多餘部分，並暴露出光阻46。蝕刻可以電漿進行，且蝕刻劑氣體係取決於反轉記憶層52的材料而選擇。蝕刻係用端點偵測(end-point detection)進行，以偵測光阻46之暴露，使反轉記憶層52的多餘部分被移除，而反轉記憶層52之填充在開口50(請參照第4圖)的部分不被過度蝕刻。
隨後移除光阻46，所得到之結構如第7圖所示。光阻46可使用，舉例而言，灰化(ashing)移除。保留填充於開口50(請參照第4圖)內之反轉記憶層52，並於說明中以反轉記憶柱52’表示。因而暴露出蓋罩層44，其係作為 下層金屬層42之蝕刻終止層及保護層。反轉記憶柱52’可具有圓形、矩形(如：正方形)或類似形狀之頂視形狀。
第8圖係繪示以反轉記憶柱52’作為蝕刻遮罩對蓋罩層44以及金屬層42(請參照第7圖)進行蝕刻。金屬層42(請參照第7圖)之剩餘部分形成閘極接觸插塞54以及源/汲極接觸插塞56。然後，移除反轉記憶柱52’以及蓋罩層44之剩餘部分，所得到之結構如第9圖所示。
在前述之實施方式中，反轉記憶柱52’係形成作為蝕刻遮罩以圖案化金屬層42，而非形成光阻柱(photo resist post)作為蝕刻遮罩以圖案化金屬層42。由於橫向尺寸W1(請同時參照第4圖中標示之橫向尺寸W1)很小，若使用光阻形成反轉記憶柱52’之圖案，將很難防止高、薄之光阻柱崩解。具優勢地，於光阻中形成小開口較形成高、薄之光阻柱簡單，故相較於光阻柱，反轉記憶柱52’具有較佳之控制尺寸。此外，反轉記憶柱52’具有較光阻柱大之機械強度，且可於圖案化金屬層42時，維持反轉記憶柱52’之形狀。
在第10圖中，形成層間介電質(Inter-Layer Dielectric，ILD)58以填充接觸插塞54及56周圍之空間。層間介電質58可具有低介電常數(k值)，其低於3.8，且可包含非多孔性低介電常數材料。在一些示例性之實施方式中，層間介電質58包含氧化矽、磷矽酸鹽玻璃(phosphosilicate glass，PSG)、硼矽酸鹽玻璃(borosilicate glass，BSG)、硼磷矽酸鹽玻璃(boron-doped phosphosilicate glass，BPSG)、氟矽酸 鹽玻璃(fluorine-doped silicate glass，FSG)或其它無機介電材料。層間介電質58可為同質材料，且自頂面至底面，整個層間介電質58係由同一材料形成。層間介電質58可用旋轉塗布、化學氣相沉積(Chemical Vapor Deposition，CVD)方法或其它適用之方法形成。填充層間介電質58後，進行化學機械研磨，以使層間介電質58之頂面與接觸插塞54及56之頂面同高度。
層間介電質58包含第一部分，其係與閘電極28同高度。層間介電質58可更包含第二部分，其係上覆於閘電極28，其中第一部分以及第二部分可為連續之層間介電質58的部分。此外，層間介電質58之底面可與源/汲極矽化物22以及閘極矽化物30接觸。在一些實施方式中，孔隙60形成於層間介電質58內。
第11A及11B圖係繪示蝕刻終止層62、金屬間介電層(Inter-Metal Dielectric，IMD)64以及金屬線66之形成。蝕刻終止層62可包含碳化矽、碳氧化矽或其它介電材料。金屬間介電層64可包含低介電常數材料，其可具有低於約3.0、低於約2.5或更低之介電常數。在一些實施方式中，金屬線66包含銅或銅合金，且可進一步包含導電擴散阻擋層(如：鈦、氮化鈦、鉭、氮化鉭，未繪示)，底襯於銅或銅合金。金屬線66之形成可透過，舉例而言，單鑲嵌進行。金屬線66係透過源/汲極矽化物22以及閘極矽化物30分別電性耦合至源/汲極區18以及閘電極28。
第11A圖係繪示根據一些實施方式的剖視圖， 其中孔隙60係局限於層間介電質58內，且蝕刻終止層62並未暴露於孔隙60。在這些實施方式中，孔隙60係完全封裝(enclosed)於層間介電質58內。在另一些實施方式中，如第11B圖所示，層間介電質58經化學機械研磨後，暴露出孔隙60，因而使得後續形成之蝕刻終止層62的底面暴露於孔隙60。在這些實施方式中，孔隙60係被層間介電質58包圍，且孔隙60之底面亦由層間介電質58所定義。
本揭示之實施方式具有一些優勢特徵。藉由蝕刻塊狀金屬層(bulk metallic layer)而形成接觸插塞，故所形成之接觸插塞並不會包含孔隙於其內。因此，根據本揭示實施方式之接觸插塞的品質及電性表現並不會受到任何孔隙之負面影響。反轉記憶層之形成以及使用反轉記憶層以形成接觸插塞確保形成薄的接觸插塞，且避免與脆弱光阻相關之問題。
根據一些實施方式，一種方法包含形成基板層於裝置上，形成反轉記憶柱於基板層上，以及以反轉記憶柱作為蝕刻遮罩對基板層進行蝕刻。基板層之剩餘部分包含圓柱結構。接著，移除反轉記憶柱。
根據另一些實施方式，一種方法包含形成金屬層於金屬氧化物半導體(MOS)裝置上。金屬層包含第一底面以及第二底面，第一底面與MOS裝置之源/汲極矽化物接觸，第二底面與MOS裝置之閘極矽化物接觸。方法更包含形成光阻於金屬層上，圖案化光阻以於光阻中形成開口，以及形成反轉記憶層，以反轉記憶層之第一部分填充至光阻之 開口中，並以反轉記憶層之第二部分上覆光阻。移除反轉記憶層之第二部分，且反轉記憶層之第一部分留在開口中。接著，移除光阻。以反轉記憶層之第一部分作為蝕刻遮罩對金屬層進行蝕刻，其中金屬層之剩餘部分包含閘極接觸插塞以及源/汲極接觸插塞。接著，移除反轉記憶層之第一部分。於蝕刻金屬層之後，形成層間介電質以環繞閘極接觸插塞以及源/汲極接觸插塞。
根據又一實施方式，一種集成電路結構包含半導體基板以及位於半導體基板表面之MOS裝置。MOS裝置包含位於半導體基板上的閘電極以及位於閘電極之一側的源/汲極區。閘極接觸插塞上覆並電耦合至閘電極。源/汲極接觸插塞上覆並電耦合至源/汲極區。集成電路結構更包含層間介電質，且閘極接觸插塞以及源/汲極接觸插塞沉積於層間介電質內。層間介電質內包含孔隙。
雖然以上已詳細說明實施方式及其優點，但應當瞭解的是可做各種改變、替換及變更而不脫離由所附之申請專利範圍定義之實施方式的精神及範圍。此外，本申請之範圍並不限定於說明書中所敘述之製程、機器、製造的具體實施方案，以及物質的組成、手段、方法及步驟。本領域具有通常知識者可由本揭示瞭解，可執行與本文所述之對應實施方式大致上相同的功能或達到大致上相同結果之製程、機器、製造、物質組成、手段、方法或步驟，不論是目前現有或之後開發，皆可依據本揭示內容運用。因此，所附申請專利範圍旨在其範圍內涵蓋此類製程、機器、製造、物質組成、 手段、方法或步驟。此外，每個權利要求構成一個單獨的實施方式，且各種權利要求及實施方式之組合係涵蓋於本揭示的範圍內。
10‧‧‧MOS裝置
12‧‧‧半導體基板
14‧‧‧淺溝槽隔離區
16‧‧‧主動區
18‧‧‧源/汲極區
20‧‧‧輕摻雜源/汲極區
22‧‧‧源/汲極矽化物
26‧‧‧閘極介電質
28‧‧‧閘電極
30‧‧‧閘極矽化物
32‧‧‧閘極間隔物
54‧‧‧閘極接觸插塞
56‧‧‧源/汲極接觸插塞
58‧‧‧層間介電質
60‧‧‧孔隙
62‧‧‧蝕刻終止層
64‧‧‧金屬間介電層
66‧‧‧金屬線

Claims (10)

  1. 一種製造集成電路結構的方法，包含：形成一基板層於一金屬氧化物半導體裝置上，該金屬氧化物半導體裝置具有一閘電極、一源極及一汲極；形成反轉記憶柱於該基板層上，該反轉記憶柱分別對應於該閘電極、該源極及該汲極之上；以該反轉記憶柱作為一蝕刻遮罩對該基板層進行蝕刻，其中該基板層之剩餘部分包含一圓柱結構；以及移除該反轉記憶柱。
  2. 如請求項1所述之方法，其中形成該反轉記憶柱包含：塗布一光阻於該基板層上；將該光阻曝光及顯影以於該光阻中形成開口；以一反轉記憶層填充該開口；移除該反轉記憶層之多餘部分，其中該反轉記憶層之該多餘部分係位於該光阻上，位於該開口內之該反轉記憶層之剩餘部分即為該反轉記憶柱；以及移除該光阻。
  3. 如請求項1所述之方法，其中該圓柱結構包含一閘極接觸插塞以及一源/汲極接觸插塞分別與該金屬氧化物半導體裝置之該閘電極以及該源/汲電極電性連接，其中該源/汲極接觸插塞包含一部分與該閘電極同高度。
  4. 一種製造集成電路結構的方法，包含：形成一金屬層於一金屬氧化物半導體裝置上，其中該 金屬層包含一第一底面以及一第二底面，該第一底面與該金屬氧化物半導體裝置之一源/汲極矽化物接觸，該第二底面與該金屬氧化物半導體裝置之一閘極矽化物接觸；形成一光阻於該金屬層上；圖案化該光阻以於該光阻中形成開口；形成一反轉記憶層，以該反轉記憶層之第一部分填充至該光阻之該開口中，並以該反轉記憶層之第二部分上覆該光阻；移除該反轉記憶層之該第二部分，該反轉記憶層之該第一部分留在該開口內；移除該光阻；以該反轉記憶層之該第一部分作為一蝕刻遮罩對該金屬層進行蝕刻，其中該金屬層之剩餘部分包含一閘極接觸插塞以及一源/汲極接觸插塞；移除該反轉記憶層之該第一部分；以及於蝕刻該金屬層之後，形成一層間介電質以環繞該閘極接觸插塞以及該源/汲極接觸插塞。
  5. 如請求項4所述之方法，其中形成該反轉記憶層包含形成一介電層、一金屬層或一包含金屬之陶瓷層。
  6. 如請求項4所述之方法，其中形成該層間介電質時，形成孔隙於該層間介電質內。
  7. 如請求項4所述之方法，更包含於形成該介電質之後，形成一低k介電層於該層間介電質上；以及 形成金屬線於該低k介電層內。
  8. 如請求項4所述之方法，其中形成該反轉記憶層包含一原子層沉積。
  9. 如請求項4所述之方法，其中移除該光阻係以端點偵測進行。
  10. 如請求項4所述之方法，其中該反轉記憶層係光阻的反轉圖案。
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