TWI525766B - 晶片封裝體 - Google Patents

晶片封裝體 Download PDF

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TWI525766B
TWI525766B TW100138670A TW100138670A TWI525766B TW I525766 B TWI525766 B TW I525766B TW 100138670 A TW100138670 A TW 100138670A TW 100138670 A TW100138670 A TW 100138670A TW I525766 B TWI525766 B TW I525766B
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layer
light shielding
conductive
chip package
shielding layer
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TW201234550A (en
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邱新智
鄭家明
許傳進
樓百堯
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精材科技股份有限公司
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Description

晶片封裝體
本發明係有關於晶片封裝體，且特別是有關於光電元件晶片封裝體。
光感測元件或發光元件等光電元件在擷取影像或提供光線的應用中扮演著重要的角色。這些光電元件均已廣泛地應用於例如是數位相機(digital camera)、數位攝錄像機(digital video recorder)、手機(mobile phone)、太陽能電池、螢幕、照明設備等的電子產品中。
隨著科技之演進，對於光感測元件之感測精準度或發光元件之發光精準度的需求亦隨之提高。
本發明一實施例提供一種晶片封裝體，包括：一基底，具有一第一表面及一第二表面；一光電元件，設置於該第一表面處；一保護層，位於該基底之該第二表面上，該保護層具有一開口；一遮光層，位於該基底之該第二表面之上，其中部分的該遮光層延伸於該保護層之該開口之中；一導電凸塊，設置於該基底之該第二表面上，且填充於該保護層之該開口之中；以及一導電層，位於該基底與該保護層之間，其中該導電層電性連接該光電元件與該導電凸塊。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間必然具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。
本發明一實施例之晶片封裝體可用以封裝光電元件，例如光感測元件或發光元件。然其應用不限於此，例如在本發明之晶片封裝體的實施例中，其可應用於各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical System;MEMS)、微流體系統(micro fluidic systems)、或利用熱、光線及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package;WSP)製程對影像感測元件、發光二極體(light-emitting diodes;LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)噴墨頭(ink printer heads)、或功率金氧半電晶體模組(power MOSFET modules)等半導體晶片進行封裝。
其中上述晶圓級封裝製程主要係指在晶圓階段完成封裝步驟後，再予以切割成獨立的封裝體，然而，在一特定實施例中，例如將已分離之半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。另外，上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓，以形成多層積體電路(multi-layer integrated circuit devices)之晶片封裝體。
第1A-1C圖顯示根據本發明一實施例之晶片封裝體的製程剖面圖。如第1A圖所示，提供基底100，其例如為半導體基底或陶瓷基底。在一實施例中，基底100包括半導體材料，其例如為半導體晶圓(如矽晶圓)而可進行晶圓級封裝以節省製程時間與成本。基底100具有表面100a與100b。表面100a與100b例如係彼此相反。
如第1A圖所示，在一實施例中，表面100a上設置有光電元件102。光電元件102可包括(但不限於)影像感測元件或發光元件。影像感測元件例如是互補式金氧半(CMOS)影像感測元件(CIS)或電荷耦合元件(charge-coupled device，CCD)感測元件，而發光元件例如是發光二極體元件。光電元件102例如可與形成於表面100a上之導電墊104電性連接，並可透過導電墊104而與其他導電通路連結。在一實施例中，可於光電元件102上設置微透鏡陣列102a以輔助光線之進入及/或發射。
雖然，第1A圖中僅顯示出單層的導電墊104。然而，多個導電墊可能係彼此堆疊及/或排列於基底100之上。例如，在一實施例中，導電墊104為多個彼此堆疊之導電墊、或至少一導電墊、或至少一導電墊與至少一層內連線結構所組成之導電墊結構。在以下之實施例中，為方便說明，圖式中僅顯示單層導電墊104以簡化圖式。
如第1A圖所示，在一實施例中，可於基底100上形成電性連接至導電墊104之導電層110。導電層110可用以電性連接光電元件102(例如，透過導電墊104)。導電層110與導電墊104之間的導電通路例如可以是穿基底導電結構或延伸於基底100之外側的線路重佈層。在第1A圖之實施例中，係以穿基底導電結構為例。在一實施例中，基底100中包括穿孔106，其自基底100之表面100b朝表面100a延伸。在一實施例中，穿孔106露出部分的導電墊104。此外，導電層110係延伸於穿孔106之側壁與基底100之表面100b之上，並電性連接導電墊104。導電層110之材質例如為(但不限於)金屬材料，如銅、鋁、金、或前述之組合等。
應注意的是，當基底100之材質具有導電性時，(例如是矽)，需於導電層110與基底100之間形成絕緣層以避免發生短路。例如，在第1A圖之實施例中，可選擇性於基底100與導電層110之間形成絕緣層108。相似地，亦可視情況於其他導電性結構與基底100之間形成絕緣層。
在一實施例中，穿孔106較佳具有“倒角結構”。即，穿孔106之口徑沿著自表面100b朝表面100a之方向遞增。可透過蝕刻條件之調整而使所形成之穿孔106具“倒角結構”之特性。穿孔106之位置較佳位於導電墊104之正上方而使至少部分的導電墊104於穿孔106之底部露出。在一些實施例中，導電墊104上可能形成有層間介電層。此時，可進行另一蝕刻製程移除層間介電層而使導電墊104於穿孔106之底部露出。
接著，例如可透過化學氣相沉積法或其他塗佈方法於穿孔106之側壁及底部上形成絕緣層108。絕緣層108可進一步延伸至基底100之表面100b上。接著，移除穿孔106底部上之絕緣層108而使導電墊104露出。由於在一實施例中，穿孔106係具有“倒角結構”。因此，穿孔106底部上之絕緣層108的蝕刻移除可採自對準之方式進行，不需額外形成圖案化遮罩層，可節省製程成本與時間。
接著，於穿孔106中之絕緣層108上形成導電層110。導電層110電性接觸導電墊104而與光電元件102電性連接。導電層110還可延伸至基底100之表面100b上。在一實施例中，可例如以物理氣相沉積法於穿孔106之側壁、底部、及表面100b上形成晶種層(未顯示)。接著，於晶種層上形成圖案化遮罩層(未顯示)。圖案化遮罩層具有數個開口，開口露出實際上欲形成導電層110之區域。接著，可透過電鍍製程於開口所露出之晶種層上電鍍沉積導電材料。接著，移除圖案化遮罩層以及對其下之晶種層進行蝕刻製程。可透過上述之方式視需求於基底100之表面100b上形成具有所需導電圖案之導電層110。導電層110亦可稱為線路重佈層。
如第1A圖所示，在形成導電層110之後，在表面100b及導電層110上形成保護層112。保護層112例如包括(但不限於)防銲材料、聚醯亞胺樹脂(polyimide)、或綠漆等。保護層112中定義有至少一開口113，其露出部分的導電層110。
接著，如第1B圖所示，於保護層112上形成遮光層114。遮光層114之材質例如可為絕緣材料，例如高分子材料。在一實施例中，遮光層114為一光阻層而可便於將之圖案化。例如，遮光層114可為一黑色的光阻層。在一實施例中，遮光層114為一負型光阻層。在一實施例中，可例如以塗佈之方式將遮光層114形成於基底100之上，並接著將之圖案化，例如圖案化為如第1B圖所示之圖案。
如第1B圖所示，在一實施例中，遮光層114可包括第一遮光層及第二遮光層，其分別是位於保護層112上之背面遮光層114a及位於保護層112之側壁上之側壁遮光層114b。在一實施例中，背面遮光層114a可進一步延伸至側壁遮光層114b而與之接觸。
遮光層114可覆蓋於光電元件102之上，可有助於阻擋及/或吸收來自晶片封裝體外部之光線，尤其是來自基底100之表面100b後之光線，因而可有利於光電元件102之運作。例如，當光電元件102為影像感測元件時，遮光層114可擋住及/或吸收來自基底100之表面100b之光線而避免造成影像雜訊。或者，當光電元件102為發光元件時，遮光層114可擋住及/或吸收來自基底100之表面100b之光線而避免晶片封裝體所發出之光線的波長及/或強度受到外界光線的影響。
在一實施例中，延伸於保護層112之開口113的側壁上之側壁遮光層114b可自開口113的側壁進一步延伸至開口113之底部上而覆蓋其下之導電層110，如第1B圖之實施例所示。在一實施例中，側壁遮光層114b可直接接觸導電層110。例如，延伸於開口113之底部上的側壁遮光層114b可直接接觸導電層110。如第1B圖之實施例所示，側壁遮光層114b於開口113底部中可具有一較小之開口，其具有寬度W1。側壁遮光層114b之開口可用以定義後續將形成之導電凸塊的位置。
接著，如第1C圖所示，於基底100之表面100b上設置導電凸塊116，其填充於保護層112之開口113中而電性接觸導電層110。即，導電凸塊116可設置於開口113中未被遮光層114所覆蓋之部分的導電層110之上。導電凸塊116例如為一銲球。導電凸塊116與導電層110之間可形成有凸塊下金屬層。導電凸塊116之設置方式可例如為網板印刷。
如第1C圖所示，在一實施例中，背面遮光層114a延伸至側壁遮光層114b，且側壁遮光層114b可覆蓋開口113之部分底部。因此，側壁遮光層114b之底部可與導電凸塊116之底部大抵共平面。此外，在一實施例中，遮光層114與導電凸塊116之間的最短距離小於保護層112與導電凸塊116之間的最短距離。例如，在第1C圖之實施例中，遮光層114與導電凸塊116係彼此直接接觸(即，遮光層114中之側壁遮光層114b直接接觸導電凸塊116)而最短距離為零，其小於保護層112與導電凸塊116之間的最短距離。然應注意的是，本發明實施例不限於此。在其他實施例中，遮光層114不直接接觸導電凸塊116而隔有一間距(未顯示)。
在一實施例中，可透過製程條件之調整而使導電凸塊具有大於遮光層114之開口寬度W1還寬之寬度W2。因此，在此情形下，導電凸塊116在開口113之底部上的投影將與遮光層114在開口113之底部上的投影重疊。如此，可確保外界之光線可大抵完全由遮光層114與導電凸塊116所阻擋及/或吸收而不致於影響光電元件102之運作。此外，在一實施例中，保護層112不接觸導電凸塊116。
在上述實施例中，保護層112係位於遮光層114與基底100之間。然而，本發明實施例不限於此。在其他實施例中，遮光層114可位於保護層112與基底100之間。第2A-2C圖顯示本發明另一實施例之晶片封裝體的製程剖面圖，其中相同或相似之標號將用以標示相同或相似之元件。
如第2A圖所示，可以類似於第1A圖實施例所述之方式於設置有光電元件102之基底100中選擇性形成穿基底導電結構。第2A圖實施例與第1A圖實施例之主要差異在於遮光層114係於形成保護層112之前便先形成於基底100之表面100b之上。
如第2A圖所示，可以相似之材質與製程方法於基底100上之導電層110上形成圖案化之遮光層114。在一實施例中，遮光層114可順應性形成於導電層110之上而與之直接接觸。
接著，如第2B圖所示，於基底100之表面100b上形成保護層112。保護層112具有開口113，其露出部分的遮光層114與部分的導電層110。在一實施例中，保護層112之開口113的寬度係大於延伸於開口113之底部上之遮光層114之開口的寬度W1。
如第2C圖所示，於保護層112之開口113中填充導電凸塊116。相似地，導電凸塊116之寬度W2大於遮光層114之開口的寬度W1。即，在此情形下，導電凸塊116在開口113之底部上的投影將與遮光層114在開口113之底部上的投影重疊。如此，可確保外界之光線可大抵完全由遮光層114與導電凸塊116所阻擋及/或吸收而不致於影響光電元件102之運作。
本發明實施例之晶片封裝體透過遮光層而阻擋及/或吸收外界之光線，可使晶片封裝體的運作更為順利。本發明實施例之晶片封裝體之遮光層進一步延伸至保護層之開口中。因此，遮光層與保護層開口中之導電凸塊可共同阻擋及/或吸收外界之光線，可提升光電元件之光線感測精準度或發光精準度。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100．．．基底
100a、100b．．．表面
102．．．光電元件
102a．．．微透鏡陣列
104．．．導電墊
106．．．穿孔
108．．．絕緣層
110．．．導電層
112．．．保護層
113．．．開口
114、114a、114b．．．遮光層
116．．．導電凸塊
W1、W2．．．寬度
第1A-1C圖顯示根據本發明一實施例之晶片封裝體的製程剖面圖。
第2A-2C圖顯示根據本發明一實施例之晶片封裝體的製程剖面圖。
100．．．基底
100a、100b．．．表面
102．．．光電元件
102a．．．微透鏡陣列
104．．．導電墊
106．．．穿孔
108．．．絕緣層
110．．．導電層
112．．．保護層
113．．．開口
114、114a、114b．．．遮光層
116．．．導電凸塊
W1、W2．．．寬度

Claims (19)

  1. 一種晶片封裝體，包括：一基底，具有一第一表面及一第二表面；一光電元件，設置於該第一表面處；一保護層，位於該基底之該第二表面上，該保護層具有一開口；一遮光層，位於該基底之該第二表面之上，其中部分的該遮光層延伸於該保護層之該開口之中，其中該遮光層為一絕緣材料；一導電凸塊，設置於該基底之該第二表面上，且填充於該保護層之該開口之中；以及一導電層，位於該基底與該保護層之間，其中該導電層電性連接該光電元件與該導電凸塊。
  2. 如申請專利範圍第1項所述之晶片封裝體，其中該遮光層包括一第一遮光層及一第二遮光層，其中該第一遮光層位於該保護層之上，該第二遮光層位於該保護層之該開口的一側壁之上。
  3. 如申請專利範圍第2項所述之晶片封裝體，其中該第一遮光層係延伸至該第二遮光層。
  4. 如申請專利範圍第3項所述之晶片封裝體，其中該第二遮光層進一步延伸於該開口之一底部之上。
  5. 如申請專利範圍第4項所述之晶片封裝體，其中該開口露出部分的該導電層，且該第二遮光層覆蓋部分的該導電層。
  6. 如申請專利範圍第5項所述之晶片封裝體，其中 該導電凸塊設置於該開口中之未被該第二遮光層所覆蓋之部分的該導電層之上。
  7. 如申請專利範圍第1項所述之晶片封裝體，其中該遮光層延伸於該開口之一底部之上。
  8. 如申請專利範圍第1項所述之晶片封裝體，其中該導電凸塊於該開口之一底部上之一投影與該遮光層於該開口之該底部上之一投影重疊。
  9. 如申請專利範圍第1項所述之晶片封裝體，其中該遮光層位於該保護層與該基底之間。
  10. 如申請專利範圍第1項所述之晶片封裝體，其中該保護層位於該遮光層與該基底之間。
  11. 如申請專利範圍第1項所述之晶片封裝體，其中該保護層不接觸該導電凸塊。
  12. 如申請專利範圍第1項所述之晶片封裝體，其中該遮光層直接接觸該導電層。
  13. 如申請專利範圍第1項所述之晶片封裝體，更包括一穿基底導電結構，包括：一穿孔，自該第二表面朝該第一表面延伸；以及一絕緣層，位於該穿孔之一側壁上，且延伸至該基底之該第二表面上；其中，該導電層延伸至該穿孔中之該絕緣層之上。
  14. 如申請專利範圍第13項所述之晶片封裝體，其中該穿孔之口徑沿著自該第二表面朝該第一表面之一方向遞增。
  15. 如申請專利範圍第13項所述之晶片封裝體，其 中該穿孔之一底部露出一導電墊，該導電墊電性連接該光電元件。
  16. 如申請專利範圍第15項所述之晶片封裝體，其中該導電層電性接觸該導電墊。
  17. 如申請專利範圍第1項所述之晶片封裝體，其中該光電元件包括一影像感測元件或一發光元件。
  18. 如申請專利範圍第1項所述之晶片封裝體，其中該遮光層之一底部與該導電凸塊之一底部大抵共平面。
  19. 如申請專利範圍第1項所述之晶片封裝體，其中該遮光層與該導電凸塊之間的一最短距離小於該保護層與該導電凸塊之間的一最短距離。
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