TWI523198B - Ｃｍｏｓ半導體晶片 - Google Patents

Ｃｍｏｓ半導體晶片 Download PDF

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TWI523198B
TWI523198B TW101113429A TW101113429A TWI523198B TW I523198 B TWI523198 B TW I523198B TW 101113429 A TW101113429 A TW 101113429A TW 101113429 A TW101113429 A TW 101113429A TW I523198 B TWI523198 B TW I523198B
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type metal
dummy
metal gate
region
regions
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TW101113429A
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TW201324745A (zh
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莊學理
朱鳴
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台灣積體電路製造股份有限公司
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Description

CMOS半導體晶片
本發明係有關於半導體裝置，且特別是有關於一種具有虛置閘極區之CMOS半導體晶片。
隨著技術節點持續微縮，在某些積體電路設計中需以金屬閘極元件取代傳統多晶矽閘極元件，以在元件尺寸微縮時能一併增進裝置效能。“後閘極”製程係為一種形成金屬閘極元件之製程。在後閘極製程中，閘極係為“最後”製造的元件，因而可減少其後的製程步驟，例如可省略傳統製程中必需在閘極形成之後才進行的高溫處理步驟。
然而，目前在使用及製造互補式金氧半導體(CMOS)元件時仍面臨著許多問題，且在閘極長度及裝置之間的間距更加縮小時，將使這些問題更趨嚴重。例如，在“後閘極”製程中，金屬閘極元件的分佈不均導致在化學機械研磨(chemical mechanical polish)製程中有負載效應(loading effects)產生，而增加了裝置的不穩定性及/或甚至導致裝置失效。
本發明實施例係提供一種CMOS半導體晶片，包括：一基材；一絕緣層，位於此基材之一主要表面上；複數個P型金屬閘極區，形成於此絕緣層中，並覆蓋此主要表面之一第一區域；複數個N型金屬閘極區，形成於此絕緣層中，並覆蓋此主要表面之一第二區域，其中此第一區域相對於此第二區域具有一第一比例，且此第一比例大於或等於1；複數個虛置P型金屬閘極區，形成於此絕緣層中，並覆蓋此主要表面之一第三區域；以及複數個虛置N型金屬閘極區，形成於此絕緣層中，並覆蓋此主要表面之一第四區域，其中此第三區域相對於此第四區域具有一第二比例，且此第二比例實質上等於此第一比例。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
本發明接下來將會提供許多不同的實施例以實施本發明中不同的特徵。各特定實施例中的組成及配置將會在以下作描述以簡化本發明。這些實施例並非用於限定本發明。例如，當敘述一第一元件形成於一第二元件上時，可包含第一元件與第二元件直接接觸之實施例，或也可包含該第一元件與第二元件之間更有其他額外元件，而使該第一元件與第二元件無直接接觸之實施例。為了簡潔明瞭，圖式中之各種元件係以任意地尺寸繪示。此外，於本發明各實施例中，可能會有重複的參考標號及/或符號。然而，這些重複的參考標號及/或符號僅是為了簡潔表示，不代表在各個實施例及/或圖示之間有何特定的關連。再者，本發明雖僅提供了“後閘極”金屬閘極製程之實施例，但本領域具有通常知識者當可將其應用於其他製程及/或使用其他材料。
第1圖顯示依照本發明一實施例之互補式金氧半導體(complementary metal-oxide-semiconductor，以下簡稱為CMOS)晶片之製造方法100之流程圖。第2A圖顯示依照本發明一實施例之具有複數個獨立的CMOS晶片200之晶圓20之上視圖。第2B圖顯示第2A圖之晶圓20之部分的上視圖。第2C圖顯示依照第2A及2B圖之晶圓20中之其中一CMOS晶片200之部分的上視圖。第3A至3F圖顯示依照本發明一實施例，沿第2C圖之線段a-a於各種中間製造階段之剖面圖。值得注意的是，半導體晶片200可具有至少一部分由CMOS技術製程製造。因此，可知的是，可在第1圖所示之方法之前、之後或進行期間加入額外的製程，且某些製程亦會於本說明書中簡略提及。此外，第1至3F圖係已經簡化以使本發明之概念便於明瞭。例如，雖然圖式中僅顯示用於連接半導體晶片200之金屬閘極電極，但可知的是，半導體晶片200可為積體電路之一部分，且積體電路中尚包含許多其他裝置，例如電阻器、電容器、電感及熔絲等。
第2A圖顯示了由後閘極製程所製造之具有複數個獨立CMOS晶片200之晶圓20。第2B圖顯示晶圓20之其中一部分，晶圓20包含複數個半導體晶片200，且半導體晶片200包含各種導電區，例如包含第一導電區200a及第二導電區200b。
在一實施例中，半導體晶片200包含絕緣層224，其係形成於基材202之主要表面202上(顯示於第3A至3F圖)。第2C圖顯示在進行“後閘極”製程後之半導體晶片200之局部放大圖，其具有第一導電區200a及複數個導電結構(例如P型金屬閘極元件200p、N型金屬閘極元件200n、電阻元件200r等)設置於絕緣層224中。在半導體晶片200中，這些導電結構係與一或多個電子元件電性連接(例如，包含但不限於：電阻器、電容器、電感、電晶體或二極體，未顯示於此圖式中)，以連接至所欲的電路。
在本實施例中，P型金屬閘極元件200p包含P型金屬閘極區200pa、200pb、200pc及200pd，且N型金屬閘極結構200n包含N型金屬閘極區200na、200nb、200nc及200nd。P型金屬閘極區200pa、200pb、200pc、200pd位於絕緣層224中，並覆蓋主要表面202s的第一區域。N型金屬閘極區200na、200nb、200nc及200nd位於絕緣層224中，並覆蓋主要表面202s的第二區域，其中第一區域相對於第二區域具有一第一比例，且此第一比例大於或等於1。在一實施例中，第一比例介於1至3之間。
在某些實施例中，電阻元件200r包含複數個電阻區(在此同樣標號為200r)。這些電阻區200r位於絕緣層224中，並覆蓋主要表面202s之第五區域。在一實施例中，第五區域相對於第一區域及第二區域之總和具有一第三比例。此第三比例小於0.05。
第2C圖所示之部分的半導體晶片200亦包含第二導電區200b。第二導電區200b具有位於絕緣層224中之複數個虛置導電結構(例如虛置P型金屬閘極元件300p、虛置N型金屬閘極元件300n、虛置電阻元件300r等)。這些虛置導電結構係與半導體晶片200中之其他一或多個電子元件電性隔離(例如，包含但不限於：電阻器、電容器、電感、電晶體或二極體，未顯示於此圖式中)，以改善金屬閘極電極之不均勻分佈及形成所欲之電路。
在本實施例中，虛置P型金屬閘極元件300p包含複數個虛置P型金屬閘極區300pa、300pb、300pc、300pd、300pe、300pf及300pg。虛置N型金屬閘極結構300n包含包含複數個虛置N型金屬閘極區300na、300nb、300nc及300nd。在所述之實施例中，這些虛置P型金屬閘極區300pa、300pb、300pc、300pd、300pe、300pf及300pg形成於絕緣層224中，並覆蓋主要表面202s之第三區域。這些虛置N型金屬閘極區300na、300nb、300nc及300nd形成於絕緣層224中，並覆蓋主要表面202s之第四區域。第三區域相對於第四區域具有一第二比例，其實質上等同於第一比例。在一實施例中，第二比例為介於1至3。
在某些實施例中，電阻元件300r包含複數個電阻區(在此同樣標號為300r)。這些電阻區300r位於絕緣層224中且，並覆蓋主要表面202s之第六區域。在一實施例中，第六區域相對於第三區域及第四區域之總和具有一第四比例。此第四比例小於0.05。
在一實施例中，虛置N型金屬閘極區300pa、300pb、300pc、300pd、300pe、300pf及300pg之每一者皆具有近似圖案。在其他實施例中，虛置P型金屬閘極區300pa、300pb、300pc、300pd、300pe、300pf及300pg之每一者皆具有相似尺寸。
在某些實施例中，虛置N型金屬閘極區300na、300nb、300nc及300nd之每一者皆具有近似圖案。在其他實施例中，虛置N型金屬閘極區300na、300nb、300nc及300nd之每一者皆具有相似尺寸。
在某些實施例中，虛置P型金屬閘極區300pa、300pb、300pc、300pd、300pe、300pf及300pg之每一者相對於虛置N型金屬閘極區300na、300nb、300nc及300nd之每一者皆具有近似圖案。在某些實施例中，虛置P型金屬閘極區300pa、300pb、300pc、300pd、300pe、300pf及300pg之每一者相對於虛置N型金屬閘極區300na、300nb、300nc及300nd之每一者皆具有相似尺寸。
在某些實施例中，虛置N型金屬閘極區(例如300nc)之其中一者位於兩虛置P型金屬閘極區(例如300pb及300pd)之間。在某些實施例中，虛置P型金屬閘極區(例如300pc)之其中一者位於兩虛置N型金屬閘極區(例如300nb及300nd)之間。
在某些實施例中，虛置N型金屬閘極區(例如300nb)之其中一者位於一虛置P型金屬閘極區(例如300pb)及一P型金屬閘極區(例如200pb)之間。在某些實施例中，虛置P型金屬閘極區(例如300pc)之其中一者位於一虛置N型金屬閘極區(例如300nc)及一N型金屬閘極區(例如200nc)之間。
參見第1及3A圖，方法100起始於步驟102，其為提供一基材202，其中基材202包含主要表面202s、第一導電區200a及第二導電區200b。基材202可包含矽基材。或者，基材202可包含鍺化矽、砷化鎵或其他合適半導體材料。基材202可更包含其他元件，例如摻雜區、埋藏層及/或磊晶層。此外，基材202可為絕緣層上覆半導體，例如絕緣層上覆矽。在其他實施例中，基材202可包含摻雜磊晶層、梯度半導體層及/或可更包含半導體層上覆另一不同型態之半導體層，例如鍺化矽層上覆矽層。在其他實施例中，化合物半導體基材可包含多層矽結構，或矽基材可包含多層化合物半導體結構。
在所述之實施例中，基材202上可形成絕緣區，例如淺溝槽隔離，以定義各主動區並使其彼此電性隔離。絕緣區可包含例如氧化矽、氮化矽、氮氧化矽、氟摻雜矽玻璃、低介電常數介電材料及/或前述之組合等材料。淺溝槽隔離可由任意合適製程形成。在一實施例中，淺溝槽隔離之形成步驟可包含：以微影蝕刻製程圖案化半導體基材；於基材中蝕刻溝槽(例如使用乾蝕刻、濕蝕刻及/或電漿蝕刻製程)及以介電材料填充溝槽(例如藉由化學氣相沉積製程)。在某些實施例中，經填充的溝槽可具有多層結構，例如氮化矽或氧化矽可覆蓋於熱氧化襯層上。
在一實施例中，第一導電區200a包含第一淺溝槽隔離204a及第二淺溝槽隔離204b，其中第二淺溝槽隔離204b係將P型主動區206p及N型主動區206n相互隔離。在另一實施例中，第二主動區200b包含第三淺溝槽隔離304b及第四淺溝槽隔離304a，其中第三淺溝槽隔離304b係將P型主動區306p及N型主動區306n相互隔離。在又一實施例中，第二導電區200b可完全包含一淺溝槽隔離(圖中未顯示)。
再者，P型主動區206p、306p及N型主動區206n、306n可包含各種摻雜組態以滿足各種設計需求。例如，P型主動區206p、306p係具有n型摻雜，例如摻雜磷或砷；N型主動區206n、306n係具有p型摻雜，例如摻雜硼或二氟化硼。在所述之實施例中，P型主動區206p、306p可作為P型金氧半場效電晶體區(亦稱為PMOSFET區)，N型主動區206n、306n可作為N型金氧半場效電晶體區(亦稱為NMOSFET區)。
接著，繼續進行方法100之步驟104，形成複數個虛置閘極電極210(包含210p、210n、210r、310p、310n、310r)於主要表面202s上之絕緣層224中，形成如第3b圖所示之結構。在所述之實施例中，某些虛置閘極電極210p、210n及210r位於第一導電區200a中。某些虛置閘極電極310p、310n及310r位於第二導電區200b中。在某些實施例中，虛置閘極電極210之第一支組(subset)210p及310p係形成於P型主動區206p、306p上。虛置閘極電極210之第二支組210n及310n係形成於N型主動區206n、306n上。在某些實施例中，虛置閘極電極210之第三支組210r及310r係形成於淺溝槽隔離204a、304a上。此外，虛置閘極電極210r可包含第一部分210ra、第二部分210rb及位於第一部分210ra及第二部分210rb之間的第三部分210rc。
在所述之實施例中，閘極介電層212形成於基材202上。在某些實施例中，閘極介電層212可包含氧化矽、氮化矽、氮氧化矽、或高介電常數介電材料。高介電常數介電材料可包含金屬氧化物，例如Li、Be、Mg、Ca、Sr、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb或Lu之氧化物或前述之混合物。在本實施例中，閘極介電層212可包含厚度10至30之氧化鉿。閘極介電層212可由合適之製程形成，例如原子層沉積、化學氣相沉積、物理氣相沉積、熱氧化法、紫外光-臭氧氧化法(UV-ozone oxidation)或前述之組合。閘極介電層212可更包含界面層(未顯示)，以減少閘極介電層212及基材202之間的損傷。界面層可包含氧化矽。
接著，可於閘極介電層212上沉積TiN層214，以防止或減少鋁原子自N型金屬閘極電極擴散至閘極介電層212。此外，TiN層214亦可作為電阻器之一部分。在所述之實施例中，TiN層214之厚度為約5至15，其可由化學氣相沉積、物理氣相沉積或其他合適製程形成。
在後閘極製程中，隨後形成虛置閘極電極216於TiN層214上。在某些實施例中，虛置閘極電極216可包含單層結構或多層結構。在本實施例中，虛置閘極電極216可包含經均勻摻雜或梯度摻雜之多晶矽。此外，虛置閘極電極216之厚度可介於約30 nm至約60 nm之間。虛置閘極電極216可由低壓化學氣相沉積(low-pressure CVD，LPCVD)或電漿增強式化學氣相沉積(plasma-enhanced CVD，PECVD)形成。
接著，圖案化虛置閘極電極216、TiN層214及閘極介電層212，以形成如第3B圖所示之結構。光阻層可藉由例如旋轉塗佈之合適製程形成於虛置閘極電極216上，並藉由合適之微影蝕刻方法作圖案化，以於虛置閘極電極216上形成圖案化的光阻元件。光阻元件之寬度可介於約10至45 nm。接著，可使用乾蝕刻製程將圖案化的光阻元件之圖案轉移至其下方之膜層(即閘極介電層212、TiN層214及虛置閘極電極216)，以形成複數個虛置閘極電極210。隨後，可將光阻層剝除。
值得注意的是，CMOS半導體晶片200可進行其他“後閘極製程”及其他CMOS技術製程以形成CMOS半導體晶片200中之各種元件。在此，將簡述上述之各種元件。在“後閘極”製程中，CMOS半導體晶片200中之各種元件可在形成P型金屬閘極元件及N型金屬閘極元件之前形成。這些元件可包含形成於主動區206p、206n、306p及306n中的輕摻雜源/汲極區(P型及N型LDD)及源/汲極區(P型及N型源/汲極區)(未顯示)。P型輕摻雜源/汲極區及P型源/汲極區可摻雜有硼或銦。N型輕摻雜源/汲極區及N型源/汲極區可摻雜有磷或砷。或者，這些元件亦可包含環繞這些虛置閘極電極210之閘極間隔物222及絕緣層224。在所述之實施例中，閘極間隔物222可由氧化矽、氮化矽或其他合適材料形成。絕緣層224可由以高深寬比填溝製程(high-aspect-ratio-process，HARP)及/或高密度電漿(high-density-plasma，HDP)沉積製程形成之氧化物形成。
上述之製程可用以提供複數個位於基材202之主要表面202s上之絕緣層224中的複數個虛置閘極電極210。保護某些虛置閘極電極210p及210r並同時移除其他虛置閘極電極210n、310p、310n及310r，可在虛置閘極電極210n、310p、310n及310r之原處形成複數個金屬閘極元件。易言之，N型金屬閘極元件可形成在虛置閘極電極210n的位置，複數個虛置N型金屬閘極可形成於虛置金屬閘極電極310p、310n及310r所在之處。接著，移除虛置金屬閘極210p，以使P型金屬閘極元件能形成於虛置金屬閘極電極210p所在之處。因此，在後閘極製程中，在進行化學機械研磨的期間，不同金屬閘極元件(亦即，P型金屬閘極元件及N型金屬閘極元件)之不均勻分布導致承載效應(loading effects)，因而增加裝置不穩定性及失效的可能。
因此，接下來依據第3C至3F圖可藉由控制閘極區域的比例最佳化不同金屬閘極電極之分佈。不同金屬閘極電極的最佳化分佈對於防止後閘極製程中化學機械研磨的摻載效應有更佳的效果。因此，申請人在所提出之CMOS半導體晶片之製造方法可幫助不同金屬閘極電極維持其一致性，因而增進CMOS的效能。
接著，繼續進行方法100之步驟106，移除複數個虛置閘極電極210之第一支組(即210p及310p)以形成第一組開口208p、308p，及視需要移除虛置閘極電極210r之第一部分210ra及第二部分210rb以形成第三組開口208a、208b，形成如第3C圖所示之結構。在所述之實施例中，可使用圖案化光阻層作為罩幕，移除複數個虛置閘極電極210之第一支組(即210p及310p)以形成第一組開口208p、308p及移除虛置閘極電極210r之第一部分210ra及第二部分210rb以形成第三組開口208a、208b。同時，虛置閘極電極210n、310n、310r及虛置閘極電極210r之第三部分係由圖案化光阻層400覆蓋保護。
在一實施例中，可使用乾蝕刻製程移除複數個虛置閘極電極210之第一支組(即210p及310p)及虛置閘極電極210r之第一部分210ra及第二部分210rb。在一實施例中，乾蝕刻製程可在約650至800W之電源功率、約100至120W之偏壓功率及約60至200 mTorr之壓力下進行，並可使用Cl2、HBr及He作為蝕刻氣體。隨後，可將圖案化光阻層400予以移除。
接著，繼續進行方法100之步驟108，以第一金屬材料218p填充第一組開口208p、308p，以形成複數個閘極元件200p、300p(亦即第2C圖中之P型金屬閘極區200pb及虛置P型金屬閘極區300pb)，形成如第3D圖所示之結構。在一實施例中，P型功函數金屬包含一金屬，其係擇自於由氮化鈦、氮化鎢、氮化鉭及釕所組成的群組、化學氣相沉積或其他合適技術形成。在本實施例中，首先沉積第一金屬材料218p以實質上填滿第一組開口208p及308p及第三組開口208a及208b。接著，進行化學機械研磨製程，以移除部分溢於第一組開口208p及308p及第三組開口208a及208b外之第一金屬材料218p。因此，化學機械研磨製程可在達到絕緣層224時停止，並因而提供平坦表面。
接著，參見第3D圖，以第一金屬材料218p填充第三組開口208a及208b，以形成含複數個電阻區200r之電阻元件200r之導電接觸點。在一實施例中，這些金屬區200r包含多晶矽216。在另一實施例中，這些電阻區200r包含TiN 214。再者，虛置電阻元件300r包含複數個虛置電阻區300r。在一實施例中，這些虛置電阻區300r包含多晶矽。在另一實施例中，這些虛置電阻區300r包含TiN層214。
接著，繼續進行方法100之步驟110，移除這些虛置閘極電極210之第二支組(即210n及310n)以形成第二組開口208n、308n。在所述之實施例中，使用圖案化光阻層500作為罩幕，移除這些虛置閘極電極210之第二支組(即210n及310n)以形成第二組開口208n、308n。同時，虛置閘極電極310r及虛置閘極電極210r之第三部分210rc係由圖案化光阻層500所覆蓋保護。
在一實施例中，可使用乾蝕刻製程移除複數個虛置閘極電極210之第二支組(即210n及310n)。在一實施例中，乾蝕刻製程可在約650至800W之電源功率、約100至120W之偏壓功率及約60至200 mTorr之壓力下進行，並可使用Cl2、HBr及He作為蝕刻氣體。隨後，可將圖案化光阻層500予以移除。
接著，繼續進行方法100之步驟112，以第二金屬材料218n填充第二組開口208n及308n，以形成複數個N型金屬閘極元件200n、300n(亦即第2C圖中之N型金屬閘極區200nb及虛置N型金屬閘極區300nb)。在一實施例中，第二金屬材料218n可包含N型功函數金屬。在某些實施例中，N型功函數金屬可包含一金屬，其係擇自於由鈦、銀、鋁、鋁化鈦、氮鋁化鈦、碳化鉭、氮碳化鉭、氮矽化鉭、錳及鋯所組成的群組。N型功函數金屬可由原子層沉積、物理氣相沉積、濺鍍或其他合適技術形成。在本實施例中，首先沉積第二金屬材料218r以實質上填滿第二組開口208n及308n。接著，進行化學機械研磨製程以移除部分溢於第二組開口208n及308n外之第二金屬材料218n。因此，因此，化學機械研磨製程可在達到絕緣層224時停止，並因而提供平坦表面。
第4A及4B圖顯示依照本發明第2A及2B圖所示之實施例之晶圓中之CMOS半導體晶片之部分的上視圖。在所述之實施例中，第二導電區200b具有複數個位於絕緣層224中之虛置導電結構，例如虛置P型金屬閘極元件300p、虛置N型金屬閘極元件300n等。虛置P型金屬閘極區300p及虛置N型金屬閘極區300n之每一者皆具有相似形狀及尺寸。然而，虛置P型金屬閘極區300p及虛置N型金屬閘極區300n的分佈亦可作變化。
第5A及5B圖顯示依照本發明第2A及2B圖所示之實施例之晶圓中之CMOS半導體晶片之部分的上視圖。在所述之實施例中，第二導電區200b具有複數個虛置導電結構(例如，虛置P型金屬閘極元件300p、虛置N型金屬閘極元件300n等)設置於絕緣層224中，其中虛置P型金屬閘極區300p之每一者相對於虛置N型金屬閘極區300n之每一者皆具有不同的形狀及尺寸。然而，虛置P型金屬閘極區300p及虛置N型金屬閘極區300n的分佈亦可作變化。
可知的是，可對CMOS半導體晶片200進行更進一步的CMOS製程，以形成各種元件，例如接觸點/通孔、內連線金屬層、介電層、保護層等。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
20．．．晶圓
200．．．半導體晶片
200a．．．第一導電區
200b．．．第二導電區
200n．．．N型金屬元件
200na．．．N型金屬閘極區
200nb．．．N型金屬閘極區
200nc．．．N型金屬閘極區
200nd．．．N型金屬閘極區
200p．．．P型金屬元件
200pa．．．P型金屬閘極區
200pb．．．P型金屬閘極區
200pc．．．P型金屬閘極區
200pd．．．P型金屬閘極區
200r．．．電阻元件
202．．．基材
202s．．．主要表面
204a．．．第一淺溝槽隔離
204b．．．第二淺溝槽隔離
206n．．．N型主動區
206p．．．P型主動區
208a．．．開口
208b．．．開口
208n．．．開口
208p．．．開口
210．．．虛置閘極電極
210n．．．虛置閘極電極
210p．．．虛置閘極電極
210r．．．虛置閘極電極
210ra．．．虛置閘極電極之第一部分
210rb．．．虛置閘極電極之第二部分
210rc．．．虛置閘極電極之第三部分
212．．．介電層
214．．．TiN層
216．．．虛置閘極電極
218n．．．N型閘極電極
218p．．．P型閘極電極
222．．．閘極間隔物
224．．．絕緣層
300n．．．N型金屬閘極元件
300p．．．P型金屬閘極元件
300na．．．N型金屬閘極區
300nb．．．N型金屬閘極區
300nc．．．N型金屬閘極區
300nd．．．N型金屬閘極區
300pa．．．P型金屬閘極區
300pb．．．P型金屬閘極區
300pc．．．P型金屬閘極區
300pd．．．P型金屬閘極區
300pe．．．P型金屬閘極區
300pf．．．P型金屬閘極區
300pg．．．P型金屬閘極區
300r．．．虛置電阻元件
304a．．．第三淺溝槽隔離
304b．．．第四淺溝槽隔離
306n．．．N型主動區
306p．．．P型主動區
308p．．．開口
310n．．．虛置閘極電極
310p．．．虛置閘極電極
310r．．．虛置閘極電極
400．．．圖案化光阻層
500．．．圖案化光阻層
第1圖顯示依照本發明一實施例之CMOS半導體晶片之製造方法。
第2A圖顯示依照本發明一實施例之具有複數個獨立CMOS晶片之晶圓之上視圖。
第2B圖顯示第2A圖所示之晶圓之其中一部分之上視圖。
第2C圖顯示第2A及第2B圖之晶圓中之半導體晶片之其中一者之部分的上視圖。
第3A-3F圖顯示依照本發明一實施例，沿第2C圖之線段a-a於各製造階段之剖面圖。
第4A及4B圖顯示第2A及2B圖之晶圓中之半導體晶片之其中一者於本發明一實施例中之部分的上視圖。
第5A及5B圖顯示第2A及2B圖之晶圓中之半導體晶片之其中一者於本發明另一實施例中之部分的上視圖。
200a．．．第一導電區
200b．．．第二導電區
200n．．．N型金屬元件
200na．．．N型金屬閘極區
200nb．．．N型金屬閘極區
200nc．．．N型金屬閘極區
200nd．．．N型金屬閘極區
200p．．．P型金屬元件
200pa．．．P型金屬閘極區
200pb．．．P型金屬閘極區
200pc．．．P型金屬閘極區
200pd．．．P型金屬閘極區
200r．．．電阻元件
300n．．．N型金屬閘極元件
300na．．．N型金屬閘極區
300nb．．．N型金屬閘極區
300nc．．．N型金屬閘極區
300nd．．．N型金屬閘極區
300p．．．P型金屬閘極元件
300pa．．．P型金屬閘極區
300pb．．．P型金屬閘極區
300pc．．．P型金屬閘極區
300pd．．．P型金屬閘極區
300pe．．．P型金屬閘極區
300pf．．．P型金屬閘極區
300pg．．．P型金屬閘極區
300r．．．虛置電阻元件

Claims (10)

  1. 一種CMOS半導體晶片，包括：一基材；一絕緣層，位於該基材之一主要表面上；複數個P型金屬閘極區，形成於該絕緣層中，並覆蓋該主要表面之一第一區域；複數個N型金屬閘極區，形成於該絕緣層中，並覆蓋該主要表面之一第二區域，其中該第一區域相對於該第二區域具有一第一比例，且該第一比例大於或等於1；複數個虛置P型金屬閘極區，形成於該絕緣層中，並覆蓋該主要表面之一第三區域；以及複數個虛置N型金屬閘極區，形成於該絕緣層中，並覆蓋該主要表面之一第四區域，其中該第三區域相對於該第四區域具有一第二比例，且該第二比例實質上等於該第一比例，其中該些虛置P型金屬閘極區包含一第一金屬材料，該些虛置N型金屬閘極區包含一第二金屬材料，且該第一金屬材料異於該第二金屬材料。
  2. 如申請專利範圍第1項所述之CMOS半導體晶片，其中該第一比例介於1至3之間。
  3. 如申請專利範圍第1項所述之CMOS半導體晶片，其中該些虛置P型金屬閘極區之每一者及/或該些虛置N型金屬閘極區之每一者皆具有相似形狀。
  4. 如申請專利範圍第1項所述之CMOS半導體晶片，其中該些虛置P型金屬閘極區之每一者及/或該些虛 置N型金屬閘極區之每一者皆具有相似尺寸。
  5. 如申請專利範圍第1項所述之CMOS半導體晶片，其中該些虛置N型金屬閘極區之其中一者位於兩虛置P型金屬閘極區之間。
  6. 如申請專利範圍第1項所述之CMOS半導體晶片，其中該些虛置P型金屬閘極區之其中一者位於兩虛置N型金屬閘極區之間。
  7. 如申請專利範圍第1項所述之CMOS半導體晶片，其中該些虛置N型金屬閘極區之其中一者位於該些虛置P型金屬閘極區之其中一者及該些P型金屬閘極區之其中一者之間。
  8. 如申請專利範圍第1項所述之CMOS半導體晶片，其中該些虛置P型金屬閘極區之其中一者位於該些虛置N型金屬閘極區之其中一者及該些N型金屬閘極區之其中一者之間。
  9. 如申請專利範圍第1項所述之CMOS半導體晶片，更包含：複數個電阻區形成於該絕緣層中，並覆蓋該主要表面之一第五區域；以及複數個虛置電阻區形成於該絕緣層中，並覆蓋該主要表面之一第六區域。
  10. 如申請專利範圍第9項所述之CMOS半導體晶片，其中該第五區域相對於該第一區域及該第二區域之總和具有一第三比例，且該第三比例小於0.05，其中該第六區域相對於該第三區域及該第四區域之總和具有一 第四比例，且該第四比例小於0.05。
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Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8735994B2 (en) * 2012-03-27 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical-free dummy gate
KR102311552B1 (ko) 2014-12-04 2021-10-12 삼성전자주식회사 반도체 소자 및 그 제조 방법
US9640438B2 (en) * 2014-12-30 2017-05-02 Globalfoundries Singapore Pte. Ltd. Integrated circuits with inactive gates and methods of manufacturing the same
US9530772B1 (en) * 2015-08-06 2016-12-27 International Business Machines Corporation Methods of manufacturing devices including gates with multiple lengths
US10431583B2 (en) 2016-02-11 2019-10-01 Samsung Electronics Co., Ltd. Semiconductor device including transistors with adjusted threshold voltages
US10103027B2 (en) * 2016-06-20 2018-10-16 Applied Materials, Inc. Hydrogenation and nitridization processes for modifying effective oxide thickness of a film
US10510545B2 (en) 2016-06-20 2019-12-17 Applied Materials, Inc. Hydrogenation and nitridization processes for modifying effective oxide thickness of a film
US10388576B2 (en) * 2016-06-30 2019-08-20 International Business Machines Corporation Semiconductor device including dual trench epitaxial dual-liner contacts
US20180337033A1 (en) * 2017-05-16 2018-11-22 Globalfoundries Inc. Novel approach to improve sdb device performance
US10727223B2 (en) * 2017-11-13 2020-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Thin film resistor
DE102018125043B4 (de) 2017-11-13 2023-01-19 Taiwan Semiconductor Manufacturing Co. Ltd. Neuartiger Dünnfilmwiderstand und Verfahren zu dessen Herstellung
CN110233151B (zh) * 2018-10-30 2021-10-01 上海权策微电子技术有限公司 一种cmos管及其制造方法
WO2020146030A1 (en) * 2019-01-09 2020-07-16 Applied Materials, Inc. Hydrogenation and nitridization processes for modifying effective oxide thickness of a film
US11257816B2 (en) * 2019-08-20 2022-02-22 Taiwan Semiconductor Manufacturing Co., Ltd. Method for manufacturing semiconductor device including dummy gate electrodes
WO2021150625A1 (en) 2020-01-23 2021-07-29 Applied Materials, Inc. Method of cleaning a structure and method of depositiing a capping layer in a structure
US20220037312A1 (en) * 2020-07-29 2022-02-03 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit device, method, layout, and system
CN117406547B (zh) * 2023-12-15 2024-04-05 合肥晶合集成电路股份有限公司 一种光罩的伪图形结构及光罩

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5384472A (en) * 1992-06-10 1995-01-24 Aspec Technology, Inc. Symmetrical multi-layer metal logic array with continuous substrate taps and extension portions for increased gate density
JP2689871B2 (ja) * 1993-11-10 1997-12-10 日本電気株式会社 ３値入力バッファ回路
US5907867A (en) * 1994-09-09 1999-05-25 Hitachi, Ltd. Translation lookaside buffer supporting multiple page sizes
JP3014025B2 (ja) * 1995-03-30 2000-02-28 日本電気株式会社 ＢｉＣＭＯＳ論理集積回路
JP2720816B2 (ja) * 1995-03-31 1998-03-04 日本電気株式会社 ＢｉＭＯＳ集積回路
JP2002198441A (ja) * 2000-11-16 2002-07-12 Hynix Semiconductor Inc 半導体素子のデュアル金属ゲート形成方法
JP3726760B2 (ja) * 2002-02-20 2005-12-14 セイコーエプソン株式会社 半導体装置の製造方法
US7554139B2 (en) 2004-04-30 2009-06-30 Panasonic Corporation Semiconductor manufacturing method and semiconductor device
JP2007250705A (ja) 2006-03-15 2007-09-27 Nec Electronics Corp 半導体集積回路装置及びダミーパターンの配置方法
US7678636B2 (en) * 2006-06-29 2010-03-16 Taiwan Semiconductor Manufacturing Company, Ltd. Selective formation of stress memorization layer
US20080076216A1 (en) * 2006-09-25 2008-03-27 Sangwoo Pae Method to fabricate high-k/metal gate transistors using a double capping layer process
JP2007311818A (ja) 2007-07-18 2007-11-29 Renesas Technology Corp 半導体装置
US7749822B2 (en) * 2007-10-09 2010-07-06 International Business Machines Corporation Method of forming a resistor and an FET from the metal portion of a MOSFET metal gate stack
US8125051B2 (en) * 2008-07-03 2012-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Device layout for gate last process
US8237227B2 (en) * 2008-08-29 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy gate structure for gate last process
JP5586628B2 (ja) * 2008-11-17 2014-09-10 イントリンシツク・イー・デー・ベー・ベー 分散ｐｕｆ
US8321828B2 (en) 2009-02-27 2012-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy fill to reduce shallow trench isolation (STI) stress variation on transistor performance
US8193900B2 (en) * 2009-06-24 2012-06-05 United Microelectronics Corp. Method for fabricating metal gate and polysilicon resistor and related polysilicon resistor structure
US8890260B2 (en) * 2009-09-04 2014-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Polysilicon design for replacement gate technology
US10026656B2 (en) 2011-12-06 2018-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate features of semiconductor die

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CN103151353B (zh) 2016-06-29
US20150194352A1 (en) 2015-07-09
US20160093610A1 (en) 2016-03-31
US20130140641A1 (en) 2013-06-06
CN103151353A (zh) 2013-06-12
TW201324745A (zh) 2013-06-16
KR20130063443A (ko) 2013-06-14
US9006860B2 (en) 2015-04-14
US9209090B2 (en) 2015-12-08
US9515069B2 (en) 2016-12-06
KR101338664B1 (ko) 2013-12-06
US20170084608A1 (en) 2017-03-23
US10672760B2 (en) 2020-06-02

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