CN103151353B - 半导体管芯的金属栅极部件 - Google Patents
半导体管芯的金属栅极部件 Download PDFInfo
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- CN103151353B CN103151353B CN201210107453.5A CN201210107453A CN103151353B CN 103151353 B CN103151353 B CN 103151353B CN 201210107453 A CN201210107453 A CN 201210107453A CN 103151353 B CN103151353 B CN 103151353B
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- ITWBWJFEJCHKSN-UHFFFAOYSA-N 1,4,7-triazonane Chemical compound C1CNCCNCCN1 ITWBWJFEJCHKSN-UHFFFAOYSA-N 0.000 claims description 3
- 229910004200 TaSiN Inorganic materials 0.000 claims description 3
- 229910010038 TiAl Inorganic materials 0.000 claims description 3
- 229910010037 TiAlN Inorganic materials 0.000 claims description 3
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- 229910003468 tantalcarbide Inorganic materials 0.000 claims description 3
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- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
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- 229910052731 fluorine Inorganic materials 0.000 description 1
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- 229910052746 lanthanum Inorganic materials 0.000 description 1
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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Abstract
CMOS半导体管芯包括:衬底;绝缘层,位于衬底的主面的上方;多个P金属栅极区域,形成在绝缘层内,总体覆盖主面的第一区域;多个N金属栅极区域,形成在绝缘层内,总体覆盖主面的第二区域,其中,第一区域与第二区域的第一比率等于或大于1;多个伪P金属栅极区域,形成在绝缘层内,总体覆盖主面的第三区域;以及多个伪N金属栅极区域,形状在绝缘层内,总体覆盖主面的第四区域,其中,第三区域与第四区域的第二比率基本上等于第一比率。本发明还提供了半导体管芯的金属栅极部件。
Description
技术领域
本发明内容的一个或多个实施例涉及集成电路制造,更具体地来说,涉及具有金属栅极部件的半导体管芯。
背景技术
随着技术节点的缩小,在一些集成电路(IC)设计中,期望使用金属栅极部件来代替通常的多晶硅栅极部件,以通过减小的部件尺醇来提高器件性能。形成金属栅极部件的一个工艺被称为“后栅极”工艺,其中,“最后”制造最终的栅极部件,这允许减少后续工艺的数量,包括必须在形成栅极之后实施的高温工艺。
然而,在互补金属氧化物半导体(CMOS)制造中实施这种部件和工艺存在调整。随着栅极长度和器件之间的间隔的减小,这些问题更加严重。例如,在“后栅极”制造工艺中,金属栅极部件的不均匀分布在化学机械抛光(CMP)工艺期间引起负载效应,从而增加了器件不稳定和/或器件故障的可能性。
发明内容
为了解决现有技术中所存在的缺陷,根据本发明提供了一种CMOS半导体管芯,包括:衬底;绝缘层,位于所述衬底的主面的上方;多个P金属栅极区域,形成在所述绝缘层内,总体覆盖所述主面的第一区域;多个N金属栅极区域,形成在所述绝缘层内,总体覆盖所述主面的第二区域,其中,所述第一区域与所述第二区域的第一比率等于或大于1;多个伪P金属栅极区域,形成在所述绝缘层内,总体覆盖所述主面的第三区域;以及多个伪N金属栅极区域,形成在所述绝缘层内,总体覆盖所述主面的第四区域,其中,所述第三区域与所述第四区域的第二比率基本上等于所述第一比率。
在该CMOS半导体管芯中,所述第一比率在1至3的范围内。
在该CMOS半导体管芯中,所述第二比率在1至3的范围内。
在该CMOS半导体管芯中,所述多个伪P金属栅极区域的每一个都具有与其他伪P金属栅极区域类似的形状。
在该CMOS半导体管芯中,所述多个伪N金属栅极区域的每一个都具有与其他伪N金属栅极区域类似的形状。
在该CMOS半导体管芯中,所述多个伪P金属栅极区域的每一个都具有与所述多个伪N金属栅极区域的每一个类似的形状。
在该CMOS半导体管芯中,所述多个伪P金属栅极区域的每一个的大小类似。
在该CMOS半导体管芯中,所述多个伪N金属栅极区域的每一个的大小类似。
在该CMOS半导体管芯中,所述多个伪P金属栅极区域的每一个都具有与所述多个伪N金属栅极区域的每一个类似的大小。
在该CMOS半导体管芯中,所述多个伪N金属栅极区域的一个位于两个伪P金属栅极区域之间。
在该CMOS半导体管芯中,所述多个伪P金属栅极区域的一个位于两个伪N金属栅极区域之间。
在该CMOS半导体管芯中,所述多个伪N金属栅极区域的一个位于所述伪P栅极区域中的一个和所述多个P金属栅极区域中的一个之间。
在该CMOS半导体管芯中,所述多个伪P金属栅极区域的一个位于所述伪N栅极区域中的一个和所述多个N金属栅极区域中的一个之间。
在该CMOS半导体管芯中,所述多个伪P金属栅极区域包括从由TiN、WN、TaN和Ru组成的组中所选择的金属。
在该CMOS半导体管芯中,所述多个伪N金属栅极区域包括从由Ti、Ag、Al、TiAl、TiAlN、TaC、TaCN、TaSiN、Mn和Zr组成的组中所选择的金属。
该CMOS半导体管芯还包括:多个电阻器区域,形成在所述绝缘层内,总体覆盖所述主面的第五区域,以及多个伪电阻器区域,形成在所述绝缘层内,总体覆盖所述主面的第六区域。
在该CMOS半导体管芯中,所述第五区域与所述第一区域和所述第二区域的总和的第三比率小于0.05。
在该CMOS半导体管芯中,所述第六区域与所述第三区域和所述第四区域的总和的第四比率小于0.05。
在该CMOS半导体管芯中,所述多个伪电阻器区域包括多晶硅。
在该CMOS半导体管芯中,所述多个伪电阻器区域包括TiN。
附图说明
当接合附图进行阅读时,根据以下详细描述更好地理解本发明内容。应该强调的是,根据工业的标准实践,各种部件没有按比例绘制并且仅用于说明的目的。实际上,为了讨论的清楚,可以任意增加或减小各种部件的尺寸。
图1是示出根据本发明内容的各个方面的制造CMOS半导体管芯的方法的流程图;
图2A示出了根据本发明内容的各个方面的具有多个独立CMOS半导体管芯的示例性晶圆的俯视图;
图2B示出了根据本发明内容的实施例的各个方面的图2A的示例性晶圆的一部分的俯视图;
图2C示出了根据本发明内容的各个方面的图2A和图2B的示例性晶圆中的一个CMOS半导体管芯的一部分的俯视图;
图3A至图3F示出了根据本发明内容的各个方面的处于各个制造阶段的沿着图2C的线a-a截取的截面图;
图4A至图4B示出了根据本发明内容的各个方面的图2A和图2B的示例性晶圆中的一个CMOS半导体管芯的一部分的俯视图;以及
图5A至图5B示出了根据本发明内容的各个方面的图2A和图2B的示例性晶圆中的一个CMOS半导体管芯的一部分的俯视图。
具体实施方式
应该理解,以下发明内容提供了用于实施本发明内容的不同特征的许多不同的实施例或实例。以下描述部件和配置的具体实例以简化本发明内容。当然,这些仅仅是实例而不用于限制。例如,以下描述中第一部件形成在第二部件上方可以包括以直接接触的方式形成第一部件和第二部件的实施例,并且还可以包括可以形成额外部件介于第一部件和第二部件之间使得第一部件和第二部件没有直接接触的实施例。为了简化和清楚,以不同的比例任意绘制各个部件。此外,本发明内容可以在各个实例中重复参考标号和/或字母。这种重复是为了简化和清楚的目的,其本身没有指定表示所讨论的各个实施例和/或结构之间的关系。此外,本发明内容提供了“后栅极”金属栅极工艺的实例,然而,本领域的技术人员可以意识到其他工艺和/或使用其他材料的适用性。
图1是示出根据本发明内容的各个方面的制造互补金属氧化物半导体(CMOS)半导体管芯的方法100的流程图。图2A示出了根据本发明内容的各个方面的具有多个独立CMOS半导体管芯200的示例性晶圆20的俯视图;图2B示出了根据本发明内容的各个方面的图2A的示例性晶圆20的一部分的俯视图;图2C示出了根据本发明内容的各个方面的图2A和图2B的示例性晶圆20中的一个CMOS半导体管芯200的一部分的俯视图;以及图3A至图3F示出了根据本发明内容的各个方面的处于各个制造阶段的沿着图2C的线a-a截取的截面图。注意,可以利用CMOS技术工艺制造半导体管芯200的部分。因此,应该理解,可以在图1的方法100之前、之间和之后提供额外工艺,并且可以在本文中仅简要描述一些其他工艺。此外,简化了图1至图3F以更好地理解本发明内容的概念。例如,尽管附图示出了用于半导体管芯200的金属栅电极,但应该理解,半导体管芯200可以为包括多个其他器件(包括电阻器、电容器、电感器、熔丝等)的集成电路(IC)的一部分。
图2A示出了具有通过“后栅极”工艺制造的多个独立CMOS半导体管芯200的示例性晶圆20。图2B示出了包括示例性半导体管芯200的图2A的示例性晶圆20的一部分,其中,半导体管芯200包括多个导电区域,多个导电区域包括第一导电区域200a和第二导电区域200b。
在一个实施例中,半导体管芯200包括位于衬底202的主面202s上方的绝缘层224(图3A至图3F所示)。图2C示出了在“后栅极”工艺以后的半导体管芯200的一部分,从而形成在绝缘层224内具有多个导电结构(例如,P金属栅极部件200p、N金属栅极部件200n、电阻器部件200r等)的第一导电区域200a。多个导电结构与半导体管芯200中的一个或多个电子元件(例如,包括但不限于电阻器、电容器、电感器、晶体管、二极管等,未示出)电耦合,用于将这些部件互连以形成期望电路。
在本实施例中,P金属栅极部件200p包括多个P金属栅极区域200pa、200pb、200pc和200pd,而N金属栅极部件200n包括多个N金属栅极区域200na、200nb、200nc和200nd。在所示实施例中,形成在绝缘层224内的多个P金属栅极区域200pa、200pb、200pc和200pd总体覆盖主面202s的第一区域,而形成在绝缘层224内的多个N金属栅极区域200na、200nb、200nc和200nd总体覆盖主面202s的第二区域,其中,第一区域和第二区域的第一比率等于或大于1。在一个实施例中,第一比率在1至3的范围内。
在一些实施例中,电阻器部件200r包括形成在绝缘体层224内的多个电阻器区域(也称为200r),总体覆盖主面202s的第五区域。在一个实施例中,第五区域与第一区域和第二区域的总和的第三比率小于0.05。
图2C中的半导体管芯200的所示部分还包括第二导电区域200b,第二导电区域200b在绝缘层224内具有多个伪导电结构(例如,伪P金属栅极部件300p、伪N金属栅极部件300n、伪电阻器部件300r等)。多个伪导电结构与半导体管芯200中的一个或多个电子部件(例如,包括但不限于电阻器、电容器、电感器、晶体管、二极管等,未示出)电隔离,用于改善金属栅电极的不均匀分布,从而形成期望电路。
在本实施例中,伪P金属栅极部件300p包括多个伪P金属栅极区域300pa、300pb、300pc、300pd、300pe、300pf和300pg,而伪N金属栅极部件300n包括多个伪N金属栅极区域300na、300nb、300nc和300nd。在所示实施例中,形成在绝缘层224内的多个伪P金属栅极区域300pa、300pb、300pc、300pd、300pe、300pf和300pg总体覆盖主面202s的第三区域,而形成在绝缘层224内的多个伪N金属栅极区域300na、300nb、300nc和300nd总体覆盖主面202s的第四区域,其中,第三区域与第四区域的第二比率基本上等于第一比率。在一个实施例中,第二比率在1至3的范围内。
在一些实施例中,伪电阻器部件300r包括形成在绝缘体层224内的多个伪电阻器区域(也称为300r),多个伪电阻器区域总体覆盖主面202s的第六区域。在一个实施例中,第六区域与第三区域和第四区域的总和的第四比率小于0.05。
在一个实施例中,多个伪P金属栅极区域300pa、300pb、300pc、300pd、300pe、300pf和300pg的每一个都具有与其他伪P金属栅极区域300pa、300pb、300pc、300pd、300pe、300pf和300pg类似的形状。在另一实施例中,多个伪P金属栅极区域300pa、300pb、300pc、300pd、300pe、300pf和300pg的每一个的大小类似。
在一个实施例中,多个伪N金属栅极区域300na、300nb、300nc和300nd的每一个都具有与其他伪N金属栅极区域300na、300nb、300nc和300nd类似的形状。在另一实施例中,多个伪N金属栅极区域300na、300nb、300nc和300nd的每一个的大小类似。
在一个实施例中,多个伪P金属栅极区域300pa、300pb、300pc、300pd、300pe、300pf和300pg的每一个都具有与多个伪N金属栅极区域300na、300nb、300nc和300nd类似的形状。在一些实施例中,多个伪P金属栅极区域300pa、300pb、300pc、300pd、300pe、300pf和300pg的每一个都具有与多个伪N金属栅极区域300na、300nb、300nc和300nd的每个类似的大小。
在一些实施例中,多个伪N金属栅极区域300na、300nb、300nc和300nd中的一个(例如,300nc)在两个伪P金属栅极区域(例如,300pb和300pd)之间。在一些实施例中,多个伪P金属栅极区域300pa、300pb、300pc、300pd、300pe、300pf和300pg中的一个(即,300pc)在两个伪N金属栅极区域(例如,300nb和300nd)之间。
在一些实施例中,多个伪N金属栅极区域中的一个(例如,300nb)在伪P金属栅极区域(例如,300pb)的一个和多个P金属栅极区域中的一个(例如,200pc)之间。在一些实施例中,多个伪P金属栅极区域中的一个(例如,300pc)在伪N金属栅极区域中一个(例如,300nc)和多个N金属栅极区域中的一个(例如,200nc)之间。
参考图1和图3A,方法100开始于步骤102,提供包括主面202s的衬底202,其中,衬底202包括第一导电区域200a和第二导电区域200b。衬底202可以包括硅衬底。衬底202可以可选地包括硅锗、砷化镓或其他适当的半导体材料。衬底202可以进一步包括其他部件,诸如各种掺杂区域、埋入层和/或外延(epi)层。此外,衬底202可以为绝缘体上半导体,诸如绝缘体上硅(SOI)。在其他实施例中,半导体衬底202可以包括掺杂外延层、梯度半导体层和/或可以进一步包括覆盖不同类型的另一半导体层的半导体层,诸如硅锗层上的硅层。在其他实例中,化合物半导体衬底可以包括多层硅结构,或者硅衬底可也包括多层化合物半导体结构。
在所示实施例中,诸如浅沟槽隔离(STI)的隔离区域可以形成在衬底202上方以限定各个有源区域并使各个有源区域相互隔离。隔离区域可以包括诸如氧化硅、氮化硅、氮氧化硅、掺氟的硅酸盐玻璃(FSG)、低k介电材料和/或其组合的材料。STI可以通过任何适当的工艺来形成。作为一个实例,STI的形成可以包括:通过光刻工艺图案化半导体衬底,在衬底中蚀刻沟槽(例如,通过使用干蚀刻、湿蚀刻和/或等离子体蚀刻工艺),以及利用介电材料填充沟槽(例如,通过使用化学汽相沉积工艺)。在一些实施例中,填充的沟槽可以具有多层结构,诸如填充有氮化硅或氧化硅的热氧化物衬里层。
在一个实施例中,第一导电区域200a包括第一STI204a和第二STI204b,其中,第二STI204b使P有源区域206p和N有源区域206n隔离。在另一实施例中,第二导电区域200b包括第三STI304b和第四STI304a,其中,第三STI304b使P有源区域306p和N有源区域306n隔离。在又一实施例中,第二导电区域200b可以完全包括STI(未示出)。
此外,P有源区域206p、306p和N有源区域206n、306n可以根据设计要求包括各种掺杂结构。例如,P有源区域206p、306p掺杂有诸如磷或砷的n型掺杂剂;N有源区域206n、306n可以掺杂有诸如硼或BF2的p型掺杂剂。在所示实施例中,P有源区域206p、306p可以用作被配置成用于p型金属氧化物半导体场效应晶体管(称为pMOSFET)的区域;N有源区域206n、306n可以用作被配置成用于n型金属氧化物半导体场效应晶体管(称为nMOSFET)的区域。
方法100继续到步骤104,其中,通过在位于衬底202的主面202s的上方的绝缘层224内形成多个伪栅电极210(表示为210p、210n、210r、310p、310n和310r)来制造图3B中的结构。在所示实施例中,一些伪栅电极210p、210n和210r位于第一导电区域200a中,而一些伪栅电极310p、310n和310r位于第二导电区域200b中。在一些实施例中,伪栅电极210的第一子集(例如,210p和310p)形成在P有源区域206p、306p的上方,而伪栅电极210的第二子集(例如,210n和310n)形成在N有源区域206n、306n的上方。在一些实施例中,伪栅电极210的第三子集(例如,210r和310r)形成在STI204a、304a的上方。此外,伪栅电极210r可以包括:第一部分210ra、第三部分210rc以及第一部分210ra和第三部分210rc之间的第二部分210rb。
在所示实施例中,栅极介电层212形成在衬底202的上方。在一些实施例中,栅极介电层212可以包括氧化硅、氮化硅、氮氧化硅或高k电介质。高k电介质包括特定的金属氧化物。用于高k电介质的金属氧化物的实例包括:Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu和其混合物的氧化物。在本实施例中,栅极介电层212为包括HfOx的高k介电层,其中,栅极介电层的厚度在大约10至30埃之间的范围内。栅极介电层212可以使用适当的工艺来形成,诸如原子层沉积(ALD)、化学汽相沉积(CVD)、物理汽相沉积(PVD)、热氧化、UV臭氧氧化或其组合。栅极介电层212可以进一步包括界面层(未示出),以降低栅极介电层212和衬底202之间的损伤。界面层可以包括氧化硅。
然后,TiN层214沉积在栅极介电层212的上方,以减少N金属栅电极到栅极介电层212的Al原子扩散。TiN层214还可以用作电阻器的一部分。在所示实施例中,TiN层214的厚度在5至15埃范围内。TiN层214可以通过CVD、PVD或其他适当的技术来形成。
在后栅极工艺中,伪栅电极216随后形成在TiN层214的上方。在一些实施例中,伪栅电极216可以包括单层或多层结构。在本实施例中,伪栅电极216可包括多晶硅。此外,伪栅电极216可以为具有均匀掺杂或梯度掺杂的掺杂多晶硅。伪栅电极216的厚度可以在大约30nm至大约60nm的范围内。伪栅电极216可以使用低压化学汽相沉积(LPCVD)工艺或等离子体增强化学汽相沉积(PECVD)工艺来形成。
然后,图案化伪栅电极216、TiN层214和栅极介电层212,以制造图3B中所示的结构。通过适当的工艺(诸如旋涂)在伪栅电极216的上方形成光刻胶层(未示出),并且通过适当的光刻图案化工艺图案化该光刻胶层,以在伪栅电极216的上方形成图案化光刻胶部件。图案化光刻胶部件的宽度在大约10至45nm的范围内。然后,图案化光刻胶部件可以使用干蚀刻工艺转印到下面的层(即,栅极介电层212、TiN层214和伪栅电极216),以形成多个伪栅电极210。此后可以剥离光刻胶层。
注意,CMOS半导体管芯200可以经受其他“后栅极”工艺和其他CMOS技术工艺,以形成CMOS半导体管芯200的各个部件。如此,本文仅简要讨论各个部件。在“后栅极”工艺中,可以在形成P金属栅极部件和N金属栅极部件之前,形成CMOS半导体管芯200的各个元件。各个元件可以在有源区域206p、206n、306p和306n中包括轻掺杂源极/漏极区域(p型和n型LDD)和源极/漏极区域(p型和n型S/D)(未示出)。p型LDD和S/D区域可以掺杂有B或In,并且n型LDD和S/D区域可以掺杂有P或As。各种部件可以进一步包括环绕多个伪栅电极210的栅极隔离件222和绝缘层224。在所示实施例中,栅极隔离件222可以由氧化硅、氮化硅或其他适当材料形成。绝缘层224可以包括通过高纵横比工艺(HARP)和/或高密度等离子体(HDP)沉积工艺形成的氧化物。
至此的工艺步骤以及在衬底202的主面202s的上方提供了绝缘层224内的多个伪栅电极210。保护一些伪栅电极210p和210r,同时去除其他伪栅电极210n、310p、310n和310r,使得可以代替伪栅电极210n、310p、310n和310r形成多个最终生成的金属栅极部件,即,可以代替伪栅电极210n形成N金属栅极部件,以及可以代替多个伪栅电极310p、310n和310r形成多个伪N金属栅极部件。然后,去除伪栅电极210p,使得可以代替伪栅电极210p形成P金属栅极部件。因此,不同金属栅极部件(即,P金属栅极部件和N金属栅极部件)的不均匀分布在用于后栅极工艺的化学机械抛光(CMP)期间引起负载效应,从而增加了器件不稳定和/或器件故障的可能性。
因此,以下参考图3C至图3F讨论的工艺可以通过控制栅极区域比来优化不同金属栅电极的分布。不同金属栅电极的优化分布对于后栅极工艺可以更加有效地防止CMP负载效应。因此,申请人的制造CMOS半导体管芯的方法可以有助于不同的金属栅电极保持它们的均匀性,从而达到CMOS性能。
图1中的方法100继续到步骤106,其中,通过以下工艺来制造图3C中的结构:去除多个伪栅电极210的第一子集(即,210p和310p)以形成第一组开口208p、308p以及任选地去除伪栅电极210r的第一部分210ra和第三部分210rc以形成第三组开口208a、208b。在所示实施例中,将图案化的感光层400用作掩模,去除多个伪栅电极210的第一子集(即,210p和310p)以形成第一组开口208p、308p,而去除伪栅电极210r的第一部分210ra和第三部分210rc以形成第三组开口208a、208b,同时通过图案化的感光层400覆盖伪栅电极210n、310n、310r和伪栅电极210r的第二部分210rb。
在一个实施例中,可以使用干蚀刻工艺去除多个伪栅电极210的第一子集(即,210p和310p)以及伪栅电极210r的第一部分210ra和第三部分210rc。在一个实施例中,可以将Cl2、HBr和He作为蚀刻气体,在大约650W至800W的电源功率、大约100W至120W的偏压功率和大约60mTorr至200mTorr的压力下实施干蚀刻工艺。此后可以剥离图案化的感光层400。
图1中的方法100继续到步骤108,其中,通过用第一金属材料218p填充第一组开口208p、308p以形成多个P金属栅极部件200p、300p(即,图2C中的P金属栅极区域200pb和伪P金属栅极区域300pb)来制造图3D中的结构。在一个实施例中,第一金属材料218p可以包括P功函金属。在一些实施例中,P功函金属包括从TiN、WN、TaN和Ru的组中选择的金属。P功函金属可以通过ALD、PVD、或其他适当技术来形成。在本实施例中,首先沉积第二金属材料218p以基本上填充第一组开口208p、308p和第三组开口208a、208b。然后,实施CMP工艺以去除第一组开口208p、308p和第三组开口208a、208b外的第一金属材料218p的一部分。因此,当到达绝缘层224时可以停止CMP工艺,由此提供基本上平坦的表面。
此外,参考图3D,用第一金属材料218p填充第三组开口208a、208b以形成包括多个电阻器区域200r的电阻器部件200r的导电接触件。在一个实施例中,多个电阻器区域200r包括多晶硅216。在另一实施例中,多个电阻器区域200r包括TiN214。此外,伪电阻器部件300r包括多个伪电阻器区域300r。在一个实施例中,多个伪电阻器区域300r包括多晶硅216。在另一实施例中,多个伪电阻器区域300r包括TiN214。
图1的方法110继续到步骤110,其中,通过去除多个伪栅电极210的第二子集(即,210n和310n)以形成第二组开口208n、308n来制造图3E中的结构。在所示实施例中,将图案化的感光层500用作掩模,去除多个伪栅电极210的第二子集(即,210n和310n)以形成第二组开口208n、308n,同时通过图案化的感光层500覆盖伪栅电极310r和伪栅电极210r的第二部分210rb。
在一个实施例中,可以使用干蚀刻工艺去除多个伪栅电极210的第二子集(即,210n和310n)。在一个实施例中,可以将Cl2、HBr和He作为蚀刻气体,在大约650W至800W的电源功率、大约100W至120W的偏压功率和大约60mTorr至200mTorr的压力下实施干蚀刻工艺。此后可以剥离图案化的感光层500。
图1的方法100继续到步骤112,其中,通过利用第二金属材料218n填充第二组开口208n、308n以形成多个N金属栅极部件200n、300n(即,图2C中的N金属栅极区域200nb和伪N金属栅极区域300nb)来制造图3F中的结构。在一个实施例中,第二金属材料218n可以包括N功函金属。在一些实施例中,N功函金属包括从Ti、Ag、Al、TiAl、TiAlN、TaC、TaCN、TaSiN、Mn和Zr的组中选择的材料。N功函金属可以通过ALD、PVD、溅射或其他适当技术来形成。在本实施例中,首先沉积第二金属材料218n以基本上填充第二组开口208n、308n。然后,实施CMP工艺以去除第二组开口208n、308n外的第二金属材料218n的一部分。因此,当到达绝缘层224时可以停止CMP工艺,由此提供基本上平坦的表面。
图4A至图4B示出了根据本发明内容的各个方面的图2A和图2B的示例性晶圆中的一个CMOS半导体管芯的一部分的可选俯视图。在所示实施例中,第二导电区域200b在绝缘层224内具有多个伪导电结构(例如,伪P金属栅极部件300p、伪N金属栅极部件300n等),其中,多个伪P金属栅极区域300p的每一个都可以具有与多个伪N金属栅极区域300n的每一个类似的形状和大小,其中,可以改变多个伪P金属栅极区域300p和多个伪N金属栅极区域300n的分布。
图5A至图5B示出了根据本发明内容的各个方面的图2A和图2B的示例性晶圆中的一个CMOS半导体管芯的一部分的可选俯视图。在所示实施例中,第二导电区域200b在绝缘层224内具有多个伪导电结构(例如,伪P金属栅极部件300p、伪N金属栅极部件300n等),其中,多个伪P金属栅极区域300p的每一个都可以具有与多个伪N金属区域300n的每一个不同的形状和大小,其中,可以改变多个伪P金属栅极区域300p和多个伪N金属栅极区域300n的分布。
应该理解,CMOS半导体管芯200可以经受进一步的CMOS工艺以形成各种部件,诸如接触件/通孔、互连金属层、介电层、钝化层等。
根据实施例,一种CMOS半导体管芯包括:衬底;绝缘层,位于衬底的主面的上方;多个P金属栅极区域,形成在绝缘层内,总体覆盖主面的第一区域;多个N金属栅极区域,形成在绝缘层内,总体覆盖主面的第二区域,其中,第一区域与第二区域的第一比率等于或大于1;多个伪P金属栅极区域,形成在绝缘层内,总体覆盖主面的第三区域;以及多个伪N金属栅极区域,形成在绝缘层内,总体覆盖主面的第四区域,其中,第三区域与第四区域的第二比率基本上等于第一比率。
根据其他实施例,一种CMOS半导体管芯包括:衬底;绝缘层,位于衬底的主面的上方;多个P金属栅极区域,形成在绝缘层内,总体覆盖主面的第一区域;多个N金属栅极区域,形成在绝缘层内,总体覆盖主面的第二区域,其中,第一区域与第二区域的第一比率等于或大于1;多个伪P金属栅极区域,形成在绝缘层内,总体覆盖主面的第三区域;多个伪N金属栅极区域,形成在绝缘层内,总体覆盖主面的第四区域,其中,第三区域与第四区域的第二比率基本上等于第一比率;多个电阻器区域,形成在绝缘层内,总体覆盖主面的第五区域,其中第五区域与第一区域和第二区域的总和的第三比率小于0.05;以及多个伪电阻器区域,形成在绝缘层内,总体覆盖主面的第六区域,其中第六区域与第三区域和第四区域的总和的第四比率小于0.05。
虽然通过实例和根据优选实施例描述本发明,但应该理解,本发明不限于所公开的实施例。相反,本发明用于覆盖各种修改和类似布置(如本领域的技术人员可以理解的)。因此,所附权利要求的范围应该符合最广泛的解释以包括所有这些修改和类似布置。
Claims (18)
1.一种CMOS半导体管芯,包括:
衬底;
绝缘层,位于所述衬底的主面的上方;
多个P金属栅极区域,形成在所述绝缘层内,总体覆盖所述主面的第一区域;
多个N金属栅极区域,形成在所述绝缘层内,总体覆盖所述主面的第二区域,其中,所述第一区域与所述第二区域的第一比率等于或大于1;
多个伪P金属栅极区域,形成在所述绝缘层内,总体覆盖所述主面的第三区域;以及
多个伪N金属栅极区域,形成在所述绝缘层内,总体覆盖所述主面的第四区域,其中,所述第三区域与所述第四区域的第二比率等于所述第一比率,其中所述多个伪P金属栅极区域的每一个的大小类似并且所述多个伪N金属栅极区域的每一个的大小类似。
2.根据权利要求1所述的CMOS半导体管芯,其中,所述第一比率在1至3的范围内。
3.根据权利要求1所述的CMOS半导体管芯,其中,所述第二比率在1至3的范围内。
4.根据权利要求1所述的CMOS半导体管芯,其中,所述多个伪P金属栅极区域的每一个都具有与其他伪P金属栅极区域类似的形状。
5.根据权利要求1所述的CMOS半导体管芯,其中,所述多个伪N金属栅极区域的每一个都具有与其他伪N金属栅极区域类似的形状。
6.根据权利要求1所述的CMOS半导体管芯,其中,所述多个伪P金属栅极区域的每一个都具有与所述多个伪N金属栅极区域的每一个类似的形状。
7.根据权利要求1所述的CMOS半导体管芯,其中,所述多个伪P金属栅极区域的每一个都具有与所述多个伪N金属栅极区域的每一个类似的大小。
8.根据权利要求1所述的CMOS半导体管芯,其中,所述多个伪N金属栅极区域的一个位于两个伪P金属栅极区域之间。
9.根据权利要求1所述的CMOS半导体管芯,其中,所述多个伪P金属栅极区域的一个位于两个伪N金属栅极区域之间。
10.根据权利要求1所述的CMOS半导体管芯,其中,所述多个伪N金属栅极区域的一个位于所述伪P栅极区域中的一个和所述多个P金属栅极区域中的一个之间。
11.根据权利要求1所述的CMOS半导体管芯,其中,所述多个伪P金属栅极区域的一个位于所述伪N栅极区域中的一个和所述多个N金属栅极区域中的一个之间。
12.根据权利要求1所述的CMOS半导体管芯,其中,所述多个伪P金属栅极区域包括从由TiN、WN、TaN和Ru组成的组中所选择的金属。
13.根据权利要求1所述的CMOS半导体管芯,其中,所述多个伪N金属栅极区域包括从由Ti、Ag、Al、TiAl、TiAlN、TaC、TaCN、TaSiN、Mn和Zr组成的组中所选择的金属。
14.根据权利要求1所述的CMOS半导体管芯,还包括:
多个电阻器区域,形成在所述绝缘层内,总体覆盖所述主面的第五区域,以及
多个伪电阻器区域,形成在所述绝缘层内,总体覆盖所述主面的第六区域。
15.根据权利要求14所述的CMOS半导体管芯,其中,所述第五区域与所述第一区域和所述第二区域的总和的第三比率小于0.05。
16.根据权利要求14所述的CMOS半导体管芯,其中,所述第六区域与所述第三区域和所述第四区域的总和的第四比率小于0.05。
17.根据权利要求14所述的CMOS半导体管芯,其中,所述多个伪电阻器区域包括多晶硅。
18.根据权利要求14所述的CMOS半导体管芯,其中,所述多个伪电阻器区域包括TiN。
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WO2020146030A1 (en) * | 2019-01-09 | 2020-07-16 | Applied Materials, Inc. | Hydrogenation and nitridization processes for modifying effective oxide thickness of a film |
US11257816B2 (en) * | 2019-08-20 | 2022-02-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for manufacturing semiconductor device including dummy gate electrodes |
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US20150194352A1 (en) | 2015-07-09 |
US20160093610A1 (en) | 2016-03-31 |
US20130140641A1 (en) | 2013-06-06 |
CN103151353A (zh) | 2013-06-12 |
TW201324745A (zh) | 2013-06-16 |
TWI523198B (zh) | 2016-02-21 |
KR20130063443A (ko) | 2013-06-14 |
US9006860B2 (en) | 2015-04-14 |
US9209090B2 (en) | 2015-12-08 |
US9515069B2 (en) | 2016-12-06 |
KR101338664B1 (ko) | 2013-12-06 |
US20170084608A1 (en) | 2017-03-23 |
US10672760B2 (en) | 2020-06-02 |
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