TWI523149B - 半導體製造製程及形成半導體器件之方法 - Google Patents

半導體製造製程及形成半導體器件之方法 Download PDF

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Publication number
TWI523149B
TWI523149B TW098145608A TW98145608A TWI523149B TW I523149 B TWI523149 B TW I523149B TW 098145608 A TW098145608 A TW 098145608A TW 98145608 A TW98145608 A TW 98145608A TW I523149 B TWI523149 B TW I523149B
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Taiwan
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layer
dielectric
dielectric layer
region
gate
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TW098145608A
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English (en)
Chinese (zh)
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TW201034126A (en
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羅天英
高瑞Ｖ 卡夫
丹尼爾Ｇ 帖克里
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飛思卡爾半導體公司
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0278—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline channels on wafers after forming insulating device isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0181—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/665—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
    • H10D64/666—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum the conductor further comprising additional layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
TW098145608A 2009-01-21 2009-12-29 半導體製造製程及形成半導體器件之方法 TWI523149B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/357,057 US8017469B2 (en) 2009-01-21 2009-01-21 Dual high-k oxides with sige channel

Publications (2)

Publication Number Publication Date
TW201034126A TW201034126A (en) 2010-09-16
TWI523149B true TWI523149B (zh) 2016-02-21

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TW098145608A TWI523149B (zh) 2009-01-21 2009-12-29 半導體製造製程及形成半導體器件之方法

Country Status (6)

Country Link
US (2) US8017469B2 (enExample)
EP (1) EP2389684A2 (enExample)
JP (1) JP5582582B2 (enExample)
CN (1) CN102292800B (enExample)
TW (1) TWI523149B (enExample)
WO (1) WO2010088039A2 (enExample)

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010147104A (ja) * 2008-12-16 2010-07-01 Toshiba Corp 半導体装置の製造方法
KR101589440B1 (ko) * 2009-02-09 2016-01-29 삼성전자주식회사 듀얼 게이트 반도체 장치의 제조 방법
US8048791B2 (en) * 2009-02-23 2011-11-01 Globalfoundries Inc. Method of forming a semiconductor device
US8076730B2 (en) * 2009-06-09 2011-12-13 Infineon Technologies Ag Transistor level routing
CN101964345B (zh) * 2009-07-22 2013-11-13 中国科学院微电子研究所 控制阈值电压特性的CMOSFETs器件结构及其制造方法
US8105892B2 (en) * 2009-08-18 2012-01-31 International Business Machines Corporation Thermal dual gate oxide device integration
US8278165B2 (en) * 2009-10-12 2012-10-02 GlobalFoundries, Inc. Methods for protecting film layers while removing hardmasks during fabrication of semiconductor devices
KR20120107762A (ko) * 2011-03-22 2012-10-04 삼성전자주식회사 반도체 소자의 제조 방법
US20120319207A1 (en) * 2011-06-17 2012-12-20 Toshiba America Electronic Components, Inc. Semiconductor device with threshold voltage control and method of fabricating the same
CN102856204B (zh) * 2011-06-29 2016-04-20 中芯国际集成电路制造(上海)有限公司 晶体管及其形成方法
CN102856203B (zh) * 2011-06-29 2015-04-29 中芯国际集成电路制造(上海)有限公司 Mos晶体管及其形成方法
US8703594B2 (en) * 2011-10-25 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having a treated gate structure and fabrication method thereof
US9087687B2 (en) 2011-12-23 2015-07-21 International Business Machines Corporation Thin heterostructure channel device
US20130277766A1 (en) * 2012-04-23 2013-10-24 Globalfoundries Inc. Multiple high-k metal gate stacks in a field effect transistor
US9029959B2 (en) * 2012-06-29 2015-05-12 International Business Machines Corporation Composite high-k gate dielectric stack for reducing gate leakage
US9136177B2 (en) * 2012-07-30 2015-09-15 Globalfoundries Inc. Methods of forming transistor devices with high-k insulation layers and the resulting devices
US8890264B2 (en) * 2012-09-26 2014-11-18 Intel Corporation Non-planar III-V field effect transistors with conformal metal gate electrode and nitrogen doping of gate dielectric interface
US9064726B2 (en) * 2013-03-07 2015-06-23 Texas Instruments Incorporated Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure
KR102054834B1 (ko) 2013-03-15 2019-12-12 삼성전자주식회사 반도체 메모리 소자 및 그 제조 방법
US9087716B2 (en) * 2013-07-15 2015-07-21 Globalfoundries Inc. Channel semiconductor alloy layer growth adjusted by impurity ion implantation
US9373691B2 (en) * 2013-08-07 2016-06-21 GlobalFoundries, Inc. Transistor with bonded gate dielectric
EP3748684B1 (en) * 2013-09-27 2022-06-08 INTEL Corporation Semiconductor device having group iii-v material active region and graded gate dielectric
EP3832710B1 (en) * 2013-09-27 2024-01-10 INTEL Corporation Non-planar i/o and logic semiconductor devices having different workfunction on common substrate
US20150140838A1 (en) * 2013-11-19 2015-05-21 Intermolecular Inc. Two Step Deposition of High-k Gate Dielectric Materials
US9590037B2 (en) 2014-03-19 2017-03-07 International Business Machines Corporation p-FET with strained silicon-germanium channel
US9627608B2 (en) * 2014-09-11 2017-04-18 Lam Research Corporation Dielectric repair for emerging memory devices
FR3030882B1 (fr) 2014-12-22 2018-03-09 Commissariat A L'energie Atomique Et Aux Energies Alternatives Circuit integre comportant des transistors pmos a tensions de seuil distinctes
KR102365687B1 (ko) 2015-04-21 2022-02-21 삼성전자주식회사 집적회로 소자 및 그 제조 방법
KR102395061B1 (ko) * 2015-07-02 2022-05-10 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR20170036966A (ko) 2015-09-24 2017-04-04 삼성전자주식회사 반도체 소자의 제조하는 방법
US9735061B1 (en) * 2016-02-03 2017-08-15 Globalfoundries Inc. Methods to form multi threshold-voltage dual channel without channel doping
US20180233574A1 (en) * 2017-02-10 2018-08-16 Purdue Research Foundation Silicon carbide power transistor apparatus and method of producing same
US10002939B1 (en) 2017-02-16 2018-06-19 International Business Machines Corporation Nanosheet transistors having thin and thick gate dielectric material
DE102018107908B4 (de) 2017-07-28 2023-01-05 Taiwan Semiconductor Manufacturing Co., Ltd. Verfahren zum Bilden eines integrierten Schaltkreises mit einer Versiegelungsschicht zum Bilden einer Speicherzellenstruktur in Logik- oder BCD-Technologie sowie ein integrierter Schaltkreis mit einer Dummy-Struktur an einer Grenze einer Vorrichtungsregion
US10504912B2 (en) 2017-07-28 2019-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Seal method to integrate non-volatile memory (NVM) into logic or bipolar CMOS DMOS (BCD) technology
KR20190034822A (ko) * 2017-09-25 2019-04-03 삼성전자주식회사 반도체 장치
FR3091622B1 (fr) * 2019-01-09 2021-09-17 Soitec Silicon On Insulator Structure semi-conductrice optoélectronique comprenant une couche d’injection de type p à base d’InGaN
KR102714154B1 (ko) * 2019-03-25 2024-10-07 삼성전자주식회사 반도체 장치의 제조 방법
CN110556341B (zh) * 2019-09-25 2022-02-01 上海华力集成电路制造有限公司 半导体器件的制造方法
CN114765132A (zh) * 2021-01-11 2022-07-19 长鑫存储技术有限公司 半导体结构制作方法及半导体结构
EP4053891A4 (en) 2021-01-11 2023-01-04 Changxin Memory Technologies, Inc. METHOD OF MAKING A SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE
EP4276894A4 (en) 2021-01-11 2024-07-10 Changxin Memory Technologies, Inc. METHOD FOR PRODUCING A SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6787421B2 (en) 2002-08-15 2004-09-07 Freescale Semiconductor, Inc. Method for forming a dual gate oxide device using a metal oxide and resulting device
US6921913B2 (en) 2003-03-04 2005-07-26 Taiwan Semiconductor Manufacturing Co., Ltd. Strained-channel transistor structure with lattice-mismatched zone
TWI258811B (en) 2003-11-12 2006-07-21 Samsung Electronics Co Ltd Semiconductor devices having different gate dielectrics and methods for manufacturing the same
US7662689B2 (en) 2003-12-23 2010-02-16 Intel Corporation Strained transistor integration for CMOS
JP4542807B2 (ja) * 2004-03-31 2010-09-15 東京エレクトロン株式会社 成膜方法および成膜装置、ならびにゲート絶縁膜の形成方法
US8399934B2 (en) * 2004-12-20 2013-03-19 Infineon Technologies Ag Transistor device
US20060157732A1 (en) * 2004-11-09 2006-07-20 Epispeed Sa Fabrication of MOS-gated strained-Si and SiGe buried channel field effect transistors
US7564108B2 (en) 2004-12-20 2009-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Nitrogen treatment to improve high-k gate dielectrics
JP4588483B2 (ja) * 2005-02-21 2010-12-01 ルネサスエレクトロニクス株式会社 半導体装置
US7524707B2 (en) * 2005-08-23 2009-04-28 Freescale Semiconductor, Inc. Modified hybrid orientation technology
TWI267926B (en) * 2005-09-23 2006-12-01 Ind Tech Res Inst A new method for high mobility enhancement strained channel CMOS with single workfunction metal-gate
US7265004B2 (en) 2005-11-14 2007-09-04 Freescale Semiconductor, Inc. Electronic devices including a semiconductor layer and a process for forming the same
DE102006025218B4 (de) 2006-05-29 2009-02-19 Infineon Technologies Austria Ag Leistungshalbleiterbauelement mit Ladungskompensationsstruktur und Verfahren zur Herstellung desselben
JP4282691B2 (ja) * 2006-06-07 2009-06-24 株式会社東芝 半導体装置
US7709331B2 (en) 2007-09-07 2010-05-04 Freescale Semiconductor, Inc. Dual gate oxide device integration
US8460996B2 (en) 2007-10-31 2013-06-11 Freescale Semiconductor, Inc. Semiconductor devices with different dielectric thicknesses
JP2009229117A (ja) 2008-03-19 2009-10-08 Omron Healthcare Co Ltd 電子体温計
JP5203905B2 (ja) * 2008-12-02 2013-06-05 株式会社東芝 半導体装置およびその製造方法

Also Published As

Publication number Publication date
US8017469B2 (en) 2011-09-13
US20100184260A1 (en) 2010-07-22
WO2010088039A2 (en) 2010-08-05
CN102292800B (zh) 2015-05-20
JP2012516036A (ja) 2012-07-12
JP5582582B2 (ja) 2014-09-03
CN102292800A (zh) 2011-12-21
EP2389684A2 (en) 2011-11-30
WO2010088039A3 (en) 2010-09-30
USRE45955E1 (en) 2016-03-29
TW201034126A (en) 2010-09-16

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